CN117406552A - Layout method and device of alignment marks - Google Patents

Abstract

The application provides a layout method and a device of an alignment mark, wherein the layout method of the alignment mark comprises the following steps: acquiring the placing requirement of the alignment mark; determining frame parameters of the wafer; determining design parameters of the alignment mark; generating an alignment mark layout structure according to the frame parameters of the wafer, the design parameters of the alignment mark and the placement requirements of the alignment mark. The layout method of the alignment mark can automatically generate the alignment mark layout structure, has high efficiency and reasonable placement position of the alignment mark, and can improve the alignment efficiency and accuracy of the photomask, thereby improving the productivity of chips.

Description

Layout method and device of alignment marks

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a layout method and apparatus for alignment marks.

Background

In semiconductor manufacturing, the photolithography process is the most important circuit pattern transfer process. Photolithography is the process of transferring a pattern on a Mask (Mask) onto a wafer by exposure and development.

In order to transfer the pattern on the mask onto the wafer correctly, a key step is to ensure the overlay accuracy between different layers (layers) to meet the requirements of lithography accuracy. The common alignment method is to use alignment marks on a photomask to align the film layers of the wafer through a specific position alignment device in the equipment. Since the semiconductor device generally has a plurality of mask processes, the number of alignment marks to be matched is large, and the layout structure of the alignment marks required by all masks is generally designed in advance.

However, in the prior art, the alignment mark is generally set by manual calculation, which is inefficient and has errors, resulting in long exposure alignment time and affecting the productivity of the semiconductor device.

Disclosure of Invention

In order to solve at least one problem in the background art, the invention provides a layout method and a layout device for an alignment mark, which can automatically generate an alignment mark layout structure, has high efficiency and reasonable alignment mark placement position, and can improve the productivity of chips.

In order to achieve the above object, the present application provides the following technical solutions:

in one aspect, the present application provides a layout method of alignment marks, including:

acquiring the placing requirement of the alignment mark;

determining frame parameters of the wafer;

determining design parameters of the alignment mark;

generating an alignment mark layout structure according to the frame parameters of the wafer, the design parameters of the alignment mark and the placement requirements of the alignment mark.

In one possible embodiment, the wafer includes a plurality of dies arranged in an array and scribe lines between the dies;

the alignment marks are arranged in the scribing grooves and comprise a plurality of groups of alignment marks corresponding to each photomask, and each group of alignment marks comprises a transverse alignment mark and a vertical alignment mark.

In one possible embodiment, the positioning requirements of the alignment mark include:

and in each group of alignment marks, the center distance between the transverse alignment mark and the vertical alignment mark is smaller than or equal to a first preset value.

In one possible implementation, the positioning requirements of the alignment mark further include:

the distance between the edge of the alignment mark and the groove wall of the scribing groove is larger than or equal to a second preset value.

In one possible implementation, the positioning requirements of the alignment mark further include:

in the same scribing groove, the distance between adjacent alignment marks is larger than or equal to a third preset value.

In one possible embodiment, before generating the alignment mark layout structure, the method further includes:

generating a preliminary alignment mark layout structure according to the frame parameters of the wafer, the design parameters of the alignment marks and the placement requirements of the alignment marks;

judging whether each group of alignment marks in the preliminary alignment mark layout structure meets a first preset value in the placement requirement or not;

and adjusting each group of alignment marks which do not meet the first preset value until all the alignment marks meet the placing requirement, and generating an alignment mark layout structure.

In one possible embodiment, adjusting the sets of alignment marks that do not meet the first preset value includes:

And adjusting the transverse alignment coordinates and/or the vertical alignment marks in the same group of alignment marks until the center distance between the transverse alignment marks and the vertical alignment marks in the same group of alignment marks is smaller than or equal to the first preset value.

In one possible embodiment, adjusting the lateral alignment marks in the same set of alignment marks includes:

determining a scribing groove in which the transverse alignment mark is positioned as a current scribing groove, and adjusting the position of the transverse alignment mark in the current scribing groove;

adjusting the scribing groove in which the transverse alignment mark is positioned, and adjusting the scribing groove close to the vertical alignment mark by taking the current scribing groove as an original point;

until the center distance between the transverse alignment mark and the vertical alignment mark is smaller than or equal to the first preset value.

In a possible implementation manner, the adjusting the lateral alignment marks in the same group of alignment marks further includes: after the scribing groove where the transverse alignment mark is positioned is adjusted each time, the position of the transverse alignment mark is continuously adjusted in the adjusted scribing groove.

In one possible embodiment, adjusting the vertical alignment marks in the same set of alignment marks includes:

determining a scribing groove in which the vertical alignment mark is positioned as a current scribing groove, and adjusting the position of the vertical alignment mark in the current scribing groove;

Adjusting the scribing groove in which the vertical alignment mark is positioned, and adjusting the scribing groove close to the transverse alignment mark by taking the current scribing groove as an original point;

until the center distance between the vertical alignment mark and the horizontal alignment mark is smaller than or equal to the first preset value.

In one possible embodiment, adjusting the vertical alignment marks in the same set of alignment marks further comprises: after the scribing groove where the vertical alignment mark is located is adjusted each time, the position of the vertical alignment mark is continuously adjusted in the adjusted scribing groove.

In one possible embodiment, after adjusting each set of alignment marks that do not meet the first preset value, before generating the alignment mark layout structure, the method further includes:

judging a second preset value and a third preset value for the adjusted alignment mark, and adjusting the position of the alignment mark if the second preset value is not met; and if the third preset value is not met, adjusting the positions of the alignment marks or the adjacent alignment marks.

In one possible embodiment, obtaining frame parameters of a wafer includes:

and obtaining the design size of the chip, the design size of the scribing groove and the exposure area layout.

In one possible implementation, obtaining design parameters of the alignment mark includes:

The number and shape of the alignment marks are obtained.

In another aspect, the present application provides a layout apparatus of alignment marks, including:

the acquisition module is used for acquiring the placement requirement of the alignment mark;

the determining module is used for determining frame parameters of the wafer;

the determining module is also used for determining design parameters of the alignment mark;

and the output module is used for generating an alignment mark layout structure according to the frame parameters of the wafer, the design parameters of the alignment mark and the placement requirements of the alignment mark.

According to the layout method and device of the alignment marks, the layout method of the alignment marks automatically generates the layout structure of the alignment marks by acquiring the layout requirements of the alignment marks and automatically planning the layout positions of the alignment marks and the distances between different alignment marks according to the frame parameters of the wafer and the design parameters of the alignment marks. On the basis of ensuring that the alignment marks are in sufficient quantity, the efficiency of the alignment mark layout is improved, the rationality of the alignment mark layout is ensured, and the efficiency and the accuracy of the photomask alignment can be improved, so that the productivity and the performance of chips are improved.

The construction of the present application, as well as other objects and advantages thereof, will be more readily understood from the description of the preferred embodiments taken in conjunction with the accompanying drawings.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention. Other figures may be derived from these figures without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a flowchart illustrating steps of a layout method of alignment marks according to an embodiment of the present disclosure;

fig. 2 is a frame structure diagram of a wafer according to an embodiment of the present application;

FIG. 3 is a schematic layout diagram of a set of alignment marks according to an embodiment of the present disclosure;

fig. 4a is a schematic structural diagram of a first alignment mark according to an embodiment of the present application;

FIG. 4b is a schematic structural diagram of a second alignment mark according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a manner of adjusting a distance between a lateral alignment mark and a vertical alignment mark according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of an alignment manner of an alignment mark according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of another alignment method of the alignment mark according to the embodiment of the present application;

Fig. 8 is a schematic diagram of a layout device of alignment marks according to an embodiment of the present application.

Reference numerals illustrate:

100-wafer;

110-chip; 120-dicing grooves;

200-aligning marks;

200 a-a first alignment mark; 200 b-a second alignment mark;

210-lateral alignment marks; 220-vertical alignment marks;

201-grating group;

2011-grating;

300-layout means;

310-an acquisition module; 320-a determination module; 330-output module.

Detailed Description

In the process of manufacturing semiconductor chips, photolithography is the most important process, and the quality of the photolithography process directly affects the performance of the finally formed chips. The photolithography process is to copy a pattern on a photomask to a wafer coated with photoresist by exposure, and then to etch the pattern on the photomask to the wafer by development, post baking, electroplating, ball returning, and the like.

In the fabrication of integrated circuits (integrated circuit, ICs), a complete chip is typically subjected to several tens to twenty times of lithography, in which multiple lithography, the remaining levels of lithography align the pattern of the level with the pattern left by the previous level before exposure, except for the first lithography which is directly aligned with the wafer. Thus, alignment accuracy will directly affect product quality, and alignment speed and efficiency will affect product production efficiency.

In order to ensure the photoetching precision, before the photoetching process is carried out, alignment marks are arranged in each layer of the wafer, and each layer is aligned according to the alignment marks. Before the pattern on the next photomask is exposed, the position distance between the alignment mark of the photomask and the alignment mark of the last photomask needs to be measured and adjusted, and the alignment mark meets the alignment requirement, and then the exposure and other operations are performed to realize the precise alignment between different layers of patterns.

In order to ensure alignment accuracy, a large number of alignment marks are usually designed for each photomask, and for a wafer which needs to undergo tens to twenty times of lithography, the number of alignment marks to be finally formed on the wafer is large. Because the number of alignment marks to be formed on the wafer is numerous, the layout design of the alignment marks needs to be performed in advance, and the positions of the alignment marks on the wafer are planned in advance, so that the alignment marks to be aligned for the subsequent photomask can be etched rapidly and accurately while the circuit patterns of each layer are formed on the wafer.

Taking a step-and-scan type photolithography machine with two machine stations as an example, one machine station of the photolithography machine is an alignment machine station for aligning a current photomask and a photomask of the upper layer, and the other machine station is an exposure machine station for exposing a pattern on the photomask on a wafer. In order to increase productivity, the alignment machine is generally required to perform faster than the exposure machine, and for faster alignment, the number of alignment marks is generally reduced in the related art, so as to save alignment time and improve alignment efficiency. However, reducing the number of alignment marks reduces alignment accuracy, affecting chip yield and performance.

In view of this, the present embodiment provides a layout method and apparatus for alignment marks, where the layout method for alignment marks automatically generates an alignment mark layout structure by setting a placement rule for alignment marks, and according to a frame parameter of a wafer and a design parameter of the alignment marks. On the basis of ensuring that the alignment marks with enough quantity are provided, the efficiency of the alignment mark layout is improved, the accuracy of the alignment mark placement is improved, and meanwhile, the alignment time of a machine is shortened by clamping and controlling the distance between two alignment marks in the alignment mark group, so that the productivity and the performance of chips are improved.

Fig. 1 is a flowchart of steps of a layout method of alignment marks according to an embodiment of the present application. Referring to fig. 1, the layout method of the alignment mark includes the steps of:

s100, acquiring the placement requirement of the alignment mark.

Fig. 2 is a frame structure diagram of a wafer according to an embodiment of the present application. Referring to fig. 2, wafer 100 is a silicon wafer used for manufacturing a silicon semiconductor integrated circuit, and is referred to as wafer 100 because it is generally circular in shape. A plurality of chips 110 are arranged in an array on the wafer 100, and the chips 110 are separated from each other by scribe lines 120.

Various circuit element structures are fabricated on the wafer 100 in regions corresponding to the chips 110, for example, semiconductor devices fabricated on the chips 110 include diodes, transistors, field effect transistors, low power resistors, inductors, capacitors, and the like. After the semiconductor devices on the chips 110 are processed, dicing is performed along the dicing channels 120 to separate the chips 110 from the wafer 100 to form individual chips 110 containing integrated circuits.

It will be appreciated that, for simplicity of illustration, the scribe lines 120 between the chips 110 are shown in a linear configuration in fig. 2, and in fact, the scribe lines 120 are of a groove configuration having a certain width and depth so that, after dicing along the scribe lines 120, a regular and uniform shape of the chips 110 can be formed.

As described above, in order to process the semiconductor device on the chip 110 of the wafer 100, a plurality of photolithography processes are required, each of which is to cover the wafer 100 with a mask having a corresponding pattern, align the mask with the wafer 100, and re-etch the pattern on the mask on each chip 110 of the wafer 100 through steps such as exposure, development, and the like. Thus, the pattern of the semiconductor device is mainly disposed in the region corresponding to the chip 110 on the mask, and in order to prevent the pattern of the alignment mark 200 from interfering with the pattern of the semiconductor device, the pattern of the alignment mark 200 is generally disposed in the region other than the region corresponding to the chip 110 on the mask, for example, the alignment mark 200 is disposed in the scribe line 120 between the chips 110, and the alignment mark 200 disposed in the scribe line 120 is aligned with the surface of the wafer 100 where the previous process is completed.

Since ten to twenty masks are required to form a complete integrated circuit structure on the chip 110, in order to ensure alignment accuracy, a plurality of alignment marks 200 are usually disposed between each mask and the wafer 100 for alignment, and a plurality of alignment marks 200 are required to be disposed on the plurality of masks. As described above, the required alignment mark 200 pattern is formed on each mask, and when each mask is exposed and developed on the wafer 100, the alignment mark 200 pattern on each mask is transferred to the corresponding position in the scribe line 120 on the wafer 100, so that the subsequent mask can be aligned with respect to the alignment mark 200 formed on the wafer 100 by the previous mask.

With continued reference to fig. 2, for the case where the chips 110 are arrayed on the wafer 100 and the scribe lines 120 between the chips 110 extend in the X-axis direction and the Y-axis direction in the drawing, for convenience and accuracy in aligning the mask with the wafer 100, the alignment marks 200 are generally arranged along the extending direction of the scribe lines 120, and the alignment marks 200 are generally arranged in groups to ensure alignment accuracy in both the X-axis direction and the Y-axis direction.

Fig. 3 is a schematic layout diagram of a set of alignment marks according to an embodiment of the present application. Referring to fig. 3, taking a set of alignment marks 200 disposed in the scribe line 120 of the wafer 100 as an example, each set of alignment marks 200 includes a lateral alignment mark 210 and a vertical alignment mark 220, the lateral alignment mark 210 is located in the scribe line 120 in the X-axis direction, the lateral alignment mark 210 extends in the X-axis direction, the vertical alignment mark 220 is located in the scribe line 120 in the Y-axis direction, and the vertical alignment mark 220 extends in the Y-axis direction.

Taking one mask alignment as an example, the track of mask needs to be aligned with the previous mask, the lateral alignment mark 210 of the track of mask aligns with the lateral alignment mark 210 formed on the wafer 100 by the previous mask, and the vertical alignment mark 220 of the track of mask aligns with the vertical alignment mark 220 formed on the wafer 100 by the previous mask. By aligning the mask in the X-axis direction and the Y-axis direction, the mask can be precisely positioned.

In this regard, the wafer 100 is going through multiple masks, and multiple sets of alignment marks 200 are disposed on each mask, so that the number of alignment marks 200 formed on the wafer 100 is large, and each mask refers to the alignment marks 200 left in the scribe line 120 on the wafer 100 by the previous mask when aligned, and the positions of the alignment marks 200 formed on the wafer 100 and used as reference targets by the previous mask affect the alignment efficiency, alignment accuracy, etc. of the subsequent masks. Therefore, it is necessary to perform layout design in advance for the alignment marks 200 in the scribe line 120 to be formed on the wafer 100.

In the related art, the positions of all the alignment marks 200 are usually manually calculated and designed to form the layout structure of the alignment marks 200. However, the manual calculation is inefficient, and there is an error, if the position of the alignment mark 200 is not properly placed in the process, the time is wasted due to the recalculation and redesign, and the layout of the alignment mark 200 is inefficient. If the layout structure of the alignment mark 200 is not properly designed, the mask manufactured according to the design is not suitable, which may further result in the problems of mask discard, chip 110 yield reduction, etc.

In this embodiment, by acquiring the placement requirements of the alignment marks 200, automatically planning and laying out the placement positions of the alignment marks 200 and the distances between different alignment marks 200, and automatically adjusting the placement positions, the distances and other parameters of the alignment marks 200 according to the placement requirements of the alignment marks 200, the layout efficiency of the alignment marks 200 can be improved, the layout rationality of the alignment marks 200 can be ensured, and the layout structure of the alignment marks 200 can be improved. Therefore, the alignment efficiency of the photomask can be improved, the alignment accuracy of the photomask can be improved, and the productivity of the chip 110 can be improved.

S200, determining frame parameters of the wafer.

As described above, all the alignment marks 200 are disposed in the scribe line 120 on the wafer 100, so the frame parameters of the wafer 100 need to be obtained before designing the layout structure of the alignment marks 200, and the alignment marks 200 are placed in the scribe line 120 according to the frame parameters of the wafer 100.

The frame parameters of the wafer 100 include the design dimensions of the chips 110 and the design dimensions of the scribe lines 120, and the design dimensions of the chips 110 and the scribe lines 120 need to be obtained before the layout structure of the alignment mark 200 is designed, for the chips 110 and the scribe lines 120 arranged in the frame structure of the wafer 100 for the array and the scribe lines 120 separated between the chips 110. For example, the design dimensions of the chips 110 may include the size of the area of each chip 110 (e.g., the length and width of the chips 110), and the design dimensions of the scribe line 120 may include the width of the scribe line 120.

The frame structure of the wafer 100 is generated according to the area (length and width) of the chip 110 and the width of the scribe line 120, and the alignment mark 200 is laid out in the scribe line 120 on the wafer 100.

S300, determining design parameters of the alignment marks.

As described above, a plurality of masks are required from the initial formation of the chips 110 on the wafer 100 to the final formation of the plurality of semiconductor devices in the chips 110, and in order to secure alignment accuracy, a plurality of sets of alignment marks 200 are provided on each mask, and each set of alignment marks 200 includes a lateral alignment mark 210 and a vertical alignment mark 220. Therefore, it is necessary to obtain the design parameters of the alignment mark 200 first, and perform the design layout of the alignment mark 200 according to the design parameters of the alignment mark 200.

The design parameters of the alignment marks 200 include the number of alignment marks 200, for example, the total number of alignment marks 200 of all masks, i.e., the total number of alignment marks 200 to be finally formed on the wafer 100, and the number of alignment marks 200 per mask.

In addition, the design parameters of the alignment mark 200 may also include the shape of the alignment mark 200. In order to facilitate the alignment mark 200 to be positioned by the lithography machine, especially in the case of a large number of alignment marks 200, the alignment marks 200 with different shapes can be designed, and the alignment marks 200 can be placed in the empty areas of the scribe line 120 with different sizes and can be aligned with different process precision, so that the lithography machine can more quickly determine the positions of the alignment marks 200. Therefore, the shape of the alignment mark 200 needs to be acquired before designing the layout alignment mark 200. For example, the alignment mark 200 may include two different shapes, and the alignment marks 200 of the two different shapes are respectively defined as a first alignment mark 200a and a second alignment mark 200b.

Fig. 4a is a schematic structural diagram of a first alignment mark provided in this embodiment of the present application, referring to fig. 4a, a center of the first alignment mark 200a is provided with a cross-shaped center positioning mark, two sides of the center are spaced by a plurality of grating groups 201, each grating group 201 includes, for example, a plurality of gratings 2011 (three in the drawing as an example) that are equidistantly spaced, the gratings 2011 extend along a width direction of the alignment mark 200, a distance d1 between centers of adjacent grating groups 201 on one side of the center and a distance d2 before the center of adjacent grating groups 201 on the other side of the center are unequal, for example, d1 is 16 μm, and d2 is 17.6 μm. The first alignment marks 200a may be used in different mask alignments to determine a single direction offset in the X-direction or the Y-direction, while two first alignment marks 200a in different directions may be used to determine an offset in the X-direction and the Y-direction.

Fig. 4b is a schematic structural diagram of a second alignment mark provided in this embodiment, and referring to fig. 4b, the gratings 2011 of the second alignment mark 200b extend obliquely, the inclination angle of the gratings 2011 is, for example, 45 °, the gratings 2011 are equidistantly spaced, and the spacing L0 between adjacent gratings 2011 in the X-axis direction and the Y-direction is, for example, 3.2 μm. The offset in the X-direction and the Y-direction is obtained by calculating the center coordinates and the tilt angle using a second alignment mark 200b in a different photomask.

For the present embodiment, by disposing multiple sets of alignment marks 200 on each mask, the alignment marks 200 are mainly used for realizing the precise alignment between the mask and a layer of mask on the wafer 100, and the shape of the alignment marks 200 in fig. 4a and 4b can precisely position the mask by precisely designing parameters such as the width, the pitch, the inclination degree, and the like of the grating 2011. For one mask, the alignment marks 200 of the mask may be the first alignment mark 200a or the second alignment mark 200b, or the first alignment mark 200a and the second alignment mark 200b are included in the alignment marks 200 of the mask, which are specifically set according to the process precision requirement and the size of the scribe line empty area.

For each set of alignment marks 200, the alignment marks 200 of the same shape may be selected for the lateral alignment marks 210 and the vertical alignment marks 220 in the set of alignment marks 200, for example, the lateral alignment marks 210 and the vertical alignment marks 220 in the set of alignment marks 200 are both the first alignment marks 200a or both the second alignment marks 200b.

S400, generating an alignment mark layout structure according to the frame parameters of the wafer, the design parameters of the alignment mark and the placement rules of the alignment mark.

The frame parameters of the wafer 100 include: the design dimensions of the chip 110 and the design dimensions of the scribe line 120, and the exposure area layout.

Design parameters of the alignment mark 200 include: the number and shape of the alignment marks 200.

The frame parameters of the wafer 100 and the design parameters of the alignment mark 200 are determined, and the layout structure of the alignment mark 200 can be automatically generated according to the set placement rules of the alignment mark 200.

Such as: the layout of the exposure area comprises a specific structure of the chip 110 and a specific structure in the scribing groove 120, the photoetching process precision is determined according to the structure of the chip 110, and the shape of the alignment mark 200 meeting the precision requirement is selected. The position and the size of the blank area in the scribe line 120 are identified according to the size of the scribe line 120 and the size of the chip 110, and the blank area suitable for placing the alignment mark is determined. The required number of alignment marks 200 are randomly distributed in the screened blank area, wherein the transverse alignment marks 210 are arranged in the scribing grooves 120 extending in the X direction, the vertical alignment marks 220 are arranged in the scribing grooves 120 extending in the Y direction, a preliminary alignment mark layout structure can be obtained, each alignment mark 200 is detected one by one according to the arrangement requirement of the alignment mark 200, the alignment marks 200 which do not meet the arrangement requirement are automatically adjusted, and finally the alignment mark 200 layout structure is generated.

In this way, the layout structure of the alignment mark 200 can be quickly generated, the layout efficiency of the alignment mark 200 can be improved, and the placement position of the alignment mark 200, the spacing of the alignment mark 200 and other parameters can be automatically controlled due to the setting of the placement rule of the alignment mark 200, so that the layout rationality of the alignment mark 200 can be ensured, and the layout structure accuracy of the alignment mark 200 can be improved.

By automatically generating the layout structure of the alignment mark 200, the layout efficiency of the alignment mark 200 is improved, and the layout of the alignment mark 200 is more reasonable, so that the alignment efficiency of a photomask can be improved, the alignment precision of the photomask is improved, and the productivity of the chip 110 is improved.

The requirements for placing the alignment mark 200 include: in each set of alignment marks, the center distance between the lateral alignment mark 210 and the vertical alignment mark 220 is less than or equal to a first preset value.

As described above, when aligning a mask, it is necessary to align the pattern on the mask with the pattern left by the previous mask or masks, and in this case, the alignment mark 200 on the mask is usually aligned with the alignment mark 200 of the previous mask or masks. Also, referring to FIG. 3, alignment marks 200 on a reticle are typically arranged in groups, each group of alignment marks 200 including a lateral alignment mark 210 and a vertical alignment mark 220.

Taking a set of alignment marks 200 as an example, when aligning, it is typical that the lateral alignment mark 210 of the current mask aligns with the lateral alignment mark 210 of the previous mask, and the vertical alignment mark 220 of the current mask aligns with the vertical alignment mark 220 of the previous mask.

Table 1 below shows the effect of different distances between the lateral alignment marks 210 and the vertical alignment marks 220 on the mask alignment time, where the distances represent the distances between the lateral alignment marks 210 and the vertical alignment marks 220 in a set of alignment marks 200, the alignment time is the time taken for the machine to align a set of alignment marks, and the number represents the number of alignment marks (for example, 26 sets) provided in each layer of mask.

Layer(s)	Distance (mm)	Alignment time (S)	Quantity (group)
				A	1..95	2.94	26
B	10.2	3.24	26
				C	13.7	3.43	26
D	22.2	3.64	26

TABLE 1

As can be seen from table 1, for the lateral alignment mark 210 and the vertical alignment mark 220 of the previous mask to be referred to in alignment, the longer the distance between the same set of lateral alignment mark 210 and vertical alignment mark 220, the longer the time for the lithography machine to position the set of alignment mark 200, the longer the time required for mask alignment, which reduces the mask alignment efficiency and reduces the throughput of the chip 110. Therefore, in this embodiment, when setting the placement rule of the alignment mark 200, for the same group of alignment marks 200, the distance between the horizontal alignment mark 210 and the vertical alignment mark 220 is controlled within a proper range by making the distance between the center of the alignment reference horizontal alignment mark 210 (the center positioning mark of the cross shape shown in fig. 3) and the center of the vertical alignment mark 220 (the center positioning mark of the cross shape shown in fig. 3) be equal to or less than the first preset value, so as to shorten the time for positioning the alignment mark 200 by the lithography machine, improve the alignment efficiency of the photomask, and further improve the productivity of the chip 110.

After the preliminary alignment mark layout structure is generated, whether each group of alignment marks in the preliminary alignment mark layout structure meets a first preset value in the placement requirement is judged. And for each group of alignment marks which do not meet the first preset value, adjusting the positions of the alignment marks until all the alignment marks meet the requirement of the first preset value.

Specifically, if the distance between the center of the alignment reference lateral alignment mark 210 and the center of the vertical alignment mark 220 is greater than the first preset value, the position of at least one of the lateral alignment mark 210 and the vertical alignment mark 220 is automatically adjusted, and the distance between the lateral alignment mark 210 and the vertical alignment mark 220 is shortened until the distance between the centers of the two is less than or equal to the first preset value. It should be noted that, the manner of moving the lateral alignment mark 210 and the vertical alignment mark 220 is translation, so as to ensure that the lateral alignment mark 210 always extends along the X-axis direction, and the vertical alignment mark 220 always extends along the Y-axis direction.

Fig. 5 is a schematic diagram of a manner of adjusting a distance between a lateral alignment mark and a vertical alignment mark according to an embodiment of the present application. Taking the first preset value as an example of the lengths of the oblique sides (or the length of the diagonal line of one chip 110) corresponding to the dicing grooves 120 extending in the X-axis direction and the dicing grooves 120 extending in the Y-axis direction of the outer periphery of one chip 110, referring to fig. 5 (a), if the distance between the center of the lateral alignment mark 210 and the center of the vertical alignment mark 220 is greater than the first preset value, at this time, the lateral alignment mark 210 and the vertical alignment mark 220 are translated; referring to fig. 5 (b), the lateral alignment mark 210 may move in a direction approaching the vertical alignment mark 220 along the scribe line 120 in the X-axis direction where it is located, and the vertical alignment mark 220 may move in a direction approaching the lateral alignment mark 210 along the scribe line 120 in the Y-axis direction where it is located; referring to fig. 5 (c), if the distance between the center of the lateral alignment mark 210 and the center of the vertical alignment mark 220 is still greater than the first preset value, the lateral alignment mark 210 may cross the scribe line 120 to other X-axis directions toward the direction in which the vertical alignment mark 220 is located, and the vertical alignment mark 220 continues to move along the scribe line 120 in the Y-axis direction in which it is located toward the direction approaching the lateral alignment mark 210 until the distance between the center of the lateral alignment mark 210 and the center of the vertical alignment mark 220 is less than or equal to the first preset value.

It should be noted that fig. 5 only shows one way to adjust the distance between the lateral alignment mark 210 and the vertical alignment mark 220, and in practical application, when the distance between the center of the lateral alignment mark 210 and the center of the vertical alignment mark 220 is greater than a first preset value, the lateral alignment mark 210 may move along the scribe line 120 in the X-axis direction where it is located, or may span across the scribe line 120 to other X-axis directions; similarly, the vertical alignment mark 220 may move along the scribe line 120 in the Y-axis direction, or may span across the scribe line 120 to other Y-axis directions, which is not particularly limited in this embodiment.

In addition, shown in fig. 5 is a case where the lateral alignment mark 210 and the vertical alignment mark 220 are simultaneously moved when the distance between the center of the lateral alignment mark 210 and the center of the vertical alignment mark 220 is greater than a first preset value, and in other embodiments, for example, in a case where the distance between the center of the lateral alignment mark 210 and the center of the vertical alignment mark 220 is slightly greater than the first preset value, only one of the lateral alignment mark 210 and the vertical alignment mark 220 may be moved while the other remains motionless.

Illustratively, the lateral alignment mark 210 is stationary, and the vertical alignment mark 220 moves along the scribe line 120 in the Y-axis direction in which it is located or spans the scribe line 120 in other Y-axis directions until the distance between the center of the lateral alignment mark 210 and the center of the vertical alignment mark 220 is less than or equal to the first preset value. Alternatively, the vertical alignment mark 220 is not moved, and the lateral alignment mark 210 moves along the scribe line 120 in the X-axis direction thereof or spans the scribe line 120 in other X-axis directions until the distance between the center of the lateral alignment mark 210 and the center of the vertical alignment mark 220 is less than or equal to the first preset value.

When the lateral alignment marks 210 in the same group of alignment marks are adjusted, firstly, determining the scribe line 120 where the lateral alignment mark 210 is located as the current scribe line, and adjusting the position of the lateral alignment mark 210 in the current scribe line, for example, as shown in fig. 5 (a) -5 (b), moving the lateral alignment mark 210 in the current scribe line toward the position corresponding to the vertical alignment mark 220; if the center distance between the lateral alignment mark 210 and the vertical alignment mark 220 still does not meet the requirement of the first preset value, as shown in fig. 5 (b) -5 (c), the scribe line 120 where the lateral alignment mark 210 is located may be adjusted, and the lateral alignment mark 210 is moved toward the scribe line 120 near the vertical alignment mark 220 with the current scribe line as the origin until the center distance between the lateral alignment mark 210 and the vertical alignment mark 220 is less than or equal to the first preset value. It should be appreciated that after each adjustment of the scribe line 120 in which the lateral alignment mark 210 is located, the position of the lateral alignment mark 210 may also be continuously adjusted within the adjusted scribe line 120.

Similar to adjusting the lateral alignment marks 210, when adjusting the vertical alignment marks 220 in the same group of alignment marks 200, firstly determining the scribe line 120 where the vertical alignment mark 220 is located as the current scribe line, and adjusting the position of the vertical alignment mark 220 in the current scribe line, for example, as shown in fig. 5 (a) -5 (c), moving the vertical alignment mark 220 in the current scribe line toward the position corresponding to the lateral alignment mark 210; if the center distance between the vertical alignment mark 220 and the horizontal alignment mark 210 does not meet the requirement of the first preset value, the scribe line 120 where the vertical alignment mark 220 is located may be adjusted, and the vertical alignment mark 220 is moved toward the scribe line 120 near the horizontal alignment mark 210 with the current scribe line as the origin until the center distance between the vertical alignment mark 220 and the horizontal alignment mark 210 is less than or equal to the first preset value. It should be appreciated that after each adjustment of the scribe line 120 in which the vertical alignment mark 220 is located, the position of the vertical alignment mark 220 may also be continuously adjusted within the adjusted scribe line 120. For the case where the mask is aligned with the alignment mark 200 of the previous mask, as an embodiment, when the previous mask is aligned with the previous mask, for a previous track of the mask as an alignment reference, the distance between the center of the lateral alignment mark 210 and the center of the vertical alignment mark 220 in each set of alignment marks 200 is less than or equal to the first preset value in the alignment mark 200 on the track.

In which, the lateral alignment marks 210 and the vertical alignment marks 220 in the set of alignment marks 200 are generally alignment marks 200 with the same shape, fig. 6 is a schematic diagram of an alignment manner of the alignment marks provided in the embodiment of the present application, and referring to fig. 6, taking the shape of the set of alignment marks 200 as the alignment reference as the first alignment mark 200a as an example, a distance between the center of the lateral alignment mark 210 and the center of the vertical alignment mark 220 is less than or equal to a first preset value.

As another embodiment, the lateral alignment mark 210 of the current mask is aligned with the lateral alignment mark 210 of the previous mask (for ease of illustration, it is defined as the mth mask), and the vertical alignment mark 220 of the current mask is aligned with the vertical alignment mark 220 of the previous mask (for ease of illustration, it is defined as the nth mask). At this time, it is necessary to set a distance between the center of the lateral alignment mark 210 of the mth mask and the center of the vertical alignment mark 220 of the nth mask to be equal to or less than a first preset value.

At this time, since the lateral alignment mark 210 and the vertical alignment mark 220 as alignment references are formed by different masks, and the shape of the alignment mark 200 disposed in each mask may be different, the lateral alignment mark 210 of the mth mask and the vertical alignment mark 220 of the nth mask may be selected to have the same shape or different shapes.

Fig. 7 is a schematic diagram of another alignment manner of the alignment mark provided in the embodiment of the present application, taking the shape of the alignment mark 200 provided on the mth photomask and the nth photomask as an example, which includes the first alignment mark 200a and the second alignment mark 200b, referring to fig. 7 (a), the first alignment mark 200a may be selected for the lateral alignment mark 210 of the mth photomask and the vertical alignment mark 220 of the nth photomask; referring to fig. 7 (b), the lateral alignment mark 210 of the mth mask and the vertical alignment mark 220 of the nth mask may be selected from the second alignment mark 200b; referring to fig. 7 (c), the lateral alignment mark 210 of the mth mask may be selected from the first alignment mark 200a, and the vertical alignment mark 220 of the nth mask may be selected from the second alignment mark 200b; referring to fig. 7 (d), the lateral alignment mark 210 of the mth mask may be selected from the second alignment mark 200b, and the vertical alignment mark 220 of the nth mask may be selected from the first alignment mark 200a; the distance between the center of the lateral alignment mark 210 of the mth mask and the center of the vertical alignment mark 220 of the nth mask needs to satisfy the value equal to or less than the first preset value no matter which shape is selected for the lateral alignment mark 210 of the mth mask and the vertical alignment mark 220 of the nth mask.

Since the pattern transfer of the alignment mark 200 provided on the mask is transferred and etched into the scribe line 120 of the wafer 100 at the same time as the pattern transfer of the mask for forming the semiconductor device onto the chip 110, the corresponding grating 2011 pattern is formed in the scribe line 120 as the alignment mark 200, and thus, when the mask alignment is performed, the alignment mark 200 is positioned by the lithography machine, some structures on the wafer 100 may affect the accuracy of measuring the alignment mark 200. Therefore, when designing the layout structure of the alignment mark 200, some ways that have an effect on the accuracy of determining the position of the alignment mark 200 may be considered, thereby further defining the position of the alignment mark 200.

At this time, on the basis that it is determined that the distance between the center of the horizontal alignment mark 210 and the center of the vertical alignment mark 220, which are referred to when the photomask is aligned, is less than or equal to the first preset value, the placing requirements of the alignment mark 200 may further include: the spacing between the edge of the alignment mark 200 and the groove wall of the scribe line 120 is equal to or greater than a second predetermined value.

If the alignment mark 200 in the scribe line 120 is too close to the groove wall of the scribe line 120, that is, if the alignment mark 200 is too close to the groove wall on either side of the width direction of the scribe line 120, when the photolithography machine positions the alignment mark 200 in the scribe line 120, the signal generated by the groove wall of the scribe line 120 will interfere with the signal of the alignment mark 200, and the accuracy of positioning the alignment mark 200 will be affected, thereby affecting the alignment accuracy of the photomask, causing misalignment of the semiconductor device formed by exposure and development on the chip 110, and possibly causing failure of the semiconductor device in serious cases.

Therefore, in this embodiment, by setting the distance between the edge of the alignment mark 200 and the groove wall on the corresponding side of the scribe line 120 to be equal to or greater than the second preset value, the center of the alignment mark 200 is located on the center line of the scribe line 120, or the center of the alignment mark 200 has only a small offset relative to the center line of the scribe line 120, so as to ensure that there is a sufficient gap between the alignment mark 200 and the groove wall of the scribe line 120, avoid the interference of the groove wall of the scribe line 120 on the alignment mark 200, ensure the positioning accuracy of the alignment mark 200, ensure the alignment accuracy of the photomask, and further improve the accuracy of the semiconductor device formed on the chip 110.

When the alignment mark 200 does not meet the requirement of the second preset value, the adjusting the position of the alignment mark 200 specifically includes: the distance between the two side edges of the alignment mark 200 corresponding to the width direction of the scribe line 120 and the edges of the corresponding sides of the scribe line 120 is measured, the distance between the two sides of the alignment mark 200 is obtained, and the alignment mark 200 is moved to the side with the larger distance until the distance between the two side edges of the alignment mark 200 and the two side edges of the scribe line 120 meets the requirement of the second preset value.

Similar to the interference of the groove wall of the scribe line 120 on the positioning alignment mark 200, for the lateral alignment mark 210 in the scribe line 120 in the same X-axis direction or the vertical alignment mark 220 in the scribe line 120 in the same Y-axis direction, if the distance between the adjacent alignment marks 200 is too close, signals generated by the alignment marks 200 will interfere with each other, which affects the accuracy of the positioning alignment mark 200 of the lithography machine, and further affects the alignment accuracy of the photomask.

In this embodiment, when designing the layout structure of the alignment mark 200, the placement requirements of the alignment mark 200 may further include: in the same scribe line 120, the distance between adjacent alignment marks 200 is equal to or greater than a third predetermined value.

By setting the interval between adjacent alignment marks 200 in the same scribing groove 120 to be equal to or larger than a third preset value, when the photoetching machine positions the alignment marks 200 in the scribing groove 120, mutual interference caused by too small interval between the adjacent alignment marks 200 is avoided, positioning accuracy of the alignment marks 200 is ensured, alignment accuracy of a photomask is ensured, and further, accuracy of semiconductor devices formed on the chip 110 is improved.

For example, when the pitch between adjacent alignment marks 200 in the same scribe line 120 is smaller than 500 μm, the signals generated by the adjacent alignment marks 200 may have relatively significant mutual interference, and the third preset value may be 500 μm.

When the alignment mark 200 does not meet the requirement of the third preset value, the adjusting the position of the alignment mark 200 or the adjacent alignment mark specifically includes: if the adjacent alignment marks are single alignment marks and do not have the same group of alignment marks, the positions of the adjacent alignment marks are preferentially adjusted, for example: the adjacent alignment marks are translated away from the adjusted alignment marks 200.

If the adjacent alignment marks have the same group of alignment marks and meet the requirements of the first preset value and the second preset value, the currently adjusted alignment mark 200 is continuously adjusted, for example: when the spacing between adjacent lateral alignment marks 210 in the dicing groove 120 in the X-axis direction does not meet the requirement of the third preset value, the vertical alignment marks 220 in the same group of alignment marks 200 can be fixed, and the lateral alignment marks 210 in the same group of alignment marks 200 can be adjusted; when the spacing between adjacent vertical alignment marks 220 in the scribe line 120 in the Y-axis direction does not meet the requirement of the third preset value, the lateral alignment marks 210 in the same group of alignment marks 200 may be fixed, and the vertical alignment marks 220 in the same group of alignment marks may be adjusted. If the currently adjusted alignment mark 200 meets the requirements of the first preset value and the second preset value and there is no adjustment space, the adjacent alignment mark is adjusted.

On the basis of this, the embodiment of the present application provides a layout apparatus of alignment marks (hereinafter referred to as a layout apparatus) which can be used to perform the layout method of alignment marks provided above. Fig. 8 is a schematic diagram of a layout device of alignment marks according to an embodiment of the present application. Referring to fig. 8, the layout apparatus 300 includes:

a determining module 310 is configured to determine frame parameters of the wafer 100.

The wafer 100 is provided with a plurality of chips 110 in an array, the chips 110 are separated from each other by dicing channels 120, and the frame parameters of the wafer 100 include the design dimensions of the chips 110 and the design dimensions of the dicing channels 120. For example, the design dimensions of the chips 110 may include the size of the area of each chip 110 (e.g., the length and width of the chips 110), and the design dimensions of the scribe line 120 may include the width of the scribe line 120.

The determination module 310 is also used to determine design parameters of the alignment mark 200.

The alignment marks 200 finally required to be formed on the wafer 100 include a plurality of groups of alignment marks 200 disposed on each photomask, and each group of alignment marks 200 includes a lateral alignment mark 210 and a vertical alignment mark 220. The alignment marks 200 may also include different shapes, and the same shape alignment mark 200 or different shapes of alignment marks 200 may be disposed on each mask, and the alignment marks 200 may include first alignment marks 200a and second alignment marks 200b having different shapes, for example.

The determination module 310 determines design parameters of the alignment marks 200, including determining the number of alignment marks 200 and the shape of the alignment marks 200. For example, the determining module 310 is configured to determine the total number of alignment marks 200 that are ultimately required to be formed on the wafer 100, including the number of lateral alignment marks 210 and the number of vertical alignment marks 220, as well as the number of alignment marks 200 of different shapes.

The obtaining module 320 is configured to obtain the placement requirement of the alignment mark 200. The obtaining module 320 may be configured to set, according to a placement requirement of the alignment marks 200, that a center distance between the horizontal alignment mark 210 and the vertical alignment mark 220 in each group of alignment marks 200 is less than or equal to a first preset value; the obtaining module 320 may be further configured to set a distance between an edge of the alignment mark 200 and a groove wall of a corresponding side of the scribe line 120 to be greater than or equal to a second preset value; the obtaining module 320 may be further configured to set a spacing between adjacent alignment marks 200 in the same scribe line 120 to be greater than or equal to a third preset value.

The output module 330 is configured to generate a layout structure of the alignment mark 200 according to the frame parameters of the wafer 100, the design parameters of the alignment mark 200, and the placement requirements of the alignment mark 200.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.

Unless specifically stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally formed; can be directly connected or indirectly connected through an intermediate medium, and can lead the connection between the two elements or the interaction relationship between the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (15)

1. A layout method of alignment marks, comprising:

acquiring the placing requirement of the alignment mark;

determining frame parameters of the wafer;

determining design parameters of the alignment mark;

and generating an alignment mark layout structure according to the frame parameters of the wafer, the design parameters of the alignment mark and the placement requirements of the alignment mark.

2. The layout method of alignment marks according to claim 1, wherein the wafer includes a plurality of chips arranged in an array and scribe lines between the chips;

the alignment marks are arranged in the scribing grooves, each alignment mark comprises a plurality of groups of alignment marks corresponding to each photomask, and each group of alignment marks comprises a transverse alignment mark and a vertical alignment mark.

3. The alignment mark layout method according to claim 2, wherein the alignment mark placement requirement comprises:

and in each group of alignment marks, the center distance between the transverse alignment mark and the vertical alignment mark is smaller than or equal to a first preset value.

4. The alignment mark layout method according to claim 3, wherein the alignment mark placement requirement further comprises:

the distance between the edge of the alignment mark and the groove wall of the scribing groove is larger than or equal to a second preset value.

5. The alignment mark layout method according to claim 4, wherein the alignment mark placement requirement further comprises:

in the same scribing groove, the distance between every two adjacent alignment marks is larger than or equal to a third preset value.

6. The method of alignment mark layout according to claim 5, further comprising, before generating the alignment mark layout structure:

generating a preliminary alignment mark layout structure according to the frame parameters of the wafer, the design parameters of the alignment marks and the placement requirements of the alignment marks;

judging whether each group of alignment marks in the preliminary alignment mark layout structure meets a first preset value in the placement requirement or not;

And adjusting all groups of alignment marks which do not meet the first preset value until all the alignment marks meet the placing requirement, and generating the alignment mark layout structure.

7. The method of laying out alignment marks according to claim 6, wherein said adjusting each set of alignment marks that does not satisfy said first preset value comprises:

and adjusting the transverse alignment coordinates and/or the vertical alignment marks in the same group of alignment marks until the center distance between the transverse alignment marks and the vertical alignment marks in the same group of alignment marks is smaller than or equal to the first preset value.

8. The method of claim 7, wherein said adjusting the lateral alignment marks in the same set of alignment marks comprises:

determining a scribing groove in which the transverse alignment mark is positioned as a current scribing groove, and adjusting the position of the transverse alignment mark in the current scribing groove;

adjusting the scribing groove in which the transverse alignment mark is positioned, and adjusting the scribing groove close to the vertical alignment mark by taking the current scribing groove as an original point;

until the center distance between the transverse alignment mark and the vertical alignment mark is smaller than or equal to the first preset value.

9. The method of alignment mark layout according to claim 8, wherein said adjusting the lateral alignment marks in the same set of alignment marks further comprises: and after each time of adjusting the scribing groove in which the transverse alignment mark is positioned, continuously adjusting the position of the transverse alignment mark in the adjusted scribing groove.

10. The method of claim 7, wherein said adjusting vertical alignment marks in the same set of alignment marks comprises:

determining a scribing groove in which the vertical alignment mark is positioned as a current scribing groove, and adjusting the position of the vertical alignment mark in the current scribing groove;

adjusting the scribing groove in which the vertical alignment mark is positioned, and adjusting the scribing groove close to the transverse alignment mark by taking the current scribing groove as an original point;

until the center distance between the vertical alignment mark and the horizontal alignment mark is smaller than or equal to the first preset value.

11. The method of claim 10, wherein said adjusting vertical alignment marks in the same set of alignment marks further comprises: and after the scribing groove where the vertical alignment mark is positioned is adjusted each time, continuously adjusting the position of the vertical alignment mark in the adjusted scribing groove.

12. The method of alignment mark layout according to claim 6, wherein after each set of alignment marks whose adjustment does not satisfy the first preset value is generated, further comprising:

judging the second preset value and the third preset value for the adjusted alignment mark, and adjusting the position of the alignment mark if the second preset distance is not met; and if the third preset distance is not met, adjusting the positions of the alignment marks or the adjacent alignment marks.

13. The method for laying out alignment marks according to any one of claims 2 to 12, wherein the acquiring frame parameters of the wafer comprises:

and obtaining the design size of the chip, the design size of the scribing groove and the exposure area layout.

14. The method for laying out an alignment mark according to any one of claims 1 to 12, wherein the obtaining design parameters of the alignment mark comprises:

and acquiring the number and the shape of the alignment marks.

15. A layout apparatus of an alignment mark, comprising:

the acquisition module is used for acquiring the placement requirement of the alignment mark;

the determining module is used for determining frame parameters of the wafer;

The determining module is also used for determining design parameters of the alignment mark;

and the output module is used for generating an alignment mark layout structure according to the frame parameters of the wafer, the design parameters of the alignment mark and the placement requirements of the alignment mark.