CN101784905B - 用于对片上系统的制造进行控制的设计信息的验证 - Google Patents
用于对片上系统的制造进行控制的设计信息的验证 Download PDFInfo
- Publication number
- CN101784905B CN101784905B CN2008801028859A CN200880102885A CN101784905B CN 101784905 B CN101784905 B CN 101784905B CN 2008801028859 A CN2008801028859 A CN 2008801028859A CN 200880102885 A CN200880102885 A CN 200880102885A CN 101784905 B CN101784905 B CN 101784905B
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- China
- Prior art keywords
- circuit module
- circuit
- chip
- register
- module
- Prior art date
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Debugging And Monitoring (AREA)
Abstract
Description
Claims (15)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP07114296 | 2007-08-14 | ||
EP07114296.2 | 2007-08-14 | ||
PCT/IB2008/053194 WO2009022276A2 (en) | 2007-08-14 | 2008-08-08 | Software-based verification of system-on-chip direct interconnect through additional registers |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101784905A CN101784905A (zh) | 2010-07-21 |
CN101784905B true CN101784905B (zh) | 2013-05-08 |
Family
ID=40210490
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2008801028859A Active CN101784905B (zh) | 2007-08-14 | 2008-08-08 | 用于对片上系统的制造进行控制的设计信息的验证 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8327309B2 (zh) |
CN (1) | CN101784905B (zh) |
WO (1) | WO2009022276A2 (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011149775A (ja) * | 2010-01-20 | 2011-08-04 | Renesas Electronics Corp | 半導体集積回路及びコアテスト回路 |
US9436785B1 (en) * | 2014-09-19 | 2016-09-06 | Xilinx, Inc. | Hierarchical preset and rule based configuration of a system-on-chip |
CN107957695A (zh) * | 2016-10-18 | 2018-04-24 | 普林斯卡思特有限公司 | 具有可调系统行为的模块化保持容器 |
KR20220090928A (ko) | 2020-12-23 | 2022-06-30 | 삼성전자주식회사 | 시스템 온 칩 테스트 방법 및 시스템 온 칩 테스트 시스템 |
CN117056157B (zh) * | 2023-10-11 | 2024-01-23 | 沐曦集成电路(上海)有限公司 | 一种寄存器层次化验证方法、存储介质和电子设备 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1476174A (zh) * | 2003-07-04 | 2004-02-18 | 清华大学 | 片上系统的测试数据压缩编码、解码方法及专用解码单元 |
CN1679165A (zh) * | 2002-08-22 | 2005-10-05 | 株式会社爱德万测试 | 评估核基片上系统的方法 |
CN1734278A (zh) * | 2005-05-27 | 2006-02-15 | 上海大学 | 集成电路片上系统中故障的测试系统和方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6484280B1 (en) * | 1999-09-30 | 2002-11-19 | Agilent Technologies Inc. | Scan path test support |
GB0121990D0 (en) * | 2001-09-11 | 2001-10-31 | Beach Solutions Ltd | Emulation system & method |
JP2004062532A (ja) * | 2002-07-29 | 2004-02-26 | Renesas Technology Corp | 接続検証装置 |
US7437692B2 (en) * | 2003-11-10 | 2008-10-14 | Infineon Technologies Ag | Memory debugger for system-on-a-chip designs |
-
2008
- 2008-08-08 CN CN2008801028859A patent/CN101784905B/zh active Active
- 2008-08-08 US US12/673,445 patent/US8327309B2/en active Active
- 2008-08-08 WO PCT/IB2008/053194 patent/WO2009022276A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1679165A (zh) * | 2002-08-22 | 2005-10-05 | 株式会社爱德万测试 | 评估核基片上系统的方法 |
CN1476174A (zh) * | 2003-07-04 | 2004-02-18 | 清华大学 | 片上系统的测试数据压缩编码、解码方法及专用解码单元 |
CN1734278A (zh) * | 2005-05-27 | 2006-02-15 | 上海大学 | 集成电路片上系统中故障的测试系统和方法 |
Non-Patent Citations (2)
Title |
---|
A.AMORY et al.Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architecture.《IFTP International Federation for Information Processing 》.2006,165-179. * |
QIANG XU et al.On Reducing Wrapper Boundary Register Cells in Modular SOC Testing.《ITC International Test Conference》.2003,622-631. * |
Also Published As
Publication number | Publication date |
---|---|
US20110239067A1 (en) | 2011-09-29 |
WO2009022276A3 (en) | 2009-04-09 |
CN101784905A (zh) | 2010-07-21 |
WO2009022276A2 (en) | 2009-02-19 |
US8327309B2 (en) | 2012-12-04 |
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ASS | Succession or assignment of patent right |
Owner name: WEIERJI LOGIC CO. Free format text: FORMER OWNER: KONINKL PHILIPS ELECTRONICS NV Effective date: 20100916 |
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C41 | Transfer of patent application or patent right or utility model | ||
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Free format text: CORRECT: ADDRESS; FROM: EINDHOVEN, NETHERLANDS TO: CALIFORNIA, USA |
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Effective date of registration: 20100916 Address after: American California Applicant after: Vilge Logic Address before: Holland Ian Deho Finn Applicant before: Koninkl Philips Electronics NV |
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Owner name: SYNOPSYS INC. Free format text: FORMER OWNER: VL C.V. Effective date: 20111115 |
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Effective date of registration: 20111115 Address after: California, USA Applicant after: Synopsys Inc. Address before: American California Applicant before: Vilge Logic |
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