CN101783303B - 用于堆叠半导体基板的激光接合方法 - Google Patents

用于堆叠半导体基板的激光接合方法 Download PDF

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CN101783303B
CN101783303B CN201010000326.6A CN201010000326A CN101783303B CN 101783303 B CN101783303 B CN 101783303B CN 201010000326 A CN201010000326 A CN 201010000326A CN 101783303 B CN101783303 B CN 101783303B
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substrate
joint sheet
row
groove
semiconductor substrates
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CN101783303A (zh
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吴汀淏
郑创仁
李久康
蔡尚颖
彭荣辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明是有关于一种用于堆叠半导体基板的激光接合方法,其中叙述了使用激光接合堆叠半导体基板的方法和结构,在一具体实施方式中,形成一半导体元件的方法包含:形成一沟槽于一第一基板中,并形成一接合垫于一包含主动线路的第二基板上;此接合垫的上表面包含一第一材料;对准第一基板于第二基板之上,进而使沟槽对准于接合垫之上;导入一电磁射束至沟槽内,以在接合垫的第一材料和第一基板下表面的一第二材料之间形成一接合。

Description

用于堆叠半导体基板的激光接合方法
技术领域
本发明涉及一种接合方法,特别是涉及一种利用激光退火接合堆叠型半导体基板的方法。
背景技术
电子组件制造过程中的一个目标是使各种组件的尺寸最小化。例如使移动电话和个人数字助理(personal digital assistants,PDAs)等手持装置的尺寸尽可能地缩小。为了达成此目标,应尽可能缩小元件中的半导体线路。使这些线路微小化的方法之一是将负有线路的晶片堆叠起来。
已知有多种在堆叠晶片中产生内连接的方法。例如在共用基板或在堆叠晶片中的其它晶片上,以导线搭接(wire bond)每一晶片表面上的接合垫(bond pad)。另一实例是所谓的微凸块3D封装(micro-bump 3D package),每一晶片包含多个与一电路板连接的微凸块(例如,延着晶片的外侧边缘排列)。然而,使用这种内连接方式可能会招致其它的困难。
而将晶片整合成一体也带来了多种新的难题,必需一一克服。其中一个难题来自于在两晶片间或在晶片和基板之间形成粘性接合时所必需使用的加热步骤。因加热所产生的问题包括晶圆弯曲和使晶片中的关键零组件熔化。随着晶圆直径增加,这些难题也更不易克服。因此,在晶片接合技术中需要改良结构和方法,以克服上述这些和其它困难。
由此可见,上述现有的接合方法在方法与使用上,显然仍存在有不便与缺陷,而亟待加以进一步改进。为了解决上述存在的问题,相关厂商莫不费尽心思来谋求解决之道,但长久以来一直未见适用的设计被发展完成,而一般方法又没有适切的方法能够解决上述问题,此显然是相关业者急欲解决的问题。因此如何能创设一种新的用于堆叠半导体基板的激光接合方法,实属当前重要研发课题之一,亦成为当前业界极需改进的目标。
发明内容
本发明的目的在于,克服现有的接合方法存在的缺陷,而提供一种新的用于堆叠半导体基板的激光接合方法,所要解决的技术问题是使其利用局部加热技术实现堆叠型半导体基板的接合,非常适于实用。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种用于堆叠半导体基板的激光接合方法,其包括以下步骤:形成一沟槽于一第一基板中;形成一接合垫于一包含主动线路的第二基板上,该接合垫的一上表面包含一第一材料;对准该第一基板于该第二基板之上,其中该沟槽对准于该接合垫之上;以及导入一激光束于该沟槽之中,以在该接合垫上的第一材料和该第一基板一下表面的一第二材料之间形成一接合。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的用于堆叠半导体基板的激光接合方法,其中所述的第一材料选自金、银、铝、锡或铅所组成的族群且该第二材料包含硅或锗。
前述的用于堆叠半导体基板的激光接合方法,其中形成该接合的步骤包含形成一由该第一材料和该第二材料组成的共金合金。
前述的用于堆叠半导体基板的激光接合方法,更包含沉积该第二材料于该沟槽之中,其中该沟槽包含一贯通该第一基板的沟槽。
前述的用于堆叠半导体基板的激光接合方法,其中由该接合垫上的第一材料和该第一基板上的第二材料之间所形成的该接合具有导电性。
前述的用于堆叠半导体基板的激光接合方法,更包含在导入该激光束之前,沉积一热吸收材料于该沟槽之上,其中该热吸收材料包含碳。
前述的用于堆叠半导体基板的激光接合方法,更包含堆叠一第三基板于该第一基板之上,该第三基板经由该沟槽和该接合垫电性耦接于该第二基板,其中该第三基板包含电路。
前述的用于堆叠半导体基板的激光接合方法,其中所述的电性耦接包含使用导线搭接。
前述的用于堆叠半导体基板的激光接合方法,其中所述的激光束的波长小于约648nm,该激光束相对于该第一基板的速度大于约100mm/sec,且该激光束没有导入该第一基板的邻近沟槽间的区域。
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种用于堆叠半导体基板的激光接合方法,其包括以下步骤:形成一第一排通孔和一第二排通孔于一第一基板内;形成一第一排接合垫和一第二排接合垫于一包含主动电路的第二基板上;对准该第一基板于该第二基板之上,其中该第一排通孔对准于该第一排接合垫之上,且其中该第二排通孔对准于该第二排接合垫之上;以及导入一激光束于该第一排通孔和该第二排通孔之上,以在该接合垫的一第一材料和该第一和第二排通孔下表面的一第二材料之间形成一导电接合。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的用于堆叠半导体基板的激光接合方法,更包含沉积该第二材料于该第一和第二排通孔之中,其中该第一和第二排通孔包含多个贯通该第一基板的通孔。
前述的用于堆叠半导体基板的激光接合方法,更包含沉积一热吸收材料于该第一和第二排通孔之上,其中在该第二材料上沉积该热吸收材料的步骤是在导入该激光束之前进行。
前述的用于堆叠半导体基板的激光接合方法,其中所述的激光束的波长小于约648nm,该激光束相对于该第一基板的速度大于约100mm/sec,且该激光束的点波束宽度约小于该第一排通孔和该第二排通孔之间的距离。
前述的用于堆叠半导体基板的激光接合方法,其中所述的激光束连续扫描过该第一排通孔之上和该第二排通孔之上且该激光束没有被导入至该第一基板的相邻通孔间的区域。
本发明与现有技术相比具有明显的优点和有益效果。由以上可知,为达到上述目的,本发明提供了一种用于堆叠半导体基板的激光接合方法,本发明的具体实施方式包含激光接合。依据本发明的一较佳的具体实施方式,一种形成半导体元件的方法包含形成一沟槽于一第一基板中。此方法更包含形成一接合垫于一包含主动线路的第二基板上,接合垫的上表面包含一第一材料。经由对准第一基板于第二基板之上,使沟槽对准于接合垫之上。经由导入一电磁射束于沟槽之中,使接合垫上的第一材料和第一基板下表面上的第二材料之间形成接合。
借由上述技术方案,本发明用于堆叠半导体基板的激光接合方法至少具有下列优点及有益效果:本发明利用局部加热技术加热被接合的区域,不需要一最低温度,就可以形成堆叠型半导体基板间的接着层,并且同时也形成导电键结,而不会实质加热到敏感元件。
综上所述,本发明是有关于一种用于堆叠半导体基板的激光接合方法,其中叙述了使用激光接合堆叠半导体基板的方法和结构,在一具体实施方式中,形成一半导体元件的方法包含:形成一沟槽于一第一基板中,并形成一接合垫于一包含主动线路的第二基板上;此接合垫的上表面包含一第一材料;对准第一基板于第二基板之上,进而使沟槽对准于接合垫之上;导入一电磁射束至沟槽内,以在接合垫的第一材料和第一基板下表面的一第二材料之间形成一接合。本发明在技术上有显著的进步,具有明显的积极效果,诚为一新颖、进步、实用的新设计。
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,而可依照说明书的内容予以实施,并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂,以下特举较佳实施例,并配合附图,详细说明如下。
附图说明
图1是依据本发明的具体实施方式所形成的半导体元件结构的具体形态的示意图。
图2a-图2f是依据本发明的一具体实施方式在各种制造阶段的半导体元件的示意图。
图3a-图3c是依据本发明的另一具体实施方式在各种制造阶段的半导体元件的示意图。
图4a-图4b是依据本发明的又一具体实施方式在各种制造阶段的半导体元件的示意图。
图5是依据本发明的具体实施方式所形成的半导体元件结构的具体形态的示意图。
1:基板                 2:基板
3:基板                 11:沟槽
12:材料                13:衬垫
16:热吸收层            17:非热吸收材料
21:接合垫              31:激光点波束
41:共金合金区域        51:导线搭接
52:接合垫
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例,对依据本发明提出的用于堆叠半导体基板的激光接合方法其具体实施方式、方法、步骤、特征及其功效,详细说明如后。
有关本发明的前述及其他技术内容、特点及功效,在以下配合参考图式的较佳实施例的详细说明中将可清楚呈现。通过具体实施方式的说明,当可对本发明为达成预定目的所采取的技术手段及功效获得一更加深入且具体的了解,然而所附图式仅是提供参考与说明之用,并非用来对本发明加以限制。
有关本发明的前述及其他技术内容、特点及功效,在以下配合参考图式的较佳实施例的详细说明中将可清楚的呈现。为了方便说明,在以下的实施例中,相同的元件以相同的编号表示。
传统的接合技术是使用一种需将整片晶圆放在炉管中加热的晶圆层级接合技术。这样会使晶圆上其它敏感、不想被加热的元件也被加热,进而对这些敏感元件造成不良影响。例如,因为各层之间的热膨胀系数不一致而造成的晶圆扭曲变形。随着晶圆翘曲和变形程度的增加,可能会在之后的制造工艺或测试机台内发生晶圆对位错误的情况。其它因加热敏感元件所出现的问题包括敏感层的碎裂、形成气泡和/或残留物、以及主动元件因硼穿透和/或掺质失活所致的劣化。
然而,接合技术经常需要一最低温度,用来形成接着层,同时也形成导电键结。在各种具体实施方式中,本发明的具体实施方式利用局部加热技术克服了这些限制,可加热被接合的区域而不会实质加热到敏感元件。
请参考本文中的较佳具体实施方式(即,用于耦接两基板的电射共金接合技术)来了解本发明。然而,本发明也可应用于其它需要加热的接合工艺和个别组件(例如切割后的晶圆(diced wafer))的接合。
以下利用图1说明一种结构的具体实施方式,利用图2a-图2f说明一种制造堆叠晶片方法的具体实施方式,利用图5说明其它包含导线搭接技术(wire bond)的结构的具体实施方式。
图1是依据本发明的具体实施方式所形成的半导体元件结构的具体形态的示意图。
一第一基板1被堆叠在一第二基板2之上。此第二基板2包含元件,例如可为微机电元件(micro electro-mechanical device)和/或电子元件。第一基板1包含硅基板、锗基板、或其它复合式半导体基板。
在第一基板1中设置一贯通基板的沟槽11(through substratetrench)。贯通基板的沟槽11被设置在第二基板2的接合垫21(bond pads)上方。接合垫21电性耦接于第二基板2的多个元件。接合垫21包含一第一材料。第一材料的实例包含金(Au)、银(Ag)、锡(Sn)、铅(Pb)和/或铝(Al)。接合垫21电性耦接于设置在贯通基板的沟槽11中的第二材料12。第二材料12的实例包含Au、Ag、Sn、Pb、Al、硅(Si)和锗(Ge)。接合垫经由一共金合金区域41(eutectic alloy region)而物理性耦接于第二材料12。此共金合金区域41设置于第二材料12和接合垫21之间。共金合金区域41包含由第一材料与第二材料12所共同形成的一共金合金。例如,共金合金区域41包含一包括Au-Si、Au-Ge、Sn-Pb、Ag-Si、Ag-Ge,或其组合在内的共金合金。在某些具体实施方式中,在第二材料12和第一基板1之间,设置一非必要的衬垫13(liner)。此衬垫13包含阻障层(barrierlayer),例如氮化钛(TiN)或氮化钽(TaN)。
图2a-图2f是依据本发明的一具体实施方式在各种制造阶段的半导体元件的示意图。其绘示了利用局部接合方式来制造堆叠基板的方法。
请参阅图2a所示,此第一基板1和第二基板2为分别制造。第二基板2包含电路及电子元件,例如晶体管、二极管、电容等等,以及电动机械结构和元件。例如在一具体实施方式中,第二基板2包含微机电系统(MEMS)元件,而在其它的具体实施方式中,第二基板2包含金属氧化物半导体元件(Metal Oxide Semiconductor,MOS)。
在一具体实施方式中,第一基板1包含硅或锗基板,其中未设置主动电路或元件。在此具体实施方式中,第一基板1为一载体(carrier),或作为第二基板2的支撑基板。此外,在另一具体实施方式中,第一基板1可包含主动电路或元件。
请参阅图2a所示,在第一基板1中制造一贯通基板的沟槽11。此贯通基板的沟槽11从第一基板1的上表面延伸至对侧的下表面。在一具体实施方式中,可用反应性离子蚀刻设备来制造此贯通基板的沟槽11。
第二基板2包含接合垫21,其电性耦接于第二基板2的电路。接合垫21的上表面覆盖一层第一材料,在一实例中,是利用相减图形化工艺(subtractive patterning process)来沉积第一材料。在一实例中,在第二基板2上沉积一第一材料的毯覆层(blanket layer),接着利用光蚀刻工艺(photolithography process)选择性地移除第一材料。或者,第一材料可为接合垫的一部分,在一实例中,可为部分的顶端金属层。
在各种的具体实施方式中,在第二基板2的接合垫21上的第一材料包含金、银、锡、铅、铝或其组合。在各种的具体实施方式中,贯通基板的沟槽11的尺寸与第二基板2的接合垫21相似(dimension)。在一具体实施方式中,贯通基板的沟槽11的最大的尺寸比接合垫21的最大的尺寸小了至少20%。
请参阅图2b和图2c所示,第一基板1对准第二基板2并堆叠在一起。图2c绘示了一堆叠基板的剖面图,图2b绘示了堆叠基板的俯视图。第一基板1对准第二基板2,使贯通基板的沟槽11也对准接合垫21。
接下来参阅图2d所示,一第二材料12被沉积在贯通基板的沟槽11之中。第二材料12包含金、银、锡、铅、或其组合,使在接合垫21上的第一材料可与第二材料12形成共金合金。在各种具体实施方式中,共金合金的实例包含Au-Si、Au-Ge、Al-Si、Al-Ge、Sn-Pb,或其组合。
可在沉积第二材料之前,先形成一层非必要的衬垫13,用来保护第一基板1并防止第二材料12向外扩散进入第一基板1。沉积并蚀刻此非必要的衬垫13以形成一间隔物(spacer)。在各种具体实施方式中,可在第一基板1与第二基板2对准之前或之后,形成该衬垫13。衬垫13包含一导电材料,例如TiN或TaN,并且较佳的材料为不与第一材料和/或第二材料产生反应的材料(inert material)。
请参阅图2e所示,使用一激光源局部加热堆叠的基板。一位于贯通基板的沟槽11之上的激光点波束31(laser spot beam)通过晶圆。激光点波束31延着一条线移动,因此只会延着一长方形区域加热第一基板,其宽度由点波束宽度决定。因此在这个具体实施方式中,第一基板1上相邻的贯通基板的沟槽11之间的区域并没有被加热到,除非其是位于激光点波束31移动的方向上。
在另一具体实施方式中,所使用的激光是脉冲式(pulsed),只有当其位于贯通基板的沟槽11上方时才会激发此激光点波束31。因此,即使是位于激光点波束31的移动方向上,第一基板上介于贯通基板的沟槽11之间的邻接区域也不会被加热。
在各种具体实施方式中,可选择激光点波束31的功率密度、扫描速度和波束宽度,局部加热贯通基板的沟槽11使其超过共金温度。在一实例中,贯通基板的沟槽11被加热至约365℃以形成一用于接合的Si-Au共金混合物,加热至约420℃以形成一用于接合的Ge-Al共金混合物。可控制激光扫描速率,在一具体实施方式中为大于约100mm/sec。在各种具体实施方式中,激光波长由激光源决定,可为约0.3nm(X光)、405nm(蓝光)至约648nm(红光激光)。
在某些具体实施方式中,可使用其它的电磁辐射,在一实例中,可使用非同调(incoherent)的电磁辐射。另外,在某些具体实施方式中可使用其它的辐射作为加热射束,例如离子辐射(ionic radiation)。任何能量源都可作为加热源,条件是其可被聚焦在所需的区域且可将能量传出至基板。
在贯通基板的沟槽11中,第一材料和第二材料局部熔融并形成一共金合金区域41,使第一基板1与第二基板2的接合垫21产生接合(图2f)。之后可继续进行一般的工艺。在一实例中,可从背面以研磨/蚀刻工艺薄化第二基板2,并在堆叠基板之上形成一保护性填充材料。
图3a-图3c是依据本发明的另一具体实施方式在各种制造阶段的半导体元件的示意图,其中所形成的沟槽为一开口,并未贯通基板。
请参阅图3a所示,在第一基板1之中形成一沟槽111。与贯通基板的沟槽11(即,图2a)不同的是,沟槽111没有从第一基板1的上表面延伸至下表面,而是在第一基板1的沟槽111下方设置了一厚度为t的薄层。在各种具体实施方式中,厚度t的范围约为10nm至约100nm。如同之前的具体实施方式(图3b)所述,沟槽111对准第二基板2的接合垫21。利用激光点波束31局部加热沟槽111形成共金合金区域41,以接合第一基板1和第二基板2(图3c)。
第一基板1包含一掺杂基板,使第一基板1上厚度为t的层不会增加经由沟槽111与接合垫21的接触电阻(contact resistance)。另外,使用低能量布植(即,B<1000eV,As<2keV)将一导电材料掺杂至沟槽111的下表面。在一具体实施方式中,布植是在激光点波束31加热之前进行。
图4a-图4b是依据本发明的又一具体实施方式在各种制造阶段的半导体元件的示意图。其绘示了使用热吸收性材料的具体实施方式。
相对于前述的图2a-图2f和图3a-图3c的具体实施方式,图4a-图4b中增加了另一步骤。图4a-图4b与前述的具体实施方式的不同处在于另外使用了一种热吸收材料,以集中或更进一步缩小第二基板2的接合垫21周围的加热区域。藉由使用吸收层,沟槽区域可优先被加热(相比较于基板其它部分),使传送至第二基板2的热被最小化。在一些具体实施方式中,若沟槽材料会使大部分碰撞激光的能量被反射,即可使用此吸收层。
图4a绘示了一具体实施方式,其中贯通基板的沟槽11中填充了一热吸收层16。在另一具体实施方式中,贯通基板的沟槽11中可能没有填充热吸收层16。热吸收层16有助于吸收更多位于贯通基板的沟槽11上方的辐射。贯通基板的沟槽11上的热吸收层16较佳的形成方式为填充贯通基板的沟槽11的空隙(图4a),或如图4b中所示被图形化。
图4b所示为将一非热吸收材料17图形化而形成的热吸收层16。局部使用热吸收层16可降低激光源使用的功率或提高激光扫描速度,因此提升传热过程的效率。热吸收层16实质是吸收任何撞击其的激光辐射。该层仅会少许反射任何由激光所发出的电磁辐射。在各式的具体实施方式中,热吸收层16包含非晶碳,此非晶碳包含以不纯物(例如氮、磷、氟、氧或其组合)掺杂的非晶碳。
例如,使用此具体实施方式的热吸收层16,激光点波束可延着一连续线行进(continuous line)(即,连续线性扫描),而非脉冲式。在一些具体实施方式中,因为对位错误问题所以使用脉冲式激光可能不是较佳的方法,因为当激光点波束经过贯通基板的沟槽11时,需要正确地开启激光点波束。
图5是依据本发明的具体实施方式所形成的半导体元件结构的具体形态的示意图,在堆叠的基板上(如图2a-图2f或图3a-图3c所示)再叠上一第三基板3。
第三基板3被叠在第一基板1上。第三基板3包含电路,并包含电子和/或电动机械元件。第三基板3贯通基板的沟槽11(或图3的沟槽111)与第二基板2电性耦接,例如,利用导线搭接51(wire bonds)。导线搭接51将第三基板3上的接合垫52耦接至第二基板2上的接合垫21。
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。

Claims (12)

1.一种用于堆叠半导体基板的激光接合方法,其特征在于其包括以下步骤:
形成一沟槽于一第一基板中;
形成一接合垫于一包含主动线路的第二基板上,该接合垫的一上表面包含一第一材料,其中所述的第一材料选自金、银、铝、锡或铅所组成的族群;
对准该第一基板于该第二基板之上,其中该沟槽对准于该接合垫之上;
沉积一第二材料于该接合垫上的该第一材料以及该沟槽中,其中所述的第二材料包含硅或锗;以及
导入一激光束于该沟槽之中,使该接合垫上的该第一材料和该第二材料局部熔融并形成一共金合金,以在该接合垫上的第一材料和该第二材料之间形成一接合。
2.根据权利要求1所述的用于堆叠半导体基板的激光接合方法,其特征在于其中由该接合垫上的第一材料和该第一基板上的第二材料之间所形成的该接合具有导电性。
3.根据权利要求1所述的用于堆叠半导体基板的激光接合方法,其特征在于更包含在导入该激光束之前,沉积一热吸收材料于该沟槽之上,其中该热吸收材料包含碳。
4.根据权利要求1所述的用于堆叠半导体基板的激光接合方法,其特征在于更包含堆叠一第三基板于该第一基板之上,该第三基板经由该沟槽和该接合垫电性耦接于该第二基板,其中该第三基板包含电路。
5.根据权利要求4所述的用于堆叠半导体基板的激光接合方法,其特征在于其中所述的电性耦接包含使用导线搭接。
6.根据权利要求1所述的用于堆叠半导体基板的激光接合方法,其特征在于其中所述的激光束的波长小于约648nm,该激光束相对于该第一基板的速度大于约100mm/sec,且该激光束没有导入该第一基板的邻近沟槽间的区域。
7.一种用于堆叠半导体基板的激光接合方法,其特征在于包括以下步骤:
形成一沟槽于一第一基板中,其中该沟槽没有贯穿该第一基板,该沟槽的下方形成有该第一基板的一薄层,且该薄层包含硅或锗;
形成一接合垫于一包含主动线路的第二基板上,该接合垫的一上表面包含一第一材料,其中所述的第一材料选自金、银、铝、锡或铅所组成的族群;
对准该第一基板于该第二基板之上,其中该沟槽和该薄层对准于该接合垫之上;以及
导入一激光光束于该沟槽之中,使该薄层与该接合垫上的该第一材料形成一共金合金,以接合该第一基板和该第二基板。
8.根据权利要求7所述的用于堆叠半导体基板的激光接合方法,其特征在于,在对准该第一基板于该第二基板之前,更包含掺杂一导电材料至该沟槽的下表面。
9.一种用于堆叠半导体基板的激光接合方法,其特征在于其包括以下步骤:
形成一第一排通孔和一第二排通孔于一第一基板内;
形成一第一排接合垫和一第二排接合垫于一包含主动电路的第二基板上,各该接合垫包含一第一材料,其中所述的第一材料选自金、银、铝、锡或铅所组成的族群;
对准该第一基板于该第二基板之上,其中该第一排通孔对准于该第一排接合垫之上,且其中该第二排通孔对准于该第二排接合垫之上;
沉积一第二材料于各该接合垫以及该第一和该第二排通孔之中,其中所述的第二材料包含硅或锗;以及
导入一激光束于该第一排通孔和该第二排通孔之上,使各该接合垫的该第一材料和该第二材料局部熔融并形成一共金合金,以在该接合垫的该第一材料和该第二材料之间形成一导电接合。
10.根据权利要求9所述的用于堆叠半导体基板的激光接合方法,其特征在于更包含沉积一热吸收材料于该第一和第二排通孔之上,其中在该第二材料上沉积该热吸收材料的步骤是在导入该激光束之前进行。
11.根据权利要求9所述的用于堆叠半导体基板的激光接合方法,其特征在于其中所述的激光束的波长小于约648nm,该激光束相对于该第一基板的速度大于约100mm/sec,且该激光束的点波束宽度约小于该第一排通孔和该第二排通孔之间的距离。
12.根据权利要求9所述的用于堆叠半导体基板的激光接合方法,其特征在于其中所述的激光束连续扫描过该第一排通孔之上和该第二排通孔之上且该激光束没有被导入至该第一基板的相邻通孔间的区域。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8367516B2 (en) * 2009-01-14 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Laser bonding for stacking semiconductor substrates
KR20120023260A (ko) * 2010-09-01 2012-03-13 삼성전자주식회사 반도체 장치 및 그 제조 방법
US8810027B2 (en) * 2010-09-27 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond ring for a first and second substrate
US20140097003A1 (en) * 2012-10-05 2014-04-10 Tyco Electronics Amp Gmbh Electrical components and methods and systems of manufacturing electrical components
CN105990166B (zh) * 2015-02-27 2018-12-21 中芯国际集成电路制造(上海)有限公司 晶圆键合方法
US10410883B2 (en) 2016-06-01 2019-09-10 Corning Incorporated Articles and methods of forming vias in substrates
US10794679B2 (en) 2016-06-29 2020-10-06 Corning Incorporated Method and system for measuring geometric parameters of through holes
US10134657B2 (en) * 2016-06-29 2018-11-20 Corning Incorporated Inorganic wafer having through-holes attached to semiconductor wafer
US10608404B2 (en) * 2017-02-14 2020-03-31 Cisco Technology, Inc. Bonded laser with solder-free laser active stripe in facing relationship with submount
US11078112B2 (en) 2017-05-25 2021-08-03 Corning Incorporated Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same
DE102017223372A1 (de) * 2017-12-20 2019-06-27 Robert Bosch Gmbh Laserbondverfahren und mikromechanische Vorrichtung mit Laserbondverbindung
US11554984B2 (en) 2018-02-22 2023-01-17 Corning Incorporated Alkali-free borosilicate glasses with low post-HF etch roughness

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101030627A (zh) * 2006-03-03 2007-09-05 株式会社半导体能源研究所 发光元件、发光器件、发光器件的制造方法以及片状密封材料
CN101145551A (zh) * 2006-09-12 2008-03-19 奇梦达股份公司 集成器件
CN101266955A (zh) * 2007-03-15 2008-09-17 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN101308865A (zh) * 2007-05-14 2008-11-19 索尼株式会社 有机电致发光显示装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US730777A (en) * 1903-04-07 1903-06-09 George Krebs Coupling.
US4814855A (en) 1986-04-29 1989-03-21 International Business Machines Corporation Balltape structure for tape automated bonding, multilayer packaging, universal chip interconnection and energy beam processes for manufacturing balltape
US5650881A (en) 1994-11-02 1997-07-22 Texas Instruments Incorporated Support post architecture for micromechanical devices
US6423613B1 (en) 1998-11-10 2002-07-23 Micron Technology, Inc. Low temperature silicon wafer bond process with bulk material bond strength
US6568794B2 (en) 2000-08-30 2003-05-27 Ricoh Company, Ltd. Ink-jet head, method of producing the same, and ink-jet printing system including the same
US6903442B2 (en) * 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
US7307777B2 (en) 2003-10-23 2007-12-11 Spatial Photonics, Inc. High-resolution spatial light modulation
CN101084462B (zh) 2003-10-27 2010-06-02 视频有限公司 高反差空间光调制器和方法
US8084866B2 (en) * 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US7232754B2 (en) * 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7346178B2 (en) 2004-10-29 2008-03-18 Silicon Matrix Pte. Ltd. Backplateless silicon microphone
US8586468B2 (en) 2005-08-24 2013-11-19 Sony Corporation Integrated circuit chip stack employing carbon nanotube interconnects
US8367516B2 (en) * 2009-01-14 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Laser bonding for stacking semiconductor substrates

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101030627A (zh) * 2006-03-03 2007-09-05 株式会社半导体能源研究所 发光元件、发光器件、发光器件的制造方法以及片状密封材料
CN101145551A (zh) * 2006-09-12 2008-03-19 奇梦达股份公司 集成器件
CN101266955A (zh) * 2007-03-15 2008-09-17 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN101308865A (zh) * 2007-05-14 2008-11-19 索尼株式会社 有机电致发光显示装置

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