CN101777910B - Delay phase locked loop - Google Patents
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- CN101777910B CN101777910B CN201010033860A CN201010033860A CN101777910B CN 101777910 B CN101777910 B CN 101777910B CN 201010033860 A CN201010033860 A CN 201010033860A CN 201010033860 A CN201010033860 A CN 201010033860A CN 101777910 B CN101777910 B CN 101777910B
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Abstract
The invention discloses a delay phase locked loop, which comprises a voltage control delay line and a multiplexer. The voltage control delay line comprises a plurality of cascade delay units, the multiplexer comprises a plurality of differential pair tubes, the grid of each differential pair tube is respectively connected with the output node of one delay unit, one end of the differential pair tube is connected with a grounding voltage by a shared current source, and the other end thereof is connected with a power supply voltage by a load device. The multiplexer further comprises a first switch connected among the differential pair tubes and the shared current source, a second switch connected among the differential pair tubes and the load device, and the output end node of the multiplexer is arranged between the second switch and the load device. The invention can improve the precision of delay control and ensure the consistency of the delay of each stage for VCDL.
Description
Technical field
The present invention relates to the delay circuit design field, particularly relate to a kind of delay phase-locked loop.
Background technology
In recent years; Develop rapidly along with semiconductor technology, Digital Signal Processing and the communication technology; The integration density of chip is increasingly high, scale is increasing, operating rate is also more and more faster, and this makes as the quality of the sheet internal clock of chip important component part even more important.Because the delay phase-locked loop of unconditional stability (delay locked loop-DLL) has " zero-lag ", low noise, low jitter (iitter) and be easy to design characteristic is fit to be applied to the clock synchronization of extensive high-speed chip.
The core component of delay phase-locked loop (DLL) is voltage controlled delay line (VCDL), and its main effect is to produce a plurality of (as 1 to i) to postpone certain hour (like t with original signal
1To t
i) new output signal.Usually each inter-stage of design time of delay is identical, i.e. t
i-t
I-1Be certain.But learn that from analyzing after adding MUX (mux) on the output node, because mux output is to the influence of input, its time of delay can be with the different and difference of node location with emulation.When the signal of former and later two selections is in same mux, the influence of the load variations part of can cancelling out each other, thus only receive the influence that first delay units delay of each mux changes.Yet; When the signal of former and later two selections during at two different mux; The variation of load can produce sudden change; This sudden change shows as in emulation and postpone the obvious saltus step that step-length occurs in handoff procedure, and the precision that this kind situation will limited delay control influences the consistency of VCDL delays at different levels.
In a word, need the urgent technical problem that solves of those skilled in the art to be exactly at present: how to improve the precision that postpones control, guarantee the consistency of VCDL delays at different levels.
Summary of the invention
Technical problem to be solved by this invention provides a kind of delay phase-locked loop, in order to improve the precision that postpones control, guarantees the consistency of VCDL delays at different levels.
In order to solve the problems of the technologies described above; The embodiment of the invention discloses a kind of delay phase-locked loop; Comprise voltage controlled delay line and MUX, wherein, said voltage controlled delay line comprises the delay cell of a plurality of cascades; Said MUX comprises a plurality of differential pair tubes; The grid of each differential pair tube is corresponding respectively to link to each other with the positive and negative differential output nodes of a delay cell, and said differential pair tube one end links to each other with earthed voltage (VSS) through sharing current source, and the other end links to each other with supply voltage (VDD) through load device; Said MUX also comprises:
Be connected first switch between differential pair tube and the shared current source;
Be connected the second switch between differential pair tube and the load device;
The output node of said MUX is between said second switch and load device;
When selecting the output node i of certain delay cell; First switch and the second switch conducting of the differential pair tube that links to each other with this output node i; First switch of other differential pair tube and second switch break off, and make current MUX be output as this output node i.
Preferably, described delay phase-locked loop also comprises:
The 3rd switch is connected the end of said differential pair tube away from supply voltage (VDD), and between the fixed level; Said the 3rd switch and first switch constitute complementary switch.
Preferably, said differential pair tube is made up of the NMOS pipe, and said load device is made up of the PMOS pipe.
Preferably, said supply voltage (VDD) inserts the source electrode of load device, and the drain electrode of said load device links to each other with the drain electrode of each differential pair tube respectively, and the source electrode of each differential pair tube links to each other with earthed voltage (VSS) through sharing current source.
Preferably, said first switch is connected between the source electrode and current source of said differential pair tube;
Said second switch is connected between the drain electrode of drain electrode and differential pair tube of said load device;
The output node of said MUX is between said second switch and corresponding load device.
Preferably, said the 3rd switch is connected between the source electrode and a fixed level of said differential pair tube.
Preferably, said differential pair tube is made up of the PMOS pipe, and said load device is made up of the NMOS pipe.
Compared with prior art, the present invention has the following advantages:
The present invention is through changing the design of traditional DLL; Increase by first switch between the shared current source of differential pair tube in mux and VSS end; And, between differential pair tube and load device, increase second switch, and the corresponding control signal of improving mux; Promptly when selecting the output node i of certain delay cell, if this output node i is connected to mux
j, then this moment mux
jControl signal make mux
jThe differential pair tube T that middle corresponding node i is connected
iFirst switch and second switch conducting, first switch of other differential pair tube and second switch break off.Thereby make the step-length that postpones in the process that mux switches, obvious saltus step can not occur; That is to say, though the signal of former and later two selections when two different mux, load can not produce sudden change yet; Thereby can guarantee DNL less than certain numerical value, improve the delay control precision of VCDL.
The present invention can also be at the end of differential pair tube away from VDD; And increase by the 3rd switch between the fixed level; Guaranteeing that the state of differential pair tube is a stationary state when the input of current differential pair tube is not used, thereby further improved the delay control precision of VCDL.
Description of drawings
Fig. 1 is the sketch map that is connected of a kind of VCDL of the present invention and mux;
Fig. 2 is the circuit structure diagram of a kind of delay phase-locked loop embodiment 1 of the present invention;
Fig. 3 is the circuit structure diagram of a kind of delay phase-locked loop embodiment 2 of the present invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, below in conjunction with accompanying drawing and embodiment the present invention done further detailed explanation.
For making those skilled in the art understand the present invention better, below further specify emulation and analytic process that the inventor herein finds inconsistent problem VDCL time of delays at different levels.
With reference to figure 1, suppose that VCDL is made up of N delay cell, be respectively 1,2,3,4 ..., i, i+1 ... N-1, N.Wherein, the output signal of i delay cell note is made n
i, simultaneously, it also is the input signal of i+1 unit.Because DLL is mostly in actual use to be high speed circuit, so delay cell uses the analogue delay unit more, and its output waveform is between sinusoidal waveform and square wave.Mux generally uses simulation mux.In order to reduce power consumption, generally adopt the method for multi-level mux, the shared mux of promptly adjacent a plurality of delay cells (being 4 shared 1 mux of delay cell among Fig. 1), a plurality of mux (mux as shown in fig. 1
1,1---mux
1, m) the output signal mux that re-uses down one deck further select, to the last select a unique output signal.
Suppose that the output signal is at t
0Got into VCDL at=0 o'clock, then at t
1The time arrive n
1, t
2The time arrive n
2..., remember that the time of delay of i delay cell when j signal of gating is τ
I, j, τ is then arranged
I, j=t
i-t
I-1, being without loss of generality, hypothesis as shown in Figure 1 limits the shared mux of per 4 delay cells, ignores the delay of mux, think to postpone mainly to cause by delay cell, then:
When selecting the 1st signal, t
1=τ
1,1
When selecting the 2nd signal, t2=τ
1,2+ τ
2,2
When selecting the 3rd signal, t3=τ
1,3+ τ
2,3+ τ
3,3
When selecting the 4th signal, t4=τ
1,4+ τ
2,4+ τ
3,4+ τ
4,4
When selecting the 5th signal, t5=τ
1,5+ τ
2,5+ τ
3,5+ τ
4,5+ τ
5,5
If all delay cell is identical, then t
iTo form straight line, t
i-t
I-1With identical.Adopt DNL (differential nonlinearity) to represent this characteristic, the independent variable of DNL is the index i of node, is output as poor that the i level postpones and the i-1 level postpones; DNL is carried out the normalizing words; To postpone, thereby be unit, can draw DNL=0 with lowest order (LSB) divided by average retardation.It is understandable that, postpone control precision preferably, should guarantee that DNL is less than certain numerical value if VCDL is had.
Yet in reality, because mux also is the load of delay cell, its output is all different (signal that is gating is all different at every turn) at every turn, and to make delay cell need inject the electric current of mux inequality at every turn, thereby make time of delay also inequality at every turn.For example, if the signal of mux output and input is identical, the electric capacity between then exporting and importing just is equivalent to " disappearance ".The phase difference (promptly refer to the poor of alternating current phases that two frequencies are identical, common span be smaller or equal to π (180 °)) of supposing output and input is Δ θ, and confirmable is that the delay of the delay cell of correspondence is the function of Δ θ; Can also confirm that this function is the periodic function of cycles 2 π, and be dull within the specific limits.Need to prove,, therefore can think τ because that phase difference θ causes that the delay of delay cell changes is very little
i=τ+f (Δ θ); Wherein, τ is that each delay cell is all identical.Emulation shows that f (Δ θ) is an odd symmetric function, and dull near Δ θ=0.Because it is very little that f (Δ θ) compares with τ, therefore can also suppose that below the output phase of i level delay cell is i* θ.
Can learn according to above derivation:
t
2-t
1＝τ
1，2+τ
2，2-τ
1，1＝(τ+f(θ))+(τ+f(0))-(τ+f(0))＝τ+f(θ)；
t
3-t
2＝τ
1，3+τ
2，3+τ
3，3-(τ
1，2+τ
2，2)＝τ+f(2θ)；
t
4-t
3＝τ+f(3θ)
And when the output signal when first mux (mux that connects 1-4 delay cell) switches to second mux (mux that connects 5-8 delay cell), this rule will be broken, that is,
t
5-t
4＝(τ
1，5+τ
2，5+τ
3，5+τ
4，5+τ
5，5)-(τ
1，4+τ
2，4+τ
3，4+τ
4，4)
Can find out from following formula, adopt traditional mux design, when second mux selected the 5th output node, first mux still selected the 1st output node (because in traditional mux design, can simplify the control logic of mux like this).
At this moment, that is:
t
5-t
4＝f(0)+f(-θ)+f(-2θ)+f(-3θ)+f(0)-f(3θ)-f(2θ)-f(θ)-f(0)+τ＝f(0)-2(f(θ)+f(2θ)+f(3θ))；
If θ is little, can f (θ) be similar to and be write as k* θ, can more clearly obtain t
5-t
4=-12* θ.In this case, can find that the step-length that postpones a tangible saltus step occurred in the process that mux switches, thereby limit the delay control precision of VCDL.To the analysis classes of other nodes seemingly, do not give unnecessary details at this.
To sum up can learn, when the signal of former and later two selections is in same mux, the influence of the load variations part of can cancelling out each other, thus only receive the influence that first delay units delay of each mux changes.When the signal of former and later two selections during at two different mux, the variation of load has produced sudden change, thereby has limited DNL.
Switch the influence to DNL in order to eliminate mux, the inventor herein creatively changes traditional DLL, specifically can be with reference to the circuit structure diagram of of the present invention a kind of delay phase-locked loop embodiment 1 shown in Figure 2; In the present embodiment, DLL comprises VCDL and mux, wherein; VCDL comprises the delay cell of a plurality of cascades; Mux comprises a plurality of differential pair tubes, T11 promptly as shown in the figure and T12, T21 and T22, T31 and T32, T41 and T42; The grid of each differential pair tube links to each other with output node in1, in2, in3, the in4 of a delay cell (Delay cell) among the VCDL respectively; Wherein, T11, T21, T31 and T41 receive in1, in2, in3, the positive differential input signal of in4 respectively, and T12, T22, T32 and T42 receive in1, in2, in3, the negative differential input signal of in4 respectively.
One end of each differential pair tube links to each other with earthed voltage VSS through sharing current source, and the other end links to each other with supply voltage VDD through load device Rload; Wherein, load device is used for increasing impedance, and current source is used to provide tail current, is a kind of universal architecture among the simulation mux.In concrete the realization, said differential pair tube can be made up of the NMOS pipe, and correspondingly, load device Rload can be made up of the PMOS pipe; Promptly as shown in Figure 2, supply voltage VDD inserts the source electrode of load device Rload, and the drain electrode of load device Rload links to each other with the drain electrode of differential pair tube, and the source electrode of differential pair tube links to each other with earthed voltage VSS through current source.
Certainly, as another kind of example, said differential pair tube also can be made up of the PMOS pipe, and correspondingly, said load device then is made up of the NMOS pipe.Practical devices for this part is selected for use, and the present invention need not to limit.
Emphasis improvements of the embodiment of the invention are, between each differential pair tube and VSS, promptly between the source electrode and current source like differential pair tube among Fig. 2, are connected with the corresponding first switch S 1a, S2a, S3a, S4a respectively; Between each differential pair tube and load device Rload, promptly between the drain electrode like the drain electrode of load device Rload among Fig. 2 and differential pair tube, be connected with corresponding second switch S1b, S2b, S3b, S4b respectively.In this case, the output node out of mux then lays respectively between said second switch S1b, S2b, S3b, S4b and the corresponding load device Rload.
It is understandable that; When not having the first switches Si a; Because a plurality of differential pair tubes are shared a current source; Then the differential input signal of certain differential pair tube possibly shared to hold and be coupled to other differential pair tube through this, and through adding this first switch, then can avoid the influence of this coupling effectively.Second switch then can make the signal of out end can not have influence on its input at certain mux during not by gating.
The another emphasis improvements of the embodiment of the invention are; Changed the control signal to mux, promptly in embodiments of the present invention, control signal inserts the said switch control end of (can comprise first switch and second switch in the present embodiment); When said switch adopts metal-oxide-semiconductor to realize; Said control signal can insert the grid of said metal-oxide-semiconductor switch, and the characteristic of corresponding said metal-oxide-semiconductor switch, sends effective control signal.For example, when adopting switching pmos to realize, then effectively control signal is a high level signal; When adopting NMOS pipe switch to realize, then effectively control signal is a low level signal.In this case, when selecting the output node i of certain delay cell, if this output node i is connected to mux
j, then this moment, control signal made mux
jThe differential pair tube T that middle corresponding node i is connected
iFirst switch and second switch conducting, first switch of other differential pair tube and second switch break off, promptly in this case, mux
JOutput then be this output node i.
In the structure of multilayer mux, use the embodiment of the invention, if the output node i of current certain delay cell of selection is connected to mux
j, then at gating mux
jMux before (refers to and mux at this
jWith layer, be positioned at this mux
jOther mux before is like mux among Fig. 1
1,1Be mux
1,2Mux before, mux
1,1, mux
1,2Be mux
1,3Mux before, control signal by that analogy) can be so that its input be in off-state, and gating mux
jMux afterwards (refers to and mux at this
jWith layer, be positioned at this mux
jOther mux afterwards is like mux among Fig. 1
1,2Be mux
1, 1Mux before, control signal by that analogy) is an outlier, does not influence the function and the performance of circuit, thereby can arbitrarily be provided with as required.In addition, if guarantee to have only mux
jOutput effective, other mux is output as high-impedance state, then can omit the mux after this layer.
As another kind of preferred embodiment of the present invention; The present invention can also comprise and is connected the end of said differential pair tube away from VDD, and the 3rd switch between the fixed level, promptly like the source electrode of differential pair tube among Fig. 2 and S1c, S2c, S3c, the S4c between the fixed level; Need to prove; Only having provided fixed level among the figure is a kind of example that does not meet the earthed voltage VSS of current source, and in concrete the realization, it all is feasible that those skilled in the art adopt any fixed level.Said the 3rd switch and first switch constitute complementary switch.That is to say that when first switch was conducting state, the 3rd switch was an off-state; Otherwise when first switch was off-state, the 3rd switch was a conducting state.
In the present embodiment; Said control signal can insert the control end of said first switch, second switch and the 3rd switch; In this case; When control signal makes mux be output as the output node i of certain delay cell, first switch of the differential pair tube that then links to each other and second switch conducting with this node i, the 3rd switch breaks off; When control signal was broken off the output node i of certain delay cell, first switch of the differential pair tube that then links to each other with this node i and second switch broke off, the 3rd switch conduction.The 3rd switch that here increases can be when the input of current differential pair tube not be used, and the state that guarantees this differential pair tube is a stationary state.
Use the embodiment of the invention,, only have the current mux can be by gating when when selecting some mux for use; Other mux before this mux will all turn-off; Then in this case, the delay before the gating signal is an identical value τ ', and the corresponding delay of gating signal itself is τ+f (Δ θ); Still be example, following derivation can be arranged in view of the above with Fig. 1:
t
2-t
1＝τ
1，2+τ
2，2-τ
1，1＝(τ+f(Δθ))+τ’-τ+f(Δθ))＝τ’；
t
3-t
2＝τ
1，3+τ
2，3+τ
3，3-(τ
1，2+τ
2，2)＝(τ+f(Δθ))+τ’+τ’-((τ+f(Δθ)+τ’)＝τ’；
t
4-t
3＝τ’；
t
5-t
4＝(τ
1，5+τ
2，5+τ
3，5+τ
4，5+τ
5，5)-(τ
1，4+τ
2，4+τ
3，4+τ
4，4)＝(τ+f(Δθ))+τ’*4-((τ+f(Δθ)+τ’*3)＝τ’。
Can find out; The step-length that the present invention postpones obvious saltus step can not occur in the process that mux switches; That is to say, though the signal of former and later two selections when two different mux, load can not produce sudden change yet; Thereby can guarantee DNL less than certain numerical value, improve the delay control precision of VCDL.
With reference to figure 3, show the structure chart of a kind of delay phase-locked loop embodiment 2 of the present invention, in the present embodiment; DLL comprises VCDL and mux, and wherein, VCDL comprises the delay cell of a plurality of cascades; Mux comprises that a plurality of inputs are to pipe; Each imports first input pipe and second input pipe that pipe is comprised series connection, T13 promptly as shown in the figure and T14, T23 and T24, T33 and T34, T43 and T44; The grid of said first input pipe and second input pipe links to each other, and links to each other with output node in1, in2, in3, the in4 of a delay cell among the VCDL respectively.
Wherein, an end of each first input pipe links to each other with supply voltage VDD through sharing current source, and an end of each second input pipe links to each other with earthed voltage VSS through sharing current source.In concrete the realization, said first input pipe can be managed for PMOS, and correspondingly, second input pipe can be managed for NMOS; Promptly like supply voltage VDD among Fig. 3 through sharing the source electrode that current source inserts first input pipe, the drain electrode of first input pipe links to each other with the drain electrode of second input pipe, the source electrode of second input pipe links to each other with earthed voltage VSS through shared current source.
Certainly, as another kind of example, said first input pipe also can be for NMOS manages, and correspondingly, said second input pipe also can be managed for PMOS.Practical devices for this part is selected for use, and the present invention need not to limit.
Emphasis improvements of the embodiment of the invention are that mux can also comprise following switches set:
Be connected the switch between the shared current source of said first input pipe and vdd terminal and be connected said second input pipe and the shared current source of VSS end between first switches set formed of switch; Promptly like Sp1a, Sp2a, Sp3a, Sp4a between the shared current source of the source electrode that is connected first input pipe among Fig. 3 and vdd terminal; And, Sn1a, Sn2a, Sn3a, Sn4a between the shared current source of the source electrode of second input pipe and VSS end; That is to say that Sp1a and Sn1a, Sp2a and Sn2a, Sp3a and Sn3a, Sp4a and Sn4a promptly are respectively input to pipe T13 and T14, T23 and T24, first switches set of T33 and T34, T43 and T44;
Be connected said first input pipe away from the switch of the end of VDD and be connected the second switch group that said second input pipe is formed away from the switch of the end of VSS; Promptly like Sp1b, Sp2b, Sp3b, Sp4b between the output node out of the drain electrode that is connected first input pipe among Fig. 3 and mux; And, Sn1b, Sn2b, Sn3b, Sn4b between the output node out of the drain electrode of second input pipe and mux; That is to say that Sp1b and Sn1b, Sp2b and Sn2b, Sp3b and Sn3b, Sp4b and Sn4b promptly are respectively input to pipe T13 and T14, T23 and T24, the second switch group of T33 and T34, T43 and T44.
In the present embodiment, the output node out of mux is between two switches of this second switch group, promptly as between the Sp1b and Sn1b among Fig. 3, between Sp2b and the Sn2b, between Sp3b and the Sn3b, between Sp4b and the Sn4b.
In embodiments of the present invention; Said control signal can insert the said switch control end of (can comprise first switches set and second switch group in the present embodiment); When all adopting metal-oxide-semiconductor to realize when said switch; Said control signal can insert the grid of said metal-oxide-semiconductor switch, and the characteristic of corresponding said metal-oxide-semiconductor switch, sends effective control signal.For example, when adopting switching pmos to realize, then effectively control signal is a high level signal; When adopting NMOS pipe switch to realize, then effectively control signal is a low level signal.In this case; When control signal is selected the output node i of certain delay cell; The input that links to each other with this output node i is to first switches set and the conducting of second switch group of pipe; Other input is broken off first switches set and the second switch group of pipe, makes current mux be output as this output node i.
In the present embodiment, said first switches set is used to avoid the input signal of certain input pipe to be coupled to other input pipe through this shared end equally.The second switch group then can make the signal of out end can not have influence on its input at certain mux during not by gating equally.
As another kind of preferred embodiment of the present invention; The present invention can also comprise and is connected first input pipe near an end and the switch between first fixed level of supply voltage VDD and be connected the 3rd switches set that second input pipe is formed near an end and the switch between second fixed level of earthed voltage VSS; Promptly as being connected Sp1c, Sp2c, Sp3c, the Sp4c between first input pipe and the supply voltage VDD among Fig. 3; And, be connected switch S n1c, Sn2c, Sn3c, Sn4c between second input pipe and the earthed voltage VSS; That is to say that Sp1c and Sn1c, Sp2c and Sn2c, Sp3c and Sn3c, Sp4c and Sn4c promptly are respectively input to pipe T13 and T14, T23 and T24, the 3rd switches set of T33 and T34, T43 and T44.Need to prove; Only having provided first fixed level among the figure is a kind of supply voltage VDD that does not connect current source, and second fixed level is a kind of example that does not meet the earthed voltage VSS of current source; In concrete the realization, it all is feasible that those skilled in the art adopt any fixed level.Said the 3rd switches set and first switches set constitute complementary switch.Promptly when first switches set was conducting state, the 3rd switches set was an off-state; Otherwise when first switches set was off-state, the 3rd switches set was a conducting state.
In the present embodiment; Said control signal can insert the control end of said first switch, second switch and the 3rd switch; In this case; When control signal makes mux be output as the output node i of certain delay cell, first switches set of the differential pair tube that then links to each other and the conducting of second switch group with this node i, the 3rd switches set is broken off; When control signal was broken off the output node i of certain delay cell, first switches set of the differential pair tube that then links to each other with this node i and second switch group were broken off, the 3rd switches set conducting.The 3rd switches set that here increases can be when the input of current differential pair tube not be used, and the state that guarantees this differential pair tube is a stationary state.
Certainly, in concrete the realization, said switch can adopt any switching device of prior art, is not limited to the example of above-mentioned metal-oxide-semiconductor, and the present invention need not this to limit.
The embodiment of the invention can be applicable in reality in the various delay phase-locked loops; For example; A kind of typical delays phase-locked loop can comprise phase discriminator, charge pump, loop filter, biasing generator, VCDL and mux of the present invention; Because using the delay precision of VCDL of the present invention can be controlled, thereby can also make that in reality the time-delay configuration of delay phase-locked loop is more flexible.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.
At last; Also need to prove; In this article; Relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint relation or the order that has any this reality between these entities or the operation.
More than a kind of delay phase-locked loop provided by the present invention has been carried out detailed introduction; Used concrete example among this paper principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that on embodiment and range of application, all can change, in sum, this description should not be construed as limitation of the present invention.
Claims (7)
1. a delay phase-locked loop is characterized in that, comprises voltage controlled delay line and MUX; Wherein, Said voltage controlled delay line comprises the delay cell of a plurality of cascades, and said MUX comprises a plurality of differential pair tubes, and the grid of each differential pair tube is corresponding respectively to link to each other with the positive and negative differential output nodes of a delay cell; Said differential pair tube one end links to each other with earthed voltage (VSS) through sharing current source, and the other end links to each other with supply voltage (VDD) through load device; Said MUX also comprises:
Be connected first switch between differential pair tube and the shared current source;
Be connected the second switch between differential pair tube and the load device;
The output node of said MUX is between said second switch and load device;
When selecting the output node i of certain delay cell; First switch and the second switch conducting of the differential pair tube that links to each other with this output node i; First switch of other differential pair tube and second switch break off, and make current MUX be output as this output node i.
2. delay phase-locked loop as claimed in claim 1 is characterized in that, also comprises:
The 3rd switch is connected the end of said differential pair tube away from supply voltage (VDD), and between the fixed level; Said the 3rd switch and first switch constitute complementary switch.
3. delay phase-locked loop as claimed in claim 2 is characterized in that, said differential pair tube is made up of the NMOS pipe, and said load device is made up of the PMOS pipe.
4. delay phase-locked loop as claimed in claim 3; It is characterized in that; Said supply voltage (VDD) inserts the source electrode of load device, and the drain electrode of said load device links to each other with the drain electrode of each differential pair tube respectively, and the source electrode of each differential pair tube links to each other with earthed voltage (VSS) through sharing current source.
5. delay phase-locked loop as claimed in claim 4 is characterized in that, said first switch is connected between the source electrode and current source of said differential pair tube;
Said second switch is connected between the drain electrode of drain electrode and differential pair tube of said load device;
The output node of said MUX is between said second switch and corresponding load device.
6. delay phase-locked loop as claimed in claim 5 is characterized in that, said the 3rd switch is connected between the source electrode and a fixed level of said differential pair tube.
7. according to claim 1 or claim 2 delay phase-locked loop is characterized in that, said differential pair tube is made up of the PMOS pipe, and said load device is managed by NMOS and formed.
Priority Applications (1)
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| CN201010033860A CN101777910B (en) | 2010-01-08 | 2010-01-08 | Delay phase locked loop |
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| CN201010033860A CN101777910B (en) | 2010-01-08 | 2010-01-08 | Delay phase locked loop |
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| CN201210151859.3A Division CN102684687B (en) | 2010-01-08 | 2010-01-08 | Delay-locked loop |
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| CN101777910A CN101777910A (en) | 2010-07-14 |
| CN101777910B true CN101777910B (en) | 2012-10-17 |
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| CN103684438B (en) * | 2013-11-25 | 2016-06-08 | 龙芯中科技术有限公司 | Delay phase-locked loop |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5210450A (en) * | 1990-04-16 | 1993-05-11 | Tektronix, Inc. | Active selectable digital delay circuit |
| CN1489289A (en) * | 2002-08-29 | 2004-04-14 | 株式会社东芝 | Differential data transmitter |
| CN101176254A (en) * | 2005-03-21 | 2008-05-07 | 麦比乌斯微系统公司 | Frequency controller for a monolithic clock generator and timing/frequency refrence |
-
2010
- 2010-01-08 CN CN201010033860A patent/CN101777910B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5210450A (en) * | 1990-04-16 | 1993-05-11 | Tektronix, Inc. | Active selectable digital delay circuit |
| CN1489289A (en) * | 2002-08-29 | 2004-04-14 | 株式会社东芝 | Differential data transmitter |
| CN101176254A (en) * | 2005-03-21 | 2008-05-07 | 麦比乌斯微系统公司 | Frequency controller for a monolithic clock generator and timing/frequency refrence |
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| CN101777910A (en) | 2010-07-14 |
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