JP2019080120A - High-frequency switch device - Google Patents

Abstract

To provide a high-frequency switch device capable of achieving acceleration of a switching speed without need for adding a large output capacitance to a power supply.SOLUTION: First control signals vc1a, vc2a generated by a decoder circuit 3 on the basis of a control signal VC input from the outside are level-shifted by level shift buffer circuits 5-1, 5-2 as second control signals vc1b, vc2b with output timing adjusted by timing adjustment circuits 4-1, 4-2, which are input into high-frequency pass switch circuits 8-1, 8-2, so that both of the high-frequency pass switch circuits 8-1, 8-2, after turning off, are line-switched, thereby achieving rapid line switching without delay.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a high frequency switch, and more particularly, to a high speed switch operation in a configuration in which switch elements are connected in multiple stages in series.

  In recent years, high-frequency switches, such as SPDT (Single Pole Double Throw) switches, etc., are manufactured using fine process technology, so the gate length becomes short and one FET (field effect transistor) It is becoming more difficult to control high-power signals sufficiently.

Therefore, a configuration in which semiconductor switch elements such as FETs are connected in multiple stages may be adopted (for example, Patent Document 1 etc.).
A conventional circuit example of a high frequency switch device having a high frequency switch in which such semiconductor switch elements are connected in multiple stages in series will be described with reference to FIG. 13 to FIG.
This high frequency switch device is a configuration example in the case of an SPDT switch, and is roughly divided into a high frequency circuit unit 100A and a control circuit unit 200A (see FIG. 13).

The high frequency circuit unit 100A includes a high frequency path switch circuit 8A-1 connected between the high frequency input / output common terminal PC, the high frequency input / output individual terminals P1 and P2, and the high frequency input / output common terminal PC and the high frequency input / output individual terminal P1. And a high frequency path switch circuit 8A-2 connected between the high frequency input / output common terminal PC and the high frequency input / output individual terminal P2.
The high frequency pass switch circuits 8A-1 and 8A-2 are configured by connecting a plurality of FETs in series.

Control circuit unit 200A includes a positive voltage power supply circuit (indicated as "+ POWER" in FIG. 13) 1A, a negative voltage power supply circuit (indicated as "-POWER" in FIG. 13) 2A, and a decoder (indicated in FIG. 13). And the level shift buffer circuits 5A-1 and 5A-2, the output capacitor 6A, and the decoupling capacitors 7A-1 and 7A-2.
The positive voltage power supply circuit 1A outputs a positive voltage VON for making the high frequency switch conductive and the power supply voltage VH of the decoder 3A and the level shift buffer circuits 5A-1 and 5A-2. The voltages VON and VH may be the same voltage.
The negative voltage power supply circuit 2A outputs a negative voltage VOFF for turning off the high frequency switch.

  In such a conventional circuit, for example, as shown in FIG. 14, the path between the high frequency input / output common terminal PC and the high frequency input / output individual terminal P1 conducts, and between the high frequency input / output common terminal PC and the high frequency input / output individual terminal P2. In the state (state I) in which the path is interrupted, the path between the high frequency input / output common terminal PC and the high frequency input / output individual terminal P1 is interrupted, and the path between the high frequency input / output common terminal PC and the high frequency input / output individual terminal P2 is conductive The circuit operation at the time of switching to the state (state III) will be described below as an example.

First, in the initial state (state I), the input signal vc1c of the level shift buffer circuit 5A-1 is a voltage level corresponding to the logic value High to turn on the high frequency pass switch circuit 8A-1 of the PC-P1 path. (See FIGS. 15A and 15B).
Further, the input signal vc2c of the level shift buffer circuit 5A-2 is at a voltage level corresponding to the logic value Low in order to turn off the high frequency path switch circuit 8A-2 of the PC-P2 path (see FIG. And FIG. 15 (C)).

  In this state, when the logic of control signal VC externally input to decoder 3A is switched to switch the paths of high frequency path switch circuits 8A-1 and 8A-2, level shift buffer circuits 5A-1 and 5A are switched. As shown in FIGS. 15B and 15C, the input signals vc1c and vc2c of −2 are output from the decoding circuit 3A substantially simultaneously and the logic is inverted (state III).

By changing the logic of the input signal vc1c of the level shift buffer circuit 5A-1, in the level shift buffer circuit 5A-1, the voltage of the output signal is switched to the negative voltage of the negative voltage power supply 2A, and the high frequency pass switch circuit 8A The gate capacitance of -1 is charged from high level (VON) to low level (VOFF).
The charging path at this time is a path iss0 passing from the output capacitor 6A of the negative voltage power supply circuit 2A to the level shift buffer circuit 5A-1, as shown by a dotted line in FIG.

On the other hand, in the level shift buffer circuit 5A-2, the voltage of the output signal is switched to the positive voltage of the positive voltage power supply circuit 1A in the level shift buffer circuit 5A-2 by the logic change of the input signal vc2c. The gate capacitance of 8A-2 is charged from low level (VOFF) to high level (VON).
The charging path at this time is from the positive power supply voltage 1A to the path idd0 passing through the level shift buffer circuit 5A-2, as shown by the dotted line in FIG.

JP 2012-9981 A

  In the above-described conventional circuit, the high frequency pass switch circuits 8A-1 and 8A-2 are configured by connecting a large number of switch FETs in series, but the gate width is about several mm in order to reduce the on resistance. Therefore, the gate capacitance is very large such as several tens to 100 pF.

  The positive voltage power supply circuit 1A is realized by using a circuit configuration called LDO (Low Dorp Out) having a small input / output voltage difference and the like, and has a relatively high current driving capability. Therefore, the high frequency path switch circuits 8A-1 and 8A Even when charging a large gate capacitance such as -2, there is no delay as large as when charging a negative voltage.

In order to charge such a large gate capacitance instantaneously, the output capacitor 6A of the negative voltage power supply circuit 2A needs a larger capacitance than the gate capacitance.
However, because it is practically difficult to secure the required large capacitance value due to the constraints of the semiconductor chip, it is practically impossible to select a feasible value within the range of the constraint of the semiconductor chip. Absent.

  Therefore, in the conventional circuit, when the paths of the high frequency path switch circuits 8A-1 and 8A-2 are switched, a delay in signal propagation occurs due to the shortage of the output capacity of the negative voltage power supply circuit 2A. There is a problem that smooth route switching can not be secured.

  The present invention has been made in view of the above situation, and in a configuration in which semiconductor switch elements are connected in multiple stages in series, a high frequency switch device capable of increasing the switching speed without adding a large output capacity to the power supply. It is provided.

In order to achieve the above object of the present invention, a high frequency switch device according to the present invention is:
The high frequency path switch circuit has a high frequency path switch circuit in which a plurality of semiconductor switch elements are connected in series, and the high frequency path switch circuit is provided between one high frequency input / output common terminal and a predetermined number of high frequency input / output individual terminals. A control circuit for generating and outputting a control signal for controlling the operation of the high frequency path switch circuit, and the control circuit generates and outputs the control signal using both positive and negative power supplies to output the high frequency path switch circuit In the high frequency switch device configured to be able to control the operation of
The control circuit sets an output timing of the control signal such that transition to a desired operation state can be made via a state in which all the high frequency path switch circuits are turned off when switching the path of the high frequency path switch circuit. It is constructed as possible.

  According to the present invention, at the time of path switching of a high frequency path switch circuit formed of a plurality of semiconductor switch elements, all semiconductor switch elements are configured to transition to a desired operating state via an off state Thus, in addition to the gate capacitance of the semiconductor switching device in the off state, the decoupling capacitance can be used as the output capacitance of the negative voltage power supply, so that deterioration of the negative voltage during off charge can be suppressed. In this way, the off operation of the semiconductor switching device can be reliably speeded up, and a highly reliable high frequency switching device can be provided.

It is a circuit diagram showing the 1st example of circuit composition of the high frequency switch device in an embodiment of the invention. It is a circuit diagram showing an example of circuit composition of a high frequency pass switch circuit. It is a circuit diagram showing an example of circuit composition of a timing adjustment circuit. FIG. 4A is a timing chart showing a change of an input signal, and FIG. 4B is a timing chart showing a change of an output signal. FIG. 5A is a timing chart showing changes in input voltage, and FIG. 5B is a timing chart showing changes in output voltage. FIG. 6A is a timing chart showing a change in control signal VC input to the decoder circuit, and FIG. 6B is a timing adjustment showing a change in control signal voltage in the first circuit configuration example. FIG. 6C is a timing chart showing a change of the control signal vc2b outputted from the timing adjustment circuit. It is an explanatory view explaining change of a conduction state of a high frequency input-output common terminal and a high frequency input-output individual terminal in the example of the 1st circuit composition. FIG. 7 is a circuit diagram illustrating a charging path when the operating state of the circuit changes from state I to state II in the first circuit configuration example. FIG. 7 is a circuit diagram illustrating a charging path when the operating state of the circuit is state III in the first circuit configuration example. It is a characteristic line which shows the simulation result of the gate voltage in a 1st example of a circuit structure with the simulation result of a conventional circuit. It is a circuit diagram showing the example of the 2nd circuit configuration of the high frequency switch device in an embodiment of the invention. It is a circuit diagram showing an example of circuit composition of a high frequency pass switch circuit and a high frequency shunt switch circuit in the 2nd example of circuit composition. It is a circuit diagram showing an example of circuit composition of the conventional high frequency switch device. It is explanatory drawing explaining the operation state between the input-output terminals in a conventional circuit. FIG. 15A is a timing chart showing a change in control signal VC input to the decoder circuit, and FIG. 15B is a signal outputted from the decoder circuit. FIG. 15C is a timing chart showing the change of the control signal vc2c output from the decoder circuit. It is a circuit diagram explaining the charge course in the conventional circuit.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 12.
The members, arrangements, and the like described below do not limit the present invention, and various modifications can be made within the scope of the present invention.
First, a first circuit configuration example will be described with reference to FIG.
The circuit configuration example in FIG. 1 is a configuration example in the case of an SPDT switch, and the high frequency switch device in the embodiment of the present invention is roughly divided into a high frequency circuit unit 100 and a control circuit unit 200. It has become.

  The high frequency circuit unit 100 includes one high frequency input / output common terminal (denoted as "PC" in FIG. 1) 31 and two high frequency input / output individual terminals (in FIG. 1, "P1" and "P2" respectively). Notation) 32-1, 32-2, between the high frequency input / output common terminal 31 and the first high frequency input / output individual terminal 32-1, the high frequency input / output common terminal 31 and the second high frequency input / output individual terminal 32- And the high-frequency path switch circuits 8-1 and 8-2 connected respectively.

  In the first circuit configuration example, as described above, since the configuration example in the case of the SPDT switch is shown, there are two high frequency input / output individual terminals 32-1 and 32-2. The high frequency switch device is not limited to the application to the SPDT switch. That is, the high frequency input / output individual terminals can be applied to n SPnT switches.

FIG. 2 shows an example of the circuit configuration of the high frequency path switch circuits 8-1 and 8-2, and the high frequency path switch circuits 8-1 and 8-2 will be described below with reference to this figure.
The high frequency pass switch circuits 8-1 and 8-2 are configured as semiconductor switch elements in which k pieces of FETs (field effect transistors) 21-1 to 21-k are connected in series.

  The high frequency path switch circuit 8-1 has a high frequency input / output common terminal 31 and a second high frequency input / output common terminal 31 between the high frequency input / output common terminal 31 and the first high frequency input / output individual terminal 32-1. The FETs 21-1 to 21-k are connected in series between the high frequency input / output individual terminals 32-2.

The reason why the plurality of FETs are connected in series in this way is as follows.
That is, in recent years, in the case of a high frequency switch IC used in a wireless communication device or the like, the voltage amplitude of the high frequency signal to be handled reaches a peak voltage of several tens of volts.
On the other hand, since the switch FET is manufactured using a fine process, its operating withstand voltage is about 2.5 V and can not satisfy the withstand voltage required for the high frequency switch IC with only one switch FET. . Therefore, it is for securing a desired withstand voltage by connecting a plurality in series.

  In order to maintain a high impedance in the high frequency band, the gate resistors (the gates of the FETs 21-1 to 21-k and the output stages of the level shift buffer circuits 5-1 and 5-2 respectively) In FIG. 2, “RG11”, “RG12”, “RG13”... “RG1k”) 22-1 to 22-k are connected.

  Furthermore, in each of the FETs 21-1 to 21-k, a drain-source resistor (in FIG. 2, “RDS11”, “RDS12”, “RDS12”, RDS 13 "..." RDS 1 k ") 23-1 to 23-k are connected.

  The control circuit unit 200 includes a positive voltage power circuit (denoted as "+ POWER" in FIG. 1) 1, a negative voltage power circuit (denoted as "-POWER" in FIG. 1) 2 and a decoder (in FIG. 1). (Denoted as “DEC”) 3, timing adjustment circuits 4-1 and 4-2, level shift buffer circuits 5-1 and 5-2, output capacitor 6, and decoupling capacitors 7-1 and 7-2 Is configured.

The positive voltage power supply circuit 1 generates and outputs a positive voltage (VON> 0) based on a power supply input voltage VDD applied from the outside. Such a power supply circuit is realized, for example, by providing a regulator IC or the like called LDO (Low Dorp Out) having a small input / output voltage difference on a semiconductor substrate.
The output voltage of the positive voltage power supply circuit 1 is applied to the positive voltage input terminals of the level shift buffer circuits 5-1 and 5-2. The positive voltage power supply circuit 1 may be used as a positive power supply of the decoder circuit 3.

The negative voltage power supply circuit 2 generates and outputs a negative voltage (VOFF <0) based on the power supply input voltage VDD applied from the outside.
The negative voltage power supply circuit 2 is realized by using, for example, the oscillation circuit 9 and the charge pump circuit 10, as is well known.
The output voltage of the negative voltage power supply circuit 1 is applied to the negative voltage input terminals of the level shift buffer circuits 5-1 and 5-2.

The decoder circuit 3 decodes the control signal VC input from the outside to generate and output a plurality of first control signals.
The plurality of first control signals output from the decoder circuit 3 are input to the timing adjustment circuits 4-1 and 4-2, respectively. The decoder circuit 3 in the first circuit configuration example generates and outputs two first control signals vc1a and vc2a.

The timing adjustment circuit 4-1, 4-2 generates and outputs a second control signal at a predetermined timing according to the high level and low level of the first control signal described above, as described in detail later. .
The second control signals output from the timing adjustment circuits 4-1 and 4-2 are input to the level shift buffer circuits 5-1 and 5-2, respectively.

  FIG. 3 shows a specific circuit configuration example of the timing adjustment circuit 4-1, 4-2, and FIG. 4 shows a timing for explaining the timing of change of input / output signals of the timing adjustment circuit 4-1, 4-2. Charts are shown respectively, and a specific circuit configuration example of the timing adjustment circuits 4-1 and 4-2 will be described below with reference to these figures.

First, the circuit configuration of the timing adjustment circuits 4-1 and 4-2 illustrated in FIG. 3 will be described.
Each of the timing adjustment circuits 4-1 and 4-2 includes an FET 41, two buffer elements 42-1 and 42-2, one inverting element 43, a resistor 44, and a capacitor 45. It has been configured.

  An external input signal is applied to the input terminal of the first buffer element 42-1, while the output terminal is the input terminal of the second buffer element 42-2 via the resistor 44. As well as to the input terminal of the inverting element 43.

The output terminal of the inverting element 43 is connected to the gate of the FET 41, the drain of the FET 41 is connected to the input terminal of the second buffer element 42-2, and the source of the FET 41 is connected to the ground.
In addition, a capacitor 45 is connected between the connection point of the resistor 44 and the input terminal of the second buffer element 42-2 and the ground.

Next, the timing of the change of the input / output signal in such a configuration will be described with reference to FIG.
When input signal vin1 transitions from voltage level VL corresponding to logic value Low to voltage level VH corresponding to logic value High, output signal vout1 is delayed by time Trd and output from second buffer element 42-2 (Refer FIG. 4 (A) and FIG. 4 (B)).

  On the other hand, when input signal vin1 transitions from voltage level VH corresponding to logic value High to voltage level VL corresponding to logic value Low, output signal vout1 is delayed by time Tfd and the second buffer element 42-2 is turned on. Output (see FIG. 4A and FIG. 4B).

Here, the delay time Trd when the output signal vout1 transitions from the logic low to the voltage level corresponding to the logic high, and the delay time Tfd when transitioning from the logic high to the voltage level corresponding to the logic low are The adjustment and setting are made so as to create a period in which the gate control signals of the high frequency path switch circuits 8-1 and 8-2 are all in the off state.
That is, in the first circuit configuration example, the circuit constant is set such that Trd> Tfd.

  Next, the level shift buffer circuits 5-1, 5-2 perform the voltage amplitude of the second control signals vc1b, vc2b output from the timing adjustment circuits 4-1, 4-2 as the bias value of the high frequency switch (FET). The level is shifted to the high frequency path switch circuits 8-1 and 8-2 as gate control signals.

FIG. 5 shows a timing chart for explaining the level shift operation of the level shift buffer circuits 5-1, 5-2, and the level shift operation will be described below with reference to this figure.
The level shift buffer circuits 5-1 and 5-2 output the negative voltage VOFF generated by the negative power supply circuit 2 when the signal of the voltage level VL corresponding to the logic value Low is input (FIG. 5A). (See FIG. 5 (B)) On the other hand, when a signal of voltage level VH corresponding to the logic value High is input, the positive voltage VON generated by the positive voltage power supply circuit 1 is output (FIG. 5 (A) and FIG. 5 (B)).

The output capacitor 6 is connected between the output of the negative voltage power supply circuit 2 and the ground. The output capacitor 6 is charged with a negative voltage (VOFF) and has a function of stabilizing the output voltage (VOFF) of the negative voltage power supply circuit 2.
Decoupling capacitors 7-1 and 7-2 are connected to the ground at the outputs of level shift buffer circuits 5-1 and 5-2.
The decoupling capacitors 7-1 and 7-2 are provided to electrically separate the high frequency circuit unit 100 and the control circuit unit 200.

Next, the circuit operation in such a configuration will be described with reference to FIG. 6 to FIG.
The circuit operation at the transition from the state I, which is the initial state, to the state III (see FIG. 7) will be described below.
Here, in the state I, the path between the high frequency input / output common terminal 31 and the first high frequency input / output individual terminal 32-1 is conducted, and the high frequency input / output common terminal 31 and the second high frequency input / output individual terminal 32-2 Is defined as a state in which the route between them is blocked (see FIG. 7).
In the state III, the path between the high frequency input / output common terminal 31 and the first high frequency input / output individual terminal 32-1 is cut off, and between the high frequency input / output common terminal 31 and the second high frequency input / output individual terminal 32-2. Is defined as being in a conducting state (see FIG. 7).

First, in the initial state (state I), the input signal vc1b of the level shift buffer circuit 5-1 is a high frequency path switch circuit of a path between the high frequency input / output common terminal 31 and the first high frequency input / output individual terminal 32-1. In order to make 8-1 conductive, the voltage level corresponds to the logic value High (see FIGS. 6A and 6B).
Further, the input signal vc 2 b of the level shift buffer circuit 5-2 is for blocking the high frequency path switch circuit 8-2 in the path between the high frequency input / output common terminal 31 and the second high frequency input / output individual terminal 32-2. The voltage level corresponds to the logic value Low (see FIGS. 6A and 6C).

  Next, when the logic of the control signal vc is switched to switch the paths of the high frequency path switch circuits 8-1 and 8-2, the decode circuit 3 outputs the first control signals vc1a and vc2a. The first control signal vc1a is input to the timing adjustment circuit 4-1, and the first control signal vc2a is input to the timing adjustment circuit 4-2.

The first control signal vc1a is input to the timing adjustment circuit 4-1, delayed for time Tfd, and then output as the second control signal vc1b (see FIGS. 6A and 6B). It is input to the shift buffer circuit 5-1.
On the other hand, the first control signal vc2a is input to the timing adjustment circuit 4-2, delayed for time Trd, and then output as the second control signal vc2b (see FIGS. 6A and 6C). , Level shift buffer circuit 5-2.

In the high frequency switch device according to the embodiment of the present invention, the second control signal vc1 b, so that all FET gates are all biased to the off state when switching the paths of the high frequency path switch circuits 8-1 and 8-2. The rising and falling timings of the vc 2 b are adjusted (see FIGS. 6A to 6C), and Trd> Tfd is satisfied.
That is, as shown in FIG. 7, the path switching of the high frequency path switch circuits 8-1 and 8-2 is different from the conventional one, from state I to state II to state III or state III to state State I is reached via II.

In state II, the level of the second control signal vc2b is the same as state I and corresponds to the logic value Low, so the output of the level shift buffer circuit 5-2 is maintained at the negative voltage (VOFF). Become.
On the other hand, since the level of the second control signal vc1b transitions from the level corresponding to the logic value High to the level corresponding to the logic value Low, in the level shift buffer circuit 5-1, the positive voltage (VON) to the negative voltage ( The output is switched to VOFF.
As a result, the gate capacitance of the FET of the high frequency pass switch circuit 8-1 is charged from the high level (VON) to the low level (VOFF).

  In this case, as shown in FIG. 8, in addition to the path iss0 passing from the output capacitor 6 of the negative voltage power supply circuit 2 to the level shift buffer circuit 5-1, the charge path is a high frequency pass switch circuit 8- From the decoupling capacitor 7-2 charged with the gate capacitance of 2 and off bias, two paths of paths iss2 are generated through the level shift buffer circuit 5-2.

On the other hand, in the conventional circuit (see FIG. 13), the charging path of the gate capacitance of the high frequency path switch circuit 8A-1 is only the path iss0 (see FIG. 16).
Therefore, in the high-frequency switch device according to the embodiment of the present invention, as described above, charging of the gate capacitance of high-frequency path switch circuit 8-1 is performed by two paths iss0 and path iss2. It is possible to charge in a short time sooner.

In state III, since the second control signal vc2 b transitions from low level to high level, the output of the level shift buffer circuit 5-2 is switched from the negative voltage (VOFF) to the positive voltage (VON), The gate capacitance of the high frequency pass switch circuit 8-2 is charged to the high level.
In this case, as shown in FIG. 9, the charging path is a path idd0 passing from the positive voltage power supply circuit 1 to the level shift buffer circuit 5-2.

The positive voltage power supply circuit 1 is realized using a circuit configuration or the like called LDO (Low Dorp Out) having a small input / output voltage difference. Therefore, the current drivability is relatively high, and even when charging large gate capacitances such as the high-frequency path switch circuits 8-1 and 8-2, a delay similar to that in the case of a negative voltage does not occur.
As described above, in the high-frequency switch device according to the embodiment of the present invention, the path switching of the high-frequency path switch circuits 8-1 and 8-2 is reliably performed at high speed as compared with the conventional circuit. .

FIG. 10 shows a simulation result of the charging time when charging the gate capacitances of the high frequency path switch circuits 8-1 and 8-2 from high level to low level, and the figure will be described below.
In FIG. 10, the simulation result of the high frequency switch device according to the embodiment of the present invention is represented by a solid line, and the simulation result of the conventional circuit (see FIG. 13) is represented by a dotted line.

  In the case of the conventional circuit, while the time taken for the gate potential of the high frequency path switch circuits 8-1 and 8-2 to reach the threshold of the FET is t2 in the case of the high frequency switch device in the embodiment of the present invention. Time t1 (t1> t2), which is longer than time t2, the high frequency switching device according to the embodiment of the present invention reliably switches the paths of high frequency path switching circuits 8-1 and 8-2 faster than the conventional circuit. Can be confirmed.

  In the first circuit configuration example described above, the high-frequency path switch circuits 8-1 and 8-2 are SPDT switches, but in the case of the SPnT configuration, the level shift buffer circuit 5 and decoupling are Since the number of ring capacitors 7 and the number of high-frequency path switch circuits 8 in the off state are also (n-1), a greater effect can be expected.

Next, a second circuit configuration example will be described with reference to FIGS. 11 and 12. In addition, about the component same as the component shown by FIG. 1, the same code | symbol is attached | subjected, the detailed description is abbreviate | omitted, and below, it demonstrates focusing on a different point.
While the first example of the circuit configuration described above is configured to have two high frequency pass switch circuits 8-1 and 8-2, the second example of the circuit configuration is one high frequency pass switch circuit 8 In addition, the high-frequency shunt switch circuit 13 is newly added.

  In this configuration, one level shift buffer circuit 5-1 is connected to the high frequency path switch circuit 8, and the other level shift buffer circuit 5-2 is connected to the high frequency shunt switch circuit 13.

FIG. 12 shows a specific circuit configuration example of the high frequency path switch circuit 8 and the high frequency shunt switch circuit 13. The circuit configuration will be described below with reference to this figure.
The high frequency path switch circuit 8 is the same as the circuit configuration shown in FIG. 2 above, so the detailed description thereof will not be repeated here.

The high frequency shunt switch circuit 13 is connected in series between the high frequency input / output individual terminal (denoted as "Pn" in FIG. 12) 32-1 and the ground terminal.
The high-frequency shunt switch circuit 13 is provided by directly connecting a plurality of FETs (represented as "S11", "S12", "S13" ... "S1k" in FIG. 12) 24-1 to 24-k. It is done.

  In order to maintain a high impedance in the high frequency band between the gate of each of the FETs 24-1 to 24-k and the output terminal of the level shift buffer circuit 5-2, a gate resistor (in FIG. "SRG11", "SRG12", "SRG13", ... "SRG1k") 25-1 to 25-k are connected.

  Further, in each of the FETs 24-1 to 24-k, a drain-source resistor (in FIG. 12, “SRDS11”, “SRDS12”, SRDS 13 "..." SRDS 1 k ") 26-1 to 26-k are connected.

  The high frequency shunt switch circuit 13 becomes conductive when the high frequency path switch circuit 8 is in the cut off state (non-conductive state), releases the high frequency power leaked from the high frequency path switch circuit 8 to the ground side. I am trying to improve the blocking characteristics.

On the other hand, when the high frequency path switch circuit 8 is in the on state, the high frequency shunt switch circuit 13 is in the off state. Thus, the high frequency signal passing through the high frequency path switch circuit 8 can pass without being affected by the high frequency shunt switch circuit 13.
Thus, the high frequency path switch circuit 8 and the high frequency shunt switch circuit 13 operate in reverse logic.

  Therefore, as described in the first circuit configuration example, when switching the logic of the control signal to the high frequency path switch circuit 8 and the high frequency shunt switch circuit 13, both the high frequency path switch circuit 8 and the high frequency shunt switch circuit 13 are off. By setting the circuit constants of the timing adjustment circuits 4-1 and 4-2 so as to be in the state (see the state II in FIG. 7), the delay time of the switching time can be avoided as in the first circuit configuration example. It has become.

  The present invention can be applied to a high frequency switch device where it is desired to secure a switching speed without adding a large output capacity to a power supply.

DESCRIPTION OF SYMBOLS 1 ... Positive voltage power supply circuit 2 ... Negative voltage power supply circuit 3 ... Decoder circuit 4-1, 4-2 ... Timing adjustment circuit 5-1, 5-2 ... Level shift buffer circuit 6 ... Output capacitor 7-1, 7-2 ... Decoupling capacitor 8-1, 8-2 ... High frequency path switch circuit 100 ... High frequency circuit section 200 ... Control circuit section

Claims (2)

The high frequency path switch circuit has a high frequency path switch circuit in which a plurality of semiconductor switch elements are connected in series, and the high frequency path switch circuit is provided between one high frequency input / output common terminal and a predetermined number of high frequency input / output individual terminals. A control circuit for generating and outputting a control signal for controlling the operation of the high frequency path switch circuit, and the control circuit generates and outputs the control signal using both positive and negative power supplies to output the high frequency path switch circuit In the high frequency switch device configured to be able to control the operation of
The control circuit sets an output timing of the control signal such that transition to a desired operation state can be made via a state in which all the high frequency path switch circuits are turned off when switching the path of the high frequency path switch circuit. High frequency switch device characterized in that it is constituted possible. A semiconductor switch element is used, and a high frequency shunt switch circuit is provided to connect the input stage of the high frequency path switch circuit to the ground when the high frequency path switch circuit is in a non-conductive state,
The control circuit transitions to a desired operating state via a state in which both the high frequency path switch circuit and the high frequency shunt switch circuit are turned off when switching the operation of the high frequency path switch circuit and the high frequency shunt switch circuit. 2. The high frequency switch device according to claim 1, wherein the output timing of the control signal is settable so as to be able to be controlled.

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