JP2003069399A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that can prevent an excess through-current from being produced due to selection of a plurality of signal paths and decrease a delay in a selection signal so as to attain a high-speed circuit operation. SOLUTION: The semiconductor integrated circuit provided with a selector circuit 10 controlling pass transistors 11 to 14 provided to a plurality of signal paths PS1 to PS4 termination-coupled to one node n1 by selection signals A to D to selectively pass the selected signal, includes a detection circuit 40 that monitors the selection signals A to D so as to detect occurrence of a multi-hit state where two signal paths or more are closed and a selection signal revision circuit 30 that changes the selection signal so that all the signal paths are closed or only one signal path is opened on the basis of the result of detection.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for increasing the speed of a semiconductor integrated circuit, and more particularly to a technique useful when applied to a semiconductor integrated circuit including a selector circuit having a plurality of parallel pass transistors.

[0002]

2. Description of the Related Art There is a selector circuit using a pass transistor (transmission switch transistor) as a multi-input / single-output selector circuit capable of high-speed operation. In such a selector circuit, a plurality of selection signals for selecting a signal path must be in an asserted state and the rest in a negated state at any timing. This is because if there is a period in which a plurality of selection signals are asserted at the same time, a plurality of signal paths will be short-circuited in the selector circuit during that period, and a large through current will flow between them.

[0003]

In order to prevent the occurrence of the shoot-through current as described above, conventionally, when a plurality of selection signals among the selection signals become assert signals, all of them are negated signals on the control terminal side of the selector circuit. Or, it is common to provide a logic circuit (hereinafter, referred to as an exclusive logic circuit) that uses only one as an assert signal. This exclusive logic circuit is composed of a combinational circuit.

However, if there is such an exclusive logic circuit, the signal delay of the selection signal increases by that amount. Therefore, in the case of an integrated circuit in which the signal path of this selection signal is a critical path, There is a problem that the operation speed is reduced.

Further, as a method for preventing the generation of a through current,
On the output side of the circuit that generates the selection signal, hold the output of the selection signal during the period when the signal path of the selector circuit is valid,
In addition, there is also a method of providing a synchronous latch circuit such as a flip-flop that synchronizes a selection signal of a plurality of bits with each other during the transition period of the selector circuit and switches to the next one.

With such a configuration, unless the logic circuit for generating the selection signal behaves abnormally such as outputting a plurality of assert signals, a plurality of signal paths are short-circuited in the selector circuit. There is no such thing. Furthermore, such flip-flops are usually provided in required places on the signal path for pipeline operation of the integrated circuit and synchronization of each stage of the circuit, and a selection signal is generated for them. In many cases, there is no problem even if it is moved to the subsequent stage of the logic circuit. Therefore, in such a case, the delay of the signal path of the selection signal is shortened by the unnecessary delay of the exclusive logic circuit, which can contribute to the speedup of the circuit operation.

However, even when the synchronous latch circuit is provided as described above, the output of the latch circuit is not controlled, for example, when the power is turned on, so that a through current flows in the selector circuit during such a period. There is a problem called. Further, even during normal operation, there is a problem that a plurality of assert signals are output as selection signals from the logic circuit depending on the logic state of the circuit, and a through current flows through the selector circuit.

An object of the present invention is to prevent an excessive shoot-through current from being generated by selecting a plurality of signal paths, and to reduce the delay of the selection signal to speed up the circuit operation. Another object is to provide a semiconductor integrated circuit.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, a selection signal is monitored in a semiconductor integrated circuit including a selector circuit that selectively controls a switch transistor provided in each of a plurality of signal paths terminated to one node to selectively pass the signal. Detection means for detecting the occurrence of a multi-hit state in which two or more signal paths are opened, and a selection signal so that all signal paths are closed or only one signal path is opened based on the detection result. And selection signal changing means for changing.

According to such means, it is not necessary to add an exclusive logic circuit to the logic circuit for generating the selection signal, and in the integrated circuit in which the path of the selection signal is the critical path, the exclusive logic circuit As the delay disappears,
High-speed circuit operation. Further, since the signal path is closed even if a multi-hit state occurs, it is possible to prevent a shoot-through current from being generated in the selector circuit for a long period of time, and it is possible to reduce power consumption.

Desirably, the detection means is provided with a delay output means for performing a detection output when the multi-hit state is still detected after a predetermined time has elapsed from the detection of the multi-hit state.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of a preferred selector circuit to which the present invention is applied and peripheral circuits related to the selection signal. In the figure, 10 is a 4-input 1-output selector circuit in which the ends of four signal paths PS1 to PS4 are connected to one node n1, 20 is a logic circuit for generating a selection signal, and 30 is a multi-bit selection signal. A synchronous latch unit 40 having four flip-flops FF that respectively hold outputs and switch in synchronization, monitors a selection signal and detects a multi-hit state in which two or more signal paths of the selector circuit 10 are in an open state. It is a detection circuit.

The selector circuit 10 has four signal paths PS
1 to PS4 each is a pass transistor 1 including a P-channel type and an N-channel type transmission switch MOSFET.
1 to 14 are provided, and an output buffer 15 is provided in the output section.
Is provided. The output buffer 15 is of a self-latch type so that the floating state does not occur at the output node n1 even when all the signal paths PS1 to PS4 are closed.

The logic circuit 20 decodes, for example, n-bit input signals IN [0] to IN [n] to select the selection signal A0.
Generate ~ D0. Normal input signal IN [0] to IN
If [n], only one bit of the selection signals A to D becomes an assert signal, or all bits become negate signals, but when unexpected input signals IN [0] to IN [n] are input. In some cases, a plurality of selection signals A to D become assert signals.

2 and 3 show specific circuit examples of the detection circuit of FIG. The detection circuit 40 sets the detection output / M to the high level when the high-level assert signal of the 4-bit selection signals A to D is 1 bit or less, and when the high-level assert signal is 2 bits or more. Detection output /
This is a circuit for setting M to a low level. Specifically, as shown in FIG. 2, an AND circuit 42 that takes the logical sum of all combinations of two signals of the selection signals A to D, and any AND
N for detecting that the output of the circuit 42 has become high level
It is composed of an OR circuit 43 and a 3-input NAND circuit 44.

Further, as shown in FIG. 2, the detection circuit 40 is provided with a delay output circuit including inverters N1 and N2 and a NAND circuit 46 at its output portion. NA
The detection output M is directly input to one input terminal of the ND circuit 46, and is input to the other input terminal via the inverters N1 and N2. According to this delay output circuit, even if the detection circuit 40 detects a multi-hit state, the detection output / M is not immediately set to the low level,
When the multi-hit state is still detected after the delay of the inverters N1 and N2, the detection output / M is set to the low level. Therefore, even if the multi-hit state is erroneously detected due to a surge voltage or the like, the low-level detection output / M is not output to the flip-flop FF.

Further, as shown in FIG.
Is connected in series between the ground GND and the output node U1.
6 columns N-channel MOSFETs QA1 to QA in parallel
12 are connected, three in series between the power supply voltage and the output node U1, and four columns of P-channel MOSFETs QB1 to QB1 in parallel.
QB12 is connected, and each combination of two signals of the selection signals A to D is connected to an N-channel MOSFET of each column.
QA1 to QA12 are gate inputs, and each combination of three signals among selection signals A to D is a P channel MOS of each column.
It can also be configured as the gate input of the FETs QB1 to QB12. Then, a delay output circuit is provided in the output section as in the case of FIG.

FIG. 4 shows a circuit diagram of an example of the flip-flop circuit shown in FIG. The flip-flop FF has a function of temporarily latching the selection signals A0 to D0 output from the logic circuit 20 and outputting them in synchronization with the clock signal Φ.
The selection signal changing means for forcibly changing the output to the low level based on the detection output / M of the detection circuit 40 is included. Although not particularly limited, the flip-flop FF includes an input buffer 31, a slave latch 32,
Master latch 33, transfer MOSFETs 34 and 35 for passing and blocking signals between them, and
NA combining output buffer and selection signal changing means
It is composed of the ND circuit 36 and the like.

By the NAND circuit 36, the detection circuit 4
When the detection output / M of 0 is high level, the signal latched in the flip-flop FF is output in synchronization with the clock signal Φ, but when the detection output / M of the detection circuit 40 is low level, it is related to the latch signal. Output is fixed at low level.

The NAND circuit 3 has a configuration in which the selection signal changing means is removed from the flip-flop FF having the above configuration.
The circuit configuration is changed from 6 to an inverter buffer. Therefore, the length of the signal delay does not change between the flip-flop FF and the one obtained by removing the selection signal changing means.

According to the selector circuit 10 and the peripheral circuits related to the selection signals A to D as described above, the selector circuit 10 is activated when a plurality of the selection signals A to D are in an asserted state such as a high level. Is in a multi-hit state, the detection circuit 40 detects this state, and the detection output / M brings all the selection signals A to D into a negated state such as a low level. Therefore, even when a plurality of signal paths of the selector circuit 10 are opened when the power is turned on or due to incorrect input signals IN [0] to IN [n], the signal paths are immediately closed and a through current flows. It can be prevented.

Further, when the synchronous latch section 30 for switching the selection signals A to D in synchronism with each other is indispensable for the pipeline operation and the synchronous operation of the circuit, the selection signal A is selected.
The delay of the signal path for generating .about.D is shortened as compared with the case of inserting the conventional exclusive logic circuit, because the exclusive logic circuit is unnecessary. Therefore, in the case of a circuit in which this signal path becomes a critical path, it is possible to contribute to speeding up of circuit operation.

FIG. 5 is a block diagram showing a second embodiment of the selector circuit and its peripheral circuits. In this second embodiment, 4
This is an example in which a precharge amplifier 81 and a self-latch circuit 85 are used as a synchronous latch circuit which is a peripheral circuit of the selector circuit 60 having one input and one output.

The precharge type amplifier 81 includes N channel MOSFETs (hereinafter simply referred to as NMOS) Q4 and Q5 and P channel MOSFETs (hereinafter
Q6 and Q7 (referred to simply as PMOS), an NMOS Q1 that supplies a bias current by an enable signal AMPEN to activate an amplifier, and PMOSs Q2, Q3 and Q8 that precharge output terminals of both phases. Then, when the enable signal AMPEN is in the negated state, the outputs S and / S of both phases are precharged to a high level, and when the enable signal AMPEN is in the asserted state, one of the output signals S and / S is output according to the input signal A0. Changes to low level. The enable signal AMPEN changes in synchronization with the clock signal.

The self-latch circuit 85 includes an inverter N
5, N6 and MOS Q11 to Q14, a gate section composed of inverters N7 and N8, and a switch MOS Q16 functioning as selection signal converting means.
It is composed of Q17 and output buffers N9 and N10. When both the input signals S and / S are high level, the gate section is closed and its output node is in a floating state, and when either of the input signals S and / S becomes low level, the gate section is opened and the input signal is input to the latch section. A signal corresponding to S, / S is output.

With these configurations, the enable signals AMPEN of the precharge type amplifier 81 for 4 bits are simultaneously asserted, so that the outputs from the self-latch circuit 85 are simultaneously changed to the next selection signals. This selection signal is output and held until the enable signal AMPE is asserted.

The switch MOSs Q16 and Q17 are
The detection outputs M and / M from the detection circuit 90 forcibly apply high-level and low-level signals to the nodes of the latch section where the positive and negative phase signals are latched.

Further, the detection circuit 90 of FIG. 5 connects the power supply potential to the output node U2 when two or more of the negative-phase selection signals / A to / D are in the multi-hit state at the low level. PMOS QF1 to QF8 and an NMO that connects the ground potential to the output node U2 when three or more signals are at a high level and a multi-hit state does not occur.
SQG1 to G8 and buffers N30 to N
The negative phase selection signals / A to / D are input via 33 to detect the multi-hit state. In addition, the output section has an NA
A delay output circuit including an ND circuit 46 and inverters N21 to N24 is provided.

FIG. 6 shows a circuit diagram of another example of the self-latch portion of FIG. The self-latch portion 85 can be changed as shown in FIG. That is, the latch unit is composed of two NAND circuits G1 and G2, and one NAN
The detection output / M of the detection circuit 90 is input to the D circuit G2.
As a result, when the detection output / M is at the high level, the latch signal is changed according to the signal from the previous stage, but when the detection signal / M becomes the low level in the multi-hit state, the latch signal is forcibly fixed.

Even with the circuit configuration of the second embodiment,
The same effects as the selector circuit of the first embodiment and the peripheral circuits related to the selection signal thereof can be obtained.

FIG. 7 is a block diagram showing a semiconductor integrated circuit provided with the selector circuit of the present invention. The above-mentioned selector circuit and the peripheral circuits related to the selection signal are effective when applied to the semiconductor integrated circuit 100 of FIG. 7 which requires high-speed operation. The semiconductor integrated circuit 100 is a one-chip microcomputer equipped with a DSP (Digital Signal Processor) capable of processing real-time signals such as multimedia data.

In FIG. 7, 110 is a core part of a one-chip microcomputer, 111 is a central processing unit, 112 is a 32-bit × 32-bit multiplier, 113 is a programmable processing content by software, and signal processing is performed in real time. A DSP unit 114 for performing the above; 114 is an XY-RAM (Random Access Memory) macro connected through a processor bus L1, an X bus Lx, and a Y bus Ly;
Reference numeral 115 is a memory controller that manages the memory of the XY-RAM macro 114, 116 is a cache memory controller (CCN) that performs cache control, 117 is a TLB (address translation buffer) that stores the address translation data of the memory by a high-speed memory, 118 is a cache memory macro, 119 is a relatively slow and large capacity DRAM (Dynamic RAM) macro, and 120 is this DRA.
It is an M macro memory controller.

Further, 121 is a bus state controller (BSC) for controlling the first peripheral bus L2, the second peripheral bus L3 and the external bus L4, and 122 is a DM for directly accessing the DRAM macro 119 or the like from the peripheral module.
AC (Direct Memory Access Controller), 123 is P
Clock pulse generator with built-in LL circuit (CP
G), 124 is an interrupt controller (INTC) for controlling interrupts from peripheral modules and the outside, 130, 1
A peripheral module 31 has, for example, a serial interface for exchanging data with the outside and other external interfaces.

Then, the semiconductor integrated circuit 100 having such a configuration is connected to the external memory 200 and the AS via the external bus L4.
IC (Application Specific Integrated Circuit) 2
10 and the like are connected.

In such a semiconductor integrated circuit 100, the selector circuit and its peripheral circuits shown in FIGS. 1 and 5 are the TLB macro 117 and the cache macro 118.
It is provided in. Specifically, in a multi-way cache structure in which a plurality of address arrays and data arrays are provided, data input / output from each way is selected for a predetermined way, or a cache hit and a miss hit occur. The above selector circuit is used to switch the path of input / output data depending on the case.

As described above, the TLB which is required to operate at high speed
As a result of simulation comparison between the case where the selector of FIG. 5 is applied to the selector of the macro 117 or the cache macro 118 and the case where the conventional exclusive logic circuit is inserted, as a result, the condition of the speed worst of the device, the temperature of 125 ° C., the power supply voltage of 1 At .26 V and operating frequency of 266 MHz,
It is expected that the operating speed of one cycle will be 0.4 ns faster. This is a speedup of 10% or more for one cycle of 3.75 ns.

Further, if a multi-hit state occurs every cycle, a simulation test is performed to find out how much through current flows. As a result, the device power worst condition, temperature −40 ° C., power supply voltage 1.632 V, operation It has been found that at a frequency of 266 MHz, the current increases by about 0.5 mA and does not reach the level of destroying the LSI.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the output buffer (15) of the selector circuit may or may not be present, and the configurations of the synchronous latch circuit and the detection circuit may have various modifications other than those shown in the embodiments.

In the above description, the invention made by the present inventor was mainly described as a one-chip microcomputer which is a field of application which is the background of the invention. However, the present invention is not limited to this, and a selector circuit is provided and a high-speed operation is performed. It can be widely used in semiconductor integrated circuits that require operations.

[0040]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, it is possible to prevent the selector circuit from mistakenly short-circuiting a plurality of signal paths to cause an excessive shoot-through current and to insert an exclusive logic circuit in the path of the selection signal. The signal delay of the selection signal can be shortened as compared with the circuit of FIG. Therefore, in the case of a circuit in which the signal path of the selection signal becomes a critical path, there is an effect that it can contribute to speeding up of the circuit operation.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a preferred selector circuit to which the present invention is applied and peripheral circuits related to a selection signal thereof.

FIG. 2 is a circuit diagram showing a first example of the detection circuit of FIG.

FIG. 3 is a circuit diagram showing a second example of the detection circuit of FIG.

FIG. 4 is a circuit diagram showing an example of a flip-flop circuit in FIG.

FIG. 5 is a configuration diagram showing a second embodiment of a selector circuit and its peripheral circuits.

FIG. 6 is a circuit diagram showing another example of the self-latch unit.

FIG. 7 is a block diagram showing a semiconductor integrated circuit provided with a selector circuit of the present invention.

[Explanation of symbols]

10 Selector Circuits 11 to 14 Pass Transistor 20 Logic Circuit 30 Synchronous Latch Unit 36 NAND Circuit (Selection Signal Changing Means) 40 Detection Circuit 46 NAND Circuit (Delay Output Means) N1, N2 Inverter (Delay Output Means) FF Flip-Flop 81 Pre Charge amplifier 85 Self-latch circuit 90 Detection circuit Q16, Q17 Switch MOS (selection signal changing means) 100 One-chip microcomputer 117 TLB macro 118 Cache macro

Continued front page    (72) Inventor Noriaki Maeda             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Kiyoshi Fujimoto             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F term (reference) 5J055 AX02 AX27 BX03 CX00 DX01                       EY21 EZ07 EZ12 EZ13 EZ25                       EZ31 EZ39 GX01

Claims (5)

[Claims] 1. A semiconductor integrated circuit having a selector circuit which selectively passes a signal by controlling a switch transistor provided in each of a plurality of signal paths terminated to one node by a selection signal, Detection means for detecting the occurrence of a multi-hit state in which two or more signal paths are opened by monitoring the selection signal, and all signal paths are closed or only one signal path is detected based on the detection result of the detection means. A semiconductor integrated circuit comprising: a selection signal changing means for changing the selection signal so as to be in an open state. 2. The detection means includes a delay output means which does not perform detection output immediately after the detection of the multi-hit state, but performs detection output when the multi-hit state continues to be detected after a predetermined delay. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is provided. 3. The selection signal changing means inputs the detection output of the detection circuit, and when the detection signal indicates the occurrence of the multi-hit state, a high level or a low level is applied to the signal line of the selection signal. The semiconductor integrated circuit according to claim 1, further comprising a switch transistor for connecting a potential. 4. A synchronous latch circuit is provided on the output side of the logic circuit for generating the selection signal of the selector circuit, which outputs and holds the selection signal of a plurality of bits for a predetermined period and changes the selection signal in synchronization. 4. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a semiconductor integrated circuit. 5. The semiconductor integrated circuit according to claim 1, wherein a signal path of the selection signal is provided in a critical path of the integrated circuit.