CN101770981A - Zero drift compensation method of Hall magnetic sensor - Google Patents
Zero drift compensation method of Hall magnetic sensor Download PDFInfo
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- CN101770981A CN101770981A CN200810209819A CN200810209819A CN101770981A CN 101770981 A CN101770981 A CN 101770981A CN 200810209819 A CN200810209819 A CN 200810209819A CN 200810209819 A CN200810209819 A CN 200810209819A CN 101770981 A CN101770981 A CN 101770981A
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Abstract
The invention provides a zero drift compensation method of a Hall magnetic sensor. At present, the existing Hall magnetic sensor has the defects that the output voltage VH of the Hall magnetic sensor is not equal to zero, and the zero error VHO is generated because of factors such as unsymmetrical geometric positions of Hall electrodes, poor ohmic contact of the electrodes, nonuniform electric resistivity, nonuniform temperature and the like when the external magnetic filed B is equal to zero. In order to eliminate the zero error, the invention mainly adopts an external compensation circuit for compensating the zero drift. When the method is used, the magnetic sensor is difficult to develop in the directions of miniaturization and intelligentization. The invention uses a CMOS process for manufacturing grooves of the MOSFET Hall magnetic sensor so that the resistance values of four equivalent resistors are changed along with the external grid voltage. The invention is applicable to the fields of medicine, automobiles and the like.
Description
Technical field:
The present invention relates to a kind ofly adjust MOSFET Hall Magnetic Sensor conducting channel equivalent resistance, MOSFET Hall Magnetic Sensor is carried out the zero compensation method by gate bias voltage.
Background technology:
At present, known Hall Magnetic Sensor is adding magnetic field B=0 o'clock, because the Hall electrode geometric position is asymmetric, factors such as the electrode ohmic contact is bad, resistivity is inhomogeneous, non-uniform temperature make hall output voltage VH be not equal to zero, produces electrical error of null position VHO.For eliminating electrical error of null position, main employing adds compensating circuit zero drift is compensated, and this kind method is not easy to Magnetic Sensor to miniaturization, intelligent direction development.
Summary of the invention:
The purpose of this invention is to provide a kind of method that methods such as adding compensating circuit compensates the null offset of MOSFET Hall Magnetic Sensor performance impact that overcomes.
Above-mentioned purpose realizes by following technical scheme:
The method that Hall magnetic sensor null offset compensates, four equivalent resistance resistances of raceway groove of making MOSFET Hall Hall magnetic sensor by CMOS technology change with adding grid voltage.
The method that Hall magnetic sensor null offset compensates: described CMOS technology comprises flushing, oxidation for the first time, photoetching for the first time, oxidation for the second time, makes the doping of P type, oxidation for the third time, two-five photoetching;
Described flushing is to be that N type twin polishing high resistant (ρ＞100 Ω cm) monocrystalline silicon piece of 450 μ m boils to emitting white cigarette with the concentrated sulfuric acid with thickness, the a large amount of deionized water rinsings in cooling back, adopt electronics cleaning fluid DZ-1, DZ-2 respectively to clean again respectively twice, use a large amount of deionized water rinsings, put into drier and dry;
The described oxidation first time is that cleaned monocrystalline silicon piece is put into the high-temperature oxydation stove, adopts thermal oxidation technology growth SiO
2Layer, 1180 ℃ of oxidation furnace temperature, growth SiO
2Layer thickness 650nm;
The described photoetching first time is to adopt mask aligner to carry out photoetching, and photolithography process is gluing, preceding baking, exposure, development, post bake, corrode and remove photoresist, and makes the active area window by lithography, adopts above-mentioned silicon wafer cleaning method cleaning silicon chip;
The described oxidation second time is that cleaning back silicon chip is adopted thermal oxidation technology growth SiO
2Layer is at the regrow SiO of thickness 50nm of the active area window of a photoetching
2Layer;
Making the doping of P type is to adopt ion implantor to inject the B ion, and the injection energy is 40KeV, and implantation dosage is 6.0 * 10
13, obtain the P type and mix; Adopt wet etching to remove the SiO of thickness 50nm
2Layer;
Described oxidation for the third time is to adopt above-mentioned cleaning method to clean this silicon chip, carries out three oxidations, growth grid oxic horizon, thickness 50nm; Adopt LPCVD growing polycrystalline silicon grid and carry out the polysilicon gate phosphorous diffusion;
The described photoetching second time is to adopt above-mentioned photoetching method to carry out photoetching, and etch polysilicon forms polysilicon gate and carries out the boron injection, by the polysilicon gate self-aligned technology, realizes MOSFET source electrode, drain electrode and two Hall output doping impurity;
Described photoetching for the third time is to carry out photoetching by above-mentioned photoetching method, makes substrate impurity doping window by lithography;
Adopt ion implantor to carry out phosphorus and inject, substrate forms N
+Pass through H
2+ O
2Synthetic oxidizing process is carried out the polysilicon gate oxidation, growth SiO
2Layer thickness 200nm;
Described the 4th photoetching is etching MOSFET Hall Magnetic Sensor source electrode, drain electrode, grid, substrate and Hall output contact hole; Silicon chip front magnetron sputtering aluminium electrode, aluminium thickness of electrode 1 μ m;
Described the 5th photoetching is to anti-carve aluminium, forms source electrode, drain electrode, substrate, grid and two Hall output terminal electrodes respectively; Silicon chip is put into vacuum high temperature furnace, carry out Alloying Treatment at 400 ℃, time 30min makes source electrode, drain electrode, substrate, Hall output etc. form good Ohmic contact.
The method that described Hall magnetic sensor null offset compensates can adopt P type silicon substrate to make n-MOSFET Hall Magnetic Sensor, also can adopt N type silicon substrate to make p-MOSFET Hall Magnetic Sensor.
The method that described Hall magnetic sensor null offset compensates, the Hall output of two ohmic contact is not positioned at the raceway groove middle position in polysilicon gate up stroke concavity structure.
This technical scheme has following beneficial effect:
1. the present invention realizes when externally-applied magnetic field equals zero, and changes with adding grid voltage MOSFET Hall Magnetic Sensor raceway groove equivalent electric circuit bridge circuit output voltage, under certain grid voltage, realizes MOSFET Hall Magnetic Sensor drift compensating.
2. the object of the invention overcomes methods such as adding compensating circuit to MOSFET Hall Magnetic Sensor performance impact.
3. the present invention is by adopting MOSFET Hall Magnetic Sensor gate bias voltage V
GSAdjust the method that the conducting channel equivalent resistance makes the brachium pontis symmetry, when making externally-applied magnetic field B=0, Magnetic Sensor is equipotential electromotive force V not
HONear zero-bit output, realize the intellectuality of MOSFET Hall Magnetic Sensor zero compensation.
Description of drawings:
Accompanying drawing 1 is a MOSFET Hall Magnetic Sensor mask lithography domain among the present invention.Provide MOSFET Hall Magnetic Sensor source electrode (S), drain electrode (D), grid (G), substrate (B) and Hall output VH1, VH2 among the figure respectively.
Accompanying drawing 2 is MOSFET Hall Magnetic Sensor raceway groove equivalent circuit diagrams among the present invention.
The specific embodiment of the present invention:
Embodiment 1:
The method that Hall magnetic sensor null offset compensates, four equivalent resistance resistances of raceway groove of making MOSFET Hall Hall magnetic sensor by CMOS technology change with adding grid voltage.
Described CMOS technology comprises flushing, oxidation for the first time, photoetching for the first time, oxidation for the second time, makes the doping of P type, oxidation for the third time, time photoetching of two First Five-Year Plans.
Referring to accompanying drawing 1, thickness is N type twin polishing high resistant (ρ＞100 Ω cm) monocrystalline silicon piece of 450 μ m, boil to emitting white cigarette with the concentrated sulfuric acid, the a large amount of deionized water rinsings in cooling back, adopt cleaning fluid DZ-1, DZ-2 respectively to clean again respectively twice, use a large amount of deionized water rinsings, put into drier and dry;
Cleaned monocrystalline silicon piece is put into the high-temperature oxydation stove carry out once oxidation, adopt thermal oxidation technology growth SiO2 layer, 1180 ℃ of oxidation furnace temperature, growth SiO2 layer thickness 650nm;
Adopt mask aligner to carry out a photoetching, photolithography process is gluing, preceding baking, exposure, development, post bake, corrode and remove photoresist, and makes the active area window by lithography, adopts above-mentioned silicon wafer cleaning method cleaning silicon chip;
To clean the back silicon chip and carry out secondary oxidation, adopt thermal oxidation technology growth SiO2 layer, at the regrow SiO2 layer of thickness 50nm of the active area window of a photoetching, to improve ion implantation uniformity;
Adopt ion implantor to inject the B ion, the injection energy is 40KeV, and implantation dosage is 6.0 * 1013, obtains the P type and mixes;
Adopt wet etching to remove the SiO2 layer of thickness 50nm;
Adopt above-mentioned cleaning method to clean this silicon chip, carry out three oxidations again, growth grid oxic horizon, thickness 50nm;
Adopt LPCVD growing polycrystalline silicon grid and carry out the polysilicon gate phosphorous diffusion, to reduce polysilicon gate resistivity;
Adopt above-mentioned photoetching method to carry out the secondary photoetching, etch polysilicon forms polysilicon gate and carries out the boron injection, by the polysilicon gate self-aligned technology, realizes MOSFET source electrode, drain electrode and two Hall output doping impurity;
Carry out third photo etching by above-mentioned photoetching method, make substrate impurity doping window by lithography;
Adopt ion implantor to carry out phosphorus and inject, substrate forms N+; Carry out the polysilicon gate oxidation by the synthetic oxidizing process of H2+O2, growth SiO2 layer thickness 200nm realizes the more polysilicon gate protection;
By four photoetching, etching MOSFET Hall Magnetic Sensor source electrode, drain electrode, grid, substrate and Hall output contact hole;
Silicon chip front magnetron sputtering aluminium electrode, aluminium thickness of electrode 1 μ m;
Five photoetching anti-carve aluminium, form source electrode, drain electrode, substrate, grid and two Hall output terminal electrodes respectively;
Silicon chip is put into vacuum high temperature furnace, carry out Alloying Treatment at 400 ℃, time 30min makes source electrode, drain electrode, substrate, Hall output etc. form good Ohmic contact.
Adopt P type silicon substrate to make n-MOSFET Hall Magnetic Sensor, perhaps adopt N type silicon substrate to make p-MOSFET Hall Magnetic Sensor.
The Hall output of two ohmic contact is not positioned at the raceway groove middle position in polysilicon gate up stroke concavity structure.
Operation principle:
Be four resistance R 1, R2, R3 and R4 with the raceway groove equivalence between MOSFET Hall Magnetic Sensor source electrode (S), drain electrode (D) and four electrodes of Hall output VH1, VH2.R1, R2, R3 and R4 change with adding grid voltage, cause the bridge circuit output voltage to be adjusted.
Claims (6)
1. method that Hall magnetic sensor null offset compensates is characterized in that: four equivalent resistance resistances of raceway groove of making MOSFET Hall Hall magnetic sensor by CMOS technology change with adding grid voltage.
2. the method that Hall magnetic sensor null offset according to claim 1 compensates is characterized in that: described CMOS technology comprises flushing, oxidation for the first time, photoetching for the first time, oxidation for the second time, makes the doping of P type, oxidation for the third time, two-five photoetching.
3. the method that Hall magnetic sensor null offset according to claim 1 compensates, it is characterized in that: described flushing is to be that N type twin polishing high resistant p＞100 Ω cm monocrystalline silicon pieces of 450 μ m boil to emitting white cigarette with the concentrated sulfuric acid with thickness, the a large amount of deionized water rinsings in cooling back, adopt electronics cleaning fluid DZ-1, DZ-2 respectively to clean again respectively twice, use a large amount of deionized water rinsings, put into drier and dry;
The described oxidation first time is that cleaned monocrystalline silicon piece is put into the high-temperature oxydation stove, adopts thermal oxidation technology growth SiO
2Layer, 1180 ℃ of oxidation furnace temperature, growth SiO
2Layer thickness 650nm;
The described photoetching first time is to adopt mask aligner to carry out photoetching, and photolithography process is gluing, preceding baking, exposure, development, post bake, corrode and remove photoresist, and makes the active area window by lithography, adopts above-mentioned silicon wafer cleaning method cleaning silicon chip;
The described oxidation second time is that cleaning back silicon chip is adopted thermal oxidation technology growth SiO
2Layer is at the regrow SiO of thickness 50nm of the active area window of a photoetching
2Layer;
Making the doping of P type is to adopt ion implantor to inject the B ion, and the injection energy is 40KeV, and implantation dosage is 6.0 * 10
13, obtain the P type and mix; Adopt wet etching to remove the SiO of thickness 50nm
2Layer;
Described oxidation for the third time is to adopt above-mentioned cleaning method to clean this silicon chip, carries out three oxidations, growth grid oxic horizon, thickness 50nm; Adopt LPCVD growing polycrystalline silicon grid and carry out the polysilicon gate phosphorous diffusion;
The described photoetching second time is to adopt above-mentioned photoetching method to carry out photoetching, and etch polysilicon forms polysilicon gate and carries out the boron injection, by the polysilicon gate self-aligned technology, realizes MOSFET source electrode, drain electrode and two Hall output doping impurity;
Described photoetching for the third time is to carry out photoetching by above-mentioned photoetching method, makes substrate impurity doping window by lithography;
Adopt ion implantor to carry out phosphorus and inject, substrate forms N
+Pass through H
2+ O
2Synthetic oxidizing process is carried out the polysilicon gate oxidation, growth SiO
2Layer thickness 200nm;
Described the 4th photoetching is etching MOSFET Hall Magnetic Sensor source electrode, drain electrode, grid, substrate and Hall output contact hole; Silicon chip front magnetron sputtering aluminium electrode, aluminium thickness of electrode 1 μ m;
Described the 5th photoetching is to anti-carve aluminium, forms source electrode, drain electrode, substrate, grid and two Hall output terminal electrodes respectively; Silicon chip is put into vacuum high temperature furnace, carry out Alloying Treatment at 400 ℃, time 30min makes source electrode, drain electrode, substrate, Hall output etc. form good Ohmic contact.
4. the method that Hall magnetic sensor null offset according to claim 1 and 2 compensates is characterized in that: adopt P type silicon substrate to make n-MOSFET Hall Magnetic Sensor, perhaps adopt N type silicon substrate to make p-MOSFET Hall Magnetic Sensor.
5. the method that Hall magnetic sensor null offset according to claim 1 and 2 compensates is characterized in that: the Hall output of two ohmic contact is not positioned at the raceway groove middle position in polysilicon gate up stroke concavity structure.
6. the method that Hall magnetic sensor null offset according to claim 4 compensates is characterized in that: the Hall output of two ohmic contact is not positioned at the raceway groove middle position in polysilicon gate up stroke concavity structure.
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|---|---|---|---|
| CN200810209819A CN101770981A (en) | 2008-12-29 | 2008-12-29 | Zero drift compensation method of Hall magnetic sensor |
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|---|---|---|---|
| CN200810209819A CN101770981A (en) | 2008-12-29 | 2008-12-29 | Zero drift compensation method of Hall magnetic sensor |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102243126A (en) * | 2011-04-14 | 2011-11-16 | 黑龙江大学 | Nano silicon thin film transistor pressure sensor |
| CN102445671A (en) * | 2010-10-13 | 2012-05-09 | 北京中科信电子装备有限公司 | Hall device error compensation circuit |
| CN102636761A (en) * | 2011-02-08 | 2012-08-15 | 英飞凌科技股份有限公司 | Low offset spinning current hall plate and method to operate it |
| CN103874929A (en) * | 2011-10-10 | 2014-06-18 | ams有限公司 | Hall sensor |
| US8896303B2 (en) | 2011-02-08 | 2014-11-25 | Infineon Technologies Ag | Low offset vertical Hall device and current spinning method |
| CN108987392A (en) * | 2018-08-14 | 2018-12-11 | 黑龙江大学 | A kind of composite magnetic field sensor and its manufacture craft |
-
2008
- 2008-12-29 CN CN200810209819A patent/CN101770981A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102445671B (en) * | 2010-10-13 | 2015-12-16 | 北京中科信电子装备有限公司 | A kind of Hall device error compensation circuit |
| CN102445671A (en) * | 2010-10-13 | 2012-05-09 | 北京中科信电子装备有限公司 | Hall device error compensation circuit |
| US9261572B2 (en) | 2011-02-08 | 2016-02-16 | Infineon Technologies Ag | Low offset spinning current hall plate and method to operate it |
| US8829900B2 (en) | 2011-02-08 | 2014-09-09 | Infineon Technologies Ag | Low offset spinning current hall plate and method to operate it |
| CN102636761B (en) * | 2011-02-08 | 2014-10-22 | 英飞凌科技股份有限公司 | Low offset spinning current hall plate and method to operate it |
| US8896303B2 (en) | 2011-02-08 | 2014-11-25 | Infineon Technologies Ag | Low offset vertical Hall device and current spinning method |
| US9116196B2 (en) | 2011-02-08 | 2015-08-25 | Infineon Technologies Ag | Low offset vertical hall device and current spinning method |
| CN102636761A (en) * | 2011-02-08 | 2012-08-15 | 英飞凌科技股份有限公司 | Low offset spinning current hall plate and method to operate it |
| US9423471B2 (en) | 2011-02-08 | 2016-08-23 | Infineon Technologies Ag | Low offset vertical hall device and current spinning method |
| CN102243126A (en) * | 2011-04-14 | 2011-11-16 | 黑龙江大学 | Nano silicon thin film transistor pressure sensor |
| CN103874929A (en) * | 2011-10-10 | 2014-06-18 | ams有限公司 | Hall sensor |
| CN103874929B (en) * | 2011-10-10 | 2016-08-17 | ams有限公司 | Hall element |
| US9575141B2 (en) | 2011-10-10 | 2017-02-21 | Ams Ag | Hall sensor with hall sensor elements that respectively comprise element terminals and are interconnected in a circuit lattice |
| CN108987392A (en) * | 2018-08-14 | 2018-12-11 | 黑龙江大学 | A kind of composite magnetic field sensor and its manufacture craft |
| CN108987392B (en) * | 2018-08-14 | 2024-01-02 | 黑龙江大学 | Composite magnetic field sensor and manufacturing process thereof |
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Application publication date: 20100707 |