CN101764795B - Link layer controller of IEEE1394 bus - Google Patents
Link layer controller of IEEE1394 bus Download PDFInfo
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Abstract
The invention relates to a link layer controller of an IEEE1394 bus, which comprises a host computer interface, a link layer core module, a data buffering and routing control module, a high-speed data interface module and a configuration register, wherein an external CPU (central processing unit) can read and write data buffering areas in the configuration register and the access data buffering and routing control module by the host computer interface; the data buffering and routing control module is positioned among the link layer core module and the host computer interface and a high-speed data interface, used for providing the switching control among different data receiving and sending channels and also provided with two asynchronous first-in first-out memories which are respectively used for the buffering of receiving and sending data and the synchronization of cross-clock domain data; and the configuration register is used for providing initial configuration and control for the link layer core module and the data buffering and routing control module and controlling and acquiring the working states of all modules of the link layer controller by the host computer interface reading and writing configuration register, and has good portability.
Description
Technical field
The present invention relates to the computer standard universal serial bus---the design of IEEE1394 bus protocol controller, particularly a kind of link layer controller that is applied to the IEEE1394 bus of space electronic technical field.
Background technology
In electronic system, in order to simplify hardware circuit design, optimization system structure, one group of circuit commonly used is configured to suitable interface circuit, is connected with ancillary equipment with each parts, and the shared connection line of this group is called bus.Adopt bus structures to be convenient to the expansion of parts and equipment, especially formulated unified bus standard, make more easily and realize interconnection between distinct device.Advanced bussing technique has crucial influence for the performance that improves electronic system.
On the spacecraft in early days; Do not use bus structures; Computer and each equipment, and the communication between each equipment does not have unified standard all by user oneself definition; Connection between each electronic device unit often needs a large amount of cables, and the direct result that causes like this is that wiring is complicated, the volume of cable is big, Heavy Weight, power consumption is high and communication efficiency is low.And, owing to do not adopt unified interface standard, also can bring a lot of other difficulties and inconvenient, be difficult to expand like equipment, equipment of every increase, all with it the software and hardware of relevant device all to change; Moreover owing to do not seek unity of standard, it is very difficult that the test of equipment becomes, and can't adopt unified testing equipment and method of testing, is not easy to carry out the test of equipment, and the hardware and software cost of test is also very high; Also be not easy to the maintenance and the upgrading of system in addition.
Along with development of electronic technology; The performance of spacecraft is increasingly high; System becomes and becomes increasingly complex, and is also increasingly high to the requirement of data communication, for the ease of carrying out modularization, standardized design and management; On satellite and airship, use standard bus structure to come building network, become the inevitable requirement and the development trend of spaceborne electronic system.
Since the nineties in 20th century, MIL-STD-1553B, CAN bussing technique progressively are applied to the electronic system of spacecraft, but the speed of these buses is all lower, and for example the flank speed of 1553B is 1Mbps.Along with the development of aerospace electron technology, the various space flight buses of using at present can not satisfy the requirement that spacecraft improves day by day, and therefore, exploitation space flight data/address bus at a high speed is imminent.
The IEEE1394 bus is a kind of commercial bus, is proposed by Apple company at first, and purpose is for the real-time digital transfer of data provides a high-speed interface, is mainly used in various digital multimedia devices.The IEEE1394 bus is as a kind of commercial bus of maturation; Because the multiple advantage of himself; A lot of in the world countries have all given to show great attention to the SPACE APPLICATION of IEEE1394 bus, and the high speed data bus of IEEE1394 bus as its following satellite platform all selected by a lot of spatial organizations.
The IEEE1394 bus protocol can be divided into three layers: physical layer, link layer and transaction layer.Generally, physical layer and link layer are accomplished by hardware, and transaction layer is mainly realized by software.Therefore; The IEEE1394 bus is applied to space flight; Just must select high-grade IEEE1394 bus protocol control chip; To adapt to abominable space environment, still owing to receive the west in technology and the product blockade of space flight high-tech area to China, the IEEE1394 bus device that satisfies the space flight requirement is difficult to obtain.
Summary of the invention
The object of the present invention is to provide a kind of IEEE1394 bus links layer controller, can or be used for the ASIC flow through the FPGA realization with better portability.Use high-grade FPGA device to realize, or after having the ASIC flow of anti-irradiation technique, this controller can be used for avionics equipment, the aerospace level device that solves the IEEE1394 bus is difficult for obtaining problem.
For realizing the foregoing invention purpose; A kind of IEEE1394 bus links layer controller provided by the present invention; It is characterized in that described link layer controller comprises: HPI, link layer nucleus module, data buffering and routing module control, high speed interface and configuration register; Outside CPU can read and write configuration register, the data buffering area is carried out accessing operation through described HPI; Described data buffering and routing module control are between HPI, high speed interface and the link layer nucleus module; Provide different transceive data interchannel switching controls; Use two asynchronous first-in/first-out memory FIFO (First InFirst Out) in said data buffering and the routing module control, be respectively applied for the buffering and the cross clock domain synchronization of data of transceive data; Described configuration register links to each other with routing module control, high speed interface with link layer nucleus module, data buffering respectively with condition line through control line; Be used to provide initial configuration and control and obtaining to each module operating state of link layer controller to link layer controller;
Described link layer nucleus module is used for realizing comprising all functions of IEEE1394 bus protocol link layer: physical layer link layer interface, data buffering processing unit, data packet transceive unit, cyclic redundancy CRC check unit and cycle controller;
Described physical layer link layer interface is used to provide the standard interface between link layer and physical chip;
Described data buffering processing unit, the transfer of data that is used between data packet transceive module and the physical layer link layer interface provides the data buffering function;
Described data packet transceive unit is the core of link layer nucleus module, links to each other with routing module control with data buffering processing unit, cyclic-redundancy-check unit, cycle controller and data buffering through bidirectional data line;
Said cyclic redundancy (CRC) verification unit, the CRC check function when being used to transceive data is provided;
Said cycle controller; Comprise: cycle timer and cycle monitor; Service when being used for waiting, cycle timer is one 32 a timer, is used to produce the timing signal of 125us and time of each node synchronously; Cycle monitor is used for keeping watch on cycle timer, and can produce circulation and begin bag and corresponding bus application;
When sending data; Said data packet transceive unit according to the protocol requirement of IEEE1394 to sent packet carry out framing, CRC check, according to different type of data packet through physical layer after bus is sent bus application signal, is obtained bus, transmit packet through the physical layer link layer interface to universal serial bus; Receive to send behind the non-Broadcasting-Asynchronous bag and confirm bag, also can produce and send circulation and begin to wrap bus if this node is a cycle controller;
When receiving data; Said data packet transceive unit can receive physical layer and transmit; From the packet of universal serial bus, analysis, address decoding and the CRC check of the line data bag of going forward side by side are if the packet rs destination node that on universal serial bus after the decoding, transmits is that this node and CRC check are correct; Then receive this packet, and send to data buffering and routing module control after data are recombinated as requested.
Described HPI provides a kind of 16 general bit CPU interfaces, links to each other with configuration register, data buffering and routing module control with some control lines through 16 BDB Bi-directional Data Bus; The sequential of said HPI is accomplished under its clock signal that provides control by outer CPU; HPI is to the read-write of configuration register; And the clock synchronization that the read-write of data bufferings and routing module control is all provided with CPU, the frequency maximum of this clock signal can reach 50Mhz.
In addition; In order to satisfy the needs of a large amount of high speed data transfer; The link layer controller of said IEEE1394 bus also comprises a special high speed interface; This high speed interface links to each other with configuration register with routing module control with data buffering, is used to provide link layer controller directly outside high-speed memory directly to be carried out the interface of access; Said high speed interface is 16 to the data width of external memory storage, is 32 to the data width of inside, and work clock is produced by the clock division of link layer nucleus module clock internal control circuit according to the physical layer input.
Described high-speed memory comprises: high speed FIFO and dual port RAM have solved when transmitting when waiting the bottleneck problem of a large amount of high speed data transfer.
Described data buffering and routing module control comprise: asynchronous transmission FIFO, general reception FIFO and data routing unit;
Described asynchronous transmission FIFO is between HPI and the data routing module control, is an asynchronous FIFO that sends asynchronous data packets, is used to send the data buffering and the different clock-domains synchronization of data of asynchronous data packets; HPI writes packet to be sent to asynchronous transmission FIFO under host clock control, data buffering and routing module control be sense data under internal clocking control, and the degree of depth of asynchronous transmission FIFO is 512, and data width is 32;
Described general reception FIFO is one and can receives all types packet between HPI and data routing unit, the degree of depth 512, and the asynchronous FIFO that width is 32, its function is similar with asynchronous transmission FIFO, but data direction is opposite;
Said data routing unit is used for route control, and the data-bus width of input and output is all 32, and the one of which end links to each other with the link layer nucleus module, and the other end receives FIFO with transmission and high speed interface links to each other; When receiving data, the data routing unit is according to the control bit of configuration register, and control data outputs to general reception FIFO or high speed interface; When sending data, output to the link layer nucleus module according to control corresponding position reading of data from send FIFO or high speed interface.
Described configuration register comprises some 32 registers group, and this registers group is used to the control to link layer controller is provided, and the operating state that link layer controller is provided.
Described cycle timer is one 32 a timer, all compatible IEEE1394 bus protocol of its function and form.
The definition of the signal of described physical layer link layer interface and sequential relationship meet the IEEE1394 bus protocol; The signal that uses comprises: 7 bidirectional data line D; Two two-way control line Ctl, link layer request signal Lreq, link layer power state signal LPS; Link layer start signal LinkOn, the clock signal Sclk of 50Mhz; Wherein, the clock Sclk of 50Mhz is the element task clock of link layer controller, and except that the read-write of HPI and configuration register, other all modules all are operated in this clock or are under the clock control that derives of basis with this clock.
Described physical layer link layer interface has adopted fault-tolerant design, is used for analyzing and handling to the various mistakes that control signal Ctl possibly occur.Avoided physical layer in the link layer control signals transmitted, the gross error that probable bit error causes to occur like this.
Described link layer controller uses the VerilogHDL language description to realize, adopts the sequential logic design, and each module all is synchronized to the corresponding work clock.
When sending packet, the packet that writes specified format through HPI or high speed interface is to data buffering and routing module control; Asynchronous FIFO through data buffering and routing module control is realized the control of buffering, multi-clock zone synchronization of data and the data route of data, gets into the link layer core then; In the link layer core; Carry out the framing of data according to the form of different types of data bag in the IEEE1394 agreement; And CRC check; Through the physical layer link layer interface to the bus arbitration application that universal serial bus sends respective type, obtain the control of bus after, begin through transmitting packet to universal serial bus according to the speed (100Mpbs, 200Mpbs or 400Mpbs) of appointment with the interface of physical layer; After sending ED,, then wait for the affirmation bag that destination node is returned if transmission is non-Broadcasting-Asynchronous bag.
When receiving packet; Be received in data packets for transmission on the universal serial bus through the physical layer link layer interface; At the link layer nucleus module packet that receives is carried out the decoding of address and type of data packet, if the destination node of this packet is not this node, the then reception of forgo data bag; Otherwise begin to receive packet and carry out CRC check (like the then reception of forgo data bag of check errors); Output to data buffering and routing module control to the data that receive according to the form of appointment; In this module, accomplish multi-clock zone synchronization of data and buffering; And, arrive transaction layer or application program through HPI or high speed interface dateout according to route control; If what receive is non-Broadcasting-Asynchronous bag, after receiving packet, the link layer nucleus module can return an affirmation and wrap universal serial bus.
The present invention has advantage:
Introduced fault-tolerant design in this link layer controller design, guaranteed that this link layer controller has higher reliability.
The link layer controller of IEEE1394 bus of the present invention and IEEE1394 bus protocol standard are compatible fully; Support the data transmission rate of 100Mbps, 200Mbps and 400Mbps; Whole design uses the VerilogHDL language description to realize; Adopt the thought of sequential logic design, all Module Design all are synchronized to the corresponding work clock, have guaranteed the high-performance of design.In design, do not have to use the special resource to certain FPGA, therefore, this link layer controller has good versatility, does not rely on the FPGA of certain concrete model, also can be used for the ASIC flow and produce.
Utilize link layer controller of the present invention in the FPGA of aerospace level, to realize, perhaps utilize the ASIC flow of anti-irradiation and highly reliable technology, high-grade device is difficult for obtaining problem in the time of can solving the IEEE1394 bus and be applied to China's space mission.
Description of drawings
Fig. 1 is that the system of IEEE1394 link layer controller of the present invention forms sketch map;
Fig. 2 is the composition structure chart of data buffering of the present invention and routing module control;
Fig. 3 is the composition structure chart of link layer nucleus module of the present invention;
The flow chart of fault-tolerant design in Fig. 4 link layer physical layer interface.
Embodiment
With reference to the accompanying drawings the present invention is elaborated.
As shown in Figure 1, the present invention is made up of 5 basic modules altogether: HPI, high speed interface, data buffering and route, link layer nucleus module and configuration register.
HPI partly provides a kind of 16 general bit CPU interfaces, can realize cooperating with the sequential of different CPU through this interface.Host interface module links to each other with configuration register, data buffering and routing module control through 16 BDB Bi-directional Data Bus and some control lines in inside.Outside CPU uses this interface can read and write the inner configuration register of link layer controller, the data buffering area is carried out accessing operation: write packet to be sent or read the packet that receives.The sequential of HPI is accomplished under its clock signal that provides control by outer CPU; Therefore HPI is to the read-write of configuration register; And the clock synchronization that the read-write of data bufferings and routing module control is all provided with outer CPU, the frequency maximum of this clock signal can reach 50Mhz.
High speed interface links to each other with routing module control with data buffering through 32 BDB Bi-directional Data Bus; Link layer controller directly carries out access to outside high-speed memory a interface is provided; This interface can direct access outside high-speed memory, comprise high speed FIFO, dual port RAM etc.; Solved when transmitting when waiting the transmission bottleneck problem of a large amount of high-speed datas.The high speed interface externally data width of (external memory storage) is 16, and internally the data width of (data buffering and routing module control) is 32, and work clock is by the clock generating of link layer controller clock internal control circuit according to the physical layer input.
As shown in Figure 2, data buffering partly links to each other with high speed interface with HPI with routing module control one end, and the other end links to each other with the link layer core, receives the control of configuration register simultaneously.Data buffering and routing module control are made up of 3 parts: asynchronous transmission FIFO, general reception FIFO and data routing module.The function of data routing module is route control, and the data-bus width of input and output is 32, and the one of which end links to each other with the link layer core, and the other end receives FIFO with transmission and high speed interface links to each other.The data routing module is according to the control bit of configuration register when receiving data, and control data outputs to general reception FIFO or high speed interface; When sending data, output to the link layer core according to control corresponding position reading of data from send FIFO or high speed interface.Asynchronous transmission FIFO is between HPI and the route control, is an asynchronous FIFO, and the function that provides is data buffering and different clock-domains synchronization of data.HPI writes data to FIFO under host clock control, routing module control is sense data under internal clocking control, and the degree of depth of FIFO is 512, and data width is 32.General reception FIFO is a degree of depth 512 between HPI and data routing module, the asynchronous FIFO that width is 32, and the function that provides is similar with asynchronous transmission FIFO, but data direction is opposite.
As shown in Figure 3, the link layer nucleus module is realized all functions of link layer in the IEEE1394 bus protocol, comprises modules such as physical layer link layer interface, data buffering processing, data packet transceive module, CRC check module and cycle controller.
The physical layer link layer interface partly provides the standard interface with physical chip; The definition of this interface signal and sequential relationship meet the IEEE1394 bus protocol, and the signal of use has: 7 bidirectional data line D, two two-way control line Ctl; Link layer request signal Lreq; Link layer power state signal LPS, link layer start signal LinkOn, the clock signal Sclk of 50Mhz etc.Wherein, the clock Sclk of 50Mhz is the element task clock of link layer controller, except that the read-write of HPI part and configuration register, and the clock that other all modules are all used this clock or derived as the basis with this clock.In order to improve the reliability of this invention link layer controller; In the design of physical layer link layer interface, adopted fault-tolerant design; Its major function is when avoiding physical layer control signal in the transmission course of link layer an error code to occur; The mistake that possibly cause, the various mistakes that in design, possibly occur to control signal Ctl are analyzed and are handled.
As shown in Figure 4, handling process is following:
Step1: receive the Ctl signal, and judge its value;
Step2:, otherwise continue if Ctl=00B then forwards Step1 to;
Step3: if Ctl=01B then receives the data on the data wire D continuously, finish, forward Step1 then to, otherwise continue until this state (Ctl=01B);
Step4: judging whether 10B of Ctl, is then to forward Step7 to, otherwise continues;
Step5: judge that link layer controller has sent the bus application? Not: forwarding Step1 to, is then to continue;
Step6: take over bus, send packet, transmission turns back to Step1 after finishing;
Is Step7: the value of judgment data line FFH? Not: forwarding Step1 to, is then to continue;
Step8: receive current data, get into the next clock cycle, continue;
Whether the value of Step9:Ctl 00B, not: forward Step8 to, be: continue;
Step10: judge whether to receive 4 complete byte datas, not: forwarding Step8 to, is then to return Step1.
Wherein, the data buffering processing module is that an asynchronous FIFO provides the data buffering function.
The transceiver module of packet is the core of link layer core, links to each other with routing module control with data buffering processing module, CRC module, cycle controller module and data buffering through bidirectional data line.This module mainly provides function to be when sending data: carry out framing, CRC check, send bus arbitration signal, send after receiving non-Broadcasting-Asynchronous bag and confirm bag to bus through physical layer according to different type of data packet to sent packet according to the protocol requirement of IEEE1394, also can produce and send circulation and begin to wrap bus if this node is a cycle controller.When receiving data, the data packet transceive module can receive the packet from universal serial bus that physical layer is transmitted, analysis, address decoding and the CRC check of the line data bag of going forward side by side.If the packet rs destination node that after decoding, transmits on the universal serial bus is that this node and CRC check are correct, then receives this packet, and send to data buffering and routing module control after data are recombinated as requested.
CRC function when the CRC module provides transceive data when sending packet, is partly carried out CRC check to data packet header and data payload respectively as required, produces check code; When receiving packet, the data that receive are carried out verification, and judge whether check results is correct.
Cycle controller is made up of cycle timer and cycle monitor, and cycle timer is one 32 a timer, all compatible IEEE1394 bus protocol of its function and form.If the residing node of link layer controller is a root node, cycle monitor can be sent the application that a transmission circulation begins to wrap by every 125us, and provides circulation to begin to wrap required data to data transmit-receive module.
Configuration register partly provides several registers group of 32, and the effect of this registers group provides the control to link layer controller, and a few thing state of link layer controller is provided simultaneously.Configuration register one end links to each other with HPI, the control bit and the mode bit of the configuration register that can read and write through HPI.In addition configuration register also with link layer controller in other part link to each other, be used for implementing control and obtain state.The data that for example can select to send through configuration register are from HPI or high speed interface, return the type of confirming bag etc.; Also can obtain the state that packet sends, the data volume among the FIFO etc. through configuration register.
Claims (9)
1. the link layer controller of an IEEE1394 bus is characterized in that, described link layer controller comprises: HPI, link layer nucleus module, data buffering and routing module control, high speed interface module and configuration register; Outer CPU can be read and write the data buffer zone in configuration register, access data buffering and the routing module control through described HPI; Described data buffering and routing module control are between link layer nucleus module and HPI and the high speed interface; Be used to provide different transceive data interchannel switching controls; Wherein, Described data buffering and routing module control have also used two asynchronous first-in/first-out memories, are respectively applied for the buffering and the cross clock domain synchronization of data of transceive data; Described configuration register is used to provide initial configuration and the control to link layer nucleus module, data buffering and routing module control, implements to control and obtain the operating state of each module of link layer controller through described HPI read-write configuration register;
Described link layer nucleus module is used for realizing comprising all functions of IEEE1394 bus protocol link layer: physical layer link layer interface, data buffering processing unit, data packet transceive unit, cyclic-redundancy-check unit and cycle controller;
Described physical layer link layer interface is used to provide the link layer of IEEE1394 bus protocol regulation and the standard interface between physical layer;
Described data buffering processing unit uses an asynchronous first-in/first-out memory as the transceive data bag data buffering function to be provided;
Described data packet transceive unit is the core of link layer nucleus module, links to each other with routing module control with data buffering processing unit, cyclic-redundancy-check unit, cycle controller and data buffering through bidirectional data line;
Said cyclic-redundancy-check unit, the CRC function when being used to transceive data is provided;
Said cycle controller comprises cycle timer and cycle monitor, service when being used for waiting;
When sending packet, the packet that writes specified format through HPI is to data buffering and routing module control; Realize the control of buffering, multi-clock zone synchronization of data and the data route of data again through the asynchronous first-in/first-out memory of data buffering and routing module control; Then, get into the link layer nucleus module, carry out the framing and the CRC of data according to the form of different types of data bag in the IEEE1394 bus protocol; Send the bus application of respective type at last to physical layer through the physical layer link layer interface; After this link layer controller place node obtains bus control right, begin to transmit packet to universal serial bus according to the speed of appointment through the physical layer link layer interface;
After packet send to be accomplished,, wait for then that destination node is returned and confirm bag,, also can produce and send circulation and begin to wrap bus if this link layer controller place node is a cycle controller if what send is non-Broadcasting-Asynchronous bag;
When receiving packet; Transmit through physical layer link layer interface reception physical layer; Data packets for transmission on universal serial bus, at the link layer nucleus module, said data packet transceive unit carries out the decoding of address and type of data packet to the packet that receives; If the destination node of this packet is not this node, then the reception of forgo data bag; Otherwise; Begin to receive packet and carry out CRC check; Like the then reception of forgo data bag of check errors, then output to data buffering and routing module control to the data that receive according to the form of appointment as correct, in this module, accomplish multi-clock zone synchronization of data and buffering; And, arrive transaction layer or application program through the HPI dateout according to route control; If what receive is non-Broadcasting-Asynchronous bag, after the completion packet received, the link layer nucleus module returned an affirmation and wraps universal serial bus;
Described physical layer link layer interface has adopted fault-tolerant design, is used for analyzing and handling to the various mistakes that control signal Ctl possibly occur;
Wherein, represent control signals transmitted between physical layer and link layer interface with Ctl, said fault-tolerant design is:
Step1: receive the Ctl signal, and judge its value;
Step2:, otherwise continue if Ctl=00B then forwards Step1 to;
Step3: if Ctl=01B then receives the data on the data wire D continuously, be that Ctl=01B finishes, forward Step1 then to, otherwise continue until this state;
Step4: judging whether 10B of Ctl, is then to forward Step7 to, otherwise continues;
Step5: judge whether link layer controller has sent the bus application, not: forwarding Step1 to, is then to continue;
Step6: take over bus, send packet, transmission turns back to Step1 after finishing;
Step7: whether the value of judgment data line is FFH, and not: forwarding Step1 to, is then to continue;
Step8: receive current data, get into the next clock cycle, continue;
Whether the value of Step9:Ctl 00B, not: forward Step8 to, be: continue;
Step10: judge whether to receive 4 complete byte datas, not: forwarding Step8 to, is then to return Step1.
2. the link layer controller of IEEE1394 bus according to claim 1; It is characterized in that; Described HPI provides a kind of 16 general bit CPU interfaces; Link to each other with configuration register, data buffering and routing module control with control line with the number of address line through 16 BDB Bi-directional Data Bus, realize and the interface of transaction layer, accomplish data transmit-receive and handle;
The sequential of described HPI is accomplished under its clock signal that provides control by the CPU of outside; HPI is to the read-write of configuration register; And the clock synchronization that the read-write of data bufferings and routing module control is all provided with CPU, the frequency maximum of this clock signal can reach 50Mhz.
3. the link layer controller of IEEE1394 bus according to claim 1; It is characterized in that; Described high speed interface module and HPI are arranged side by side; Be used to provide link layer controller directly outside high-speed memory directly to be carried out the interface of access, this high speed interface module links to each other with configuration register with routing module control with data buffering;
Said high speed interface module is 16 to the data width of external memory storage, is 32 to the data buffering of inside and the data width of routing module control, and work clock is produced by the clock division of physical layer input.
4. the link layer controller of IEEE1394 bus according to claim 3 is characterized in that, described high-speed memory comprises: high speed pushup storage and Double Port Random Memory.
5. the link layer controller of IEEE1394 bus according to claim 1 is characterized in that, described data buffering and routing module control comprise: asynchronous transmission pushup storage, general reception pushup storage and data routing unit;
Described asynchronous transmission pushup storage is between HPI and the data routing unit, is an asynchronous first-in/first-out memory that sends asynchronous data packets, is used to send the data buffering and the different clock-domains synchronization of data of asynchronous data packets; HPI writes packet to be sent to the asynchronous transmission pushup storage under host clock control; Data buffering and routing module control be sense data under internal clocking control; The degree of depth of asynchronous transmission pushup storage is 512, and data width is 32;
Described general reception pushup storage is between HPI and data routing unit; Be one and can receive all types packet, the degree of depth 512, the asynchronous first-in/first-out memory that width is 32; Its function is similar with the asynchronous transmission pushup storage, but data direction is opposite;
Said data routing unit is used for route control, and the data-bus width of input and output is all 32, and the one of which end links to each other with the link layer nucleus module, and the other end receives pushup storage with transmission and the high speed interface module links to each other; When receiving data, the data routing unit is according to the control bit of configuration register, and control data outputs to general reception pushup storage or high speed interface module; When sending data, output to the link layer nucleus module according to control corresponding position reading of data from send pushup storage or high speed interface module.
6. the link layer controller of IEEE1394 bus according to claim 1; It is characterized in that; Described configuration register; Comprise some 32 registers group, this registers group is used for the control to each module of link layer controller is provided, and the operating state that link layer controller is provided.
7. the link layer controller of IEEE1394 bus according to claim 1 is characterized in that, described cycle timer is one 32 a timer, is used to produce the timing signal of 125us and time of each node synchronously;
Described cycle monitor is used for keeping watch on cycle timer, and can produce circulation and begin bag and corresponding bus application.
8. the link layer controller of IEEE1394 bus according to claim 1 is characterized in that, the signal definition of described physical layer link layer interface and sequential relationship meet the IEEE1394 bus protocol; The signal that uses comprises: 7 bidirectional data line D; Two two-way control line Ctl, link layer request signal Lreq, link layer power state signal LPS; Link layer start signal LinkOn, the clock signal Sclk of 50Mhz;
Wherein, 50Mhz clock Sclk is the element task clock of link layer controller, and except that the read-write of HPI and configuration register, other all modules all are operated in this clock or are under the clock control that derives of basis with this clock.
9. the link layer controller of IEEE1394 bus according to claim 1 is characterized in that, described link layer controller uses the VerilogHDL language description to realize, adopts the sequential logic design, and each module all is synchronized to the corresponding work clock.
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| CN106844256B (en) * | 2017-02-22 | 2020-09-11 | 天津大学 | Active power distribution network real-time simulator internal interface design method based on multiple FPGAs |
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| CN106713094B (en) * | 2016-12-26 | 2020-05-08 | 北京旋极信息技术股份有限公司 | 1394 data acquisition module |
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| CN101764795A (en) | 2010-06-30 |
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