CN1426203A - Transmission device and method for data package between different buses - Google Patents

Abstract

This invention relates to device and method for transferring data packets among different buses in which the transfer device includes: PCI bus interface module, bus control module, send and receive two interface RAM module, EHI bus interface module. The method includes: reading EHI interrupt register to determine which one has finished the receiving among the three data packets, then to read related data packet information words to determine address of data packet head to be fetched, then to read out the packet head data according to related addresses to be sent to the third process module (CPU) for route searching, flow hierarchy, address analysis to be sent back to second exchange module packet header RAM and modify related data packet information words and point out the third layer action on the packet data to be sent back to second exchange module internal system.

Description

The device and method that packet is transmitted between different bus

Technical field:

The present invention relates to mechanics of communication, particularly index is according to wrapping in the method for transmitting between different bus.

Background technology:

Present campus network, enterprise network, metropolitan area Access Network are because the development of Internet and the application of centralized server, cause discharge model to turn to and be 20/80 new rule by 80/20 original rule, promptly 20% flow is to local working group local area network (LAN), and 80% flow need flow out local network.New discharge model requires network that the disposal ability more than the 3rd layer more efficiently is provided, and simple layer 2 switch will move towards the edge of network.On the other hand, owing to divide the popular of the science of working group and mobile office, make VLAN (being called for short VLAN) technology become the critical function of layer 2 switch by function.Therefore require to have the high speed second layer function of exchange and quick the 3rd layer of data function of handling between VLAN of supported vlans, to adapt to the requirement of new Model of network traffic in the convergence-level (Distribution1ayer) of network.The EHI bus has a kind of novel bus of three layers of bag forwarding capability just, can realize the forwarding of three layers of bag between second layer Switching Module and the 3rd layer of processing module (CPU or network processing unit), layer 2 switching module is mainly finished the linear speed exchange of MAC layer, finish 802.1Q VLAN agreement, 802.1p priority protocol, 802.3x flow control protocol, 802.1D Spanning-Tree Protocol, 802.3u the function of consensus standard standards such as Fast Ethernet control protocol and 802.3z gigabit Ethernet control protocol, and three layers of Switching Module mainly realized the 3rd layer of routing function of packet, comprise searching of routing iinformation, the reorganization of packet and the functions such as forwarding of packet.Just can adopt the EHI bus to transfer Ethernet data bag more than three layers and three layers carrying out external treatment such as the Galnet3 nest plate of Galileo company, and then accept the outside data processed bag of beaming back by this bus.

General the 3rd layer of processing module of being made up of CPU has the pci bus structure, cpu chip MPC8240 such as motorola inc, can not directly link to each other with pci bus from present case EHI bus, also do not have a kind of device directly these two kinds of buses to be coupled together, make packet between them, transmit.

Summary of the invention:

The object of the invention provides a kind of method that a kind of packet is transmitted between different bus, design the device of the two-way forwarding of packet between two different bus, realizes the big transmission function of packet between two kinds of different bus.

The realization of purpose of the present invention is by the design to two mutual interfaces of bus, provides interconnection bridge retransmission unit between bus to realize realizing between two different bus the two-way forwarding of packet.The interconnection bridge retransmission unit comprises four modules: the EHI interface module of the pci interface module of connection pci bus, bus control module, transmitting-receiving dual port RAM module, connection EHI bus, wherein each module realizes by VHDL language, and whole device is realized by programmable logic device.What link to each other with the outside is pci bus signal and EHI bus signals.This interconnection bridge retransmission unit can use one the second layer Switching Module of EHI bus be connected on the 3rd layer of processing module using pci bus, and the hardware logic of being invented makes the two-way forwarding that realizes packet between two buses.

The EHI bus interface module mainly comprises four parts: the main control signal that receives the EHI bus of EHI reiving/transmitting state machine part, and the control signal according to bus control module provides the EHI bus control signal in the suitable clock cycle simultaneously; The information that EHI data channel part mainly provides according to EHI reiving/transmitting state machine merges data message that data address information that the pci bus interface module comes and dual port RAM come and sends address and data message in the suitable clock cycle; Receive the co-ordination that the Data Control part is mainly finished receiving data information (be sent to and receive dual port RAM) and received data address information (from the pci bus interface module); The information that dual port RAM address pointer part mainly provides according to EHI reiving/transmitting state machine produces the read/write address of transmitting-receiving dual port RAM module.

The pci bus interface module mainly comprises five parts: the configuration register part is mainly finished the mapping function in PCI space; The control signal that bus reiving/transmitting state machine part is mainly come according to pci bus produces the read/write address of transmitting-receiving dual port RAM module and provides address information (being sent to the EHI bus interface module) and data message (being sent to transmitting-receiving dual port RAM module) in the suitable clock cycle; The main buffer memory of PCI address date buffer part also separates address and the data message that pci bus is come; The message pick-up that the PCI control section mainly provides according to bus reiving/transmitting state machine also provides the pci bus control signal; The parity check part is mainly carried out parity check and is provided corresponding information pci bus.

The invention provides the method that a kind of packet is transmitted between different bus.This method can be supported the direct forwarding of 64 byte packet header information of three packets simultaneously, specifically will transmit which header packet information and then be decided by the state of RX in the interrupt register of EHI.In practical operation, at first to read the interrupt register of EHI, determine which bag has been accepted to finish in three packets, and then the address of reading the definite data packet head that will read of corresponding packet information word, be the address of PacketHeader RAM, read header data according to appropriate address again and send the 3rd layer of processing module (CPU) to carry out operations such as route querying, flow classification, address resolution; The 3rd layer of processing module finished after the operation of header data it being sent it back the Packet HeaderRAM of second layer Switching Module, revise corresponding packet information word simultaneously, point out the 3rd layer of operation that processing module is done header data, then by writing the built-in system of lining up the data packet head information back second layer Switching Module after command register will be handled.Word is made up of nybble (32) data.Dual port RAM can receive data and transmit data to EHI interface direction in the write operation process from pci interface, in the read operation process, receive data and send data to pci interface from the EHI interface, by pci bus interface logic detection target ready signal, and the EHI bus interface logic is monitored the pci bus state at any time and is made it can in time respond pci bus operation, and these are realized by the bus control module between two bus interface logics.

Pci interface is sent to interconnection bridge with destination address in the process that starts read-write operation, undertaken directly being sent to the EHI bus interface module after the address transition by the pci bus interface module, and the EHI bus interface module is finished the merging and the lock out operation of data and address signal.Integrated configuration register in the pci bus interface module arrives the PCI address space by the operation handlebar EHI interface mappings to configuration space, and EHI per-interface space size, clock frequency etc. can be set as required.Wherein, the read-write operation process that is started by pci interface can be finished the transmission of 64 byte datas at most, also supports arbitrarily the transmission less than 64 byte datas simultaneously.

Pci bus is the data address multiplex bus, and what this interconnection bridge retransmission unit related generally to is 32 pci buss, its basic read-write sequence such as Fig. 6, shown in Figure 7, the equal accord with PCI bus specification of all operations.The sequential chart of the pci bus signal when Fig. 6 represents to happen suddenly write data, the sequential chart of the pci bus signal when Fig. 7 represents to happen suddenly read data, clock signal clk provides the PCI communication is carried out synchronously, frame signal (FRAME#) indicates that effectively bus transfer begins, the side's of startup ready signal (IRDY#) indicates the transmission when main equipment is prepared the beginning data, target ready signal (TRDY#) indicates the transmission when target is prepared the beginning data, address/data signal (AD[31:0]) is used for the transmission of address signal and data-signal, order/byte enable signal (C/BE#) provides pci bus instruction and byte enable signal, and choice of equipment signal (DEVSEL#) shows that target effective deciphers its address.

The EHI bus also is a kind of 32 bit address data multiplex buses, its basic read-write sequence such as Fig. 4, shown in Figure 5.The sequential chart of the various EHI bus signals the when sequential chart of the various EHI bus signals when Fig. 4 represents external device (ED) burst write data, Fig. 5 are represented external device (ED) burst read data.Effective address cycle in address latch signal (Ads) the indication read-write operation, and address/data letter bus when this signal is effective (AD[31:0]) upward be effective address signal; Standby ready signal (Rdy) shows that when read operation the EHI interface drives valid data to address/data bus, show that when write operation the EHI interface prepares from the address/data bus sampled data signal, real sampling is finished effectively the time simultaneously at Rdy signal and useful signal (Valid); Last valid data cycle of burst (Blast) indication read-write operation; Read-write (RW) high level is represented the current write operation that is operating as, and low level is represented the current read operation that is operating as.

By visit, can carry out operations such as route querying, flow classification, address resolution to the received packet of second layer Switching Module to each register of EHI interface, RAM, first-in first-out space FIFO.Can visit the header packet information (Packet Header) of 64 bytes in the received packet of second layer Switching Module by the EHI interface, also can accept or send whole packet from second layer Switching Module by dma mode, on the EHI interface, can support the direct forwarding of 64 byte packet header information of three packets simultaneously, specifically will transmit which header packet information and then decide by the state of RX in the interrupt register of EHI.In practical operation, at first to read the interrupt register of EHI, determine which bag has been accepted to finish in three packets, and then the address of reading the definite data packet head that will read of corresponding packet information word, be the address of Packet Header RAM, read header data according to appropriate address again and send the 3rd layer of processing module (CPU) to carry out operations such as route querying, flow classification, address resolution; The 3rd layer of processing module finished after the operation of header data it being sent it back the Packet Header RAM of second layer Switching Module, revise corresponding packet information word simultaneously, point out the 3rd layer of operation that processing module is done header data, then by writing the built-in system of lining up the data packet head information back second layer Switching Module after command register will be handled.If the 3rd layer of processing module do not carried out any processing to header data or transport process middle wrapping head data are made mistakes, can ignore this operation or abandon this packet by packet information word corresponding positions indication second layer Switching Module is set.

For the hardware logic of this interconnection bridge retransmission unit, we come emulation and realization by programmable logic device.The read-write operation flow chart that it is concrete such as Fig. 8, shown in Figure 9.

Claims (5)

1. device that packet is transmitted between different bus, it is characterized in that, this retransmission unit can be connected to the second layer Switching Module of a use EHI bus on the 3rd layer of processing module using pci bus, and this retransmission unit comprises pci bus interface module, the bus control module of coordinating the transmitting-receiving operation between two kinds of interfaces of pci bus and EHI bus, the transmitting-receiving dual port RAM module that is used for temporarily storing read data and write data that connects pci bus, the EHIBUS interface module that is connected the EHI bus.

2. according to the described retransmission unit of claim 1, it is characterized in that the EHI interface module comprises: receive the control signal of EHI bus,, provide the EHI reiving/transmitting state machine of EHI bus control signal simultaneously according to the control signal of bus control module; The information that provides according to EHI reiving/transmitting state machine merges the data message that data address information that the pci bus interface module comes and dual port RAM come and sends the address and the EHI data channel part of data message; Finish the reception Data Control part of receiving data information and the co-ordination of reception data address information; The information that provides according to EHI reiving/transmitting state machine produces the dual port RAM address pointer part of the read/write address of transmitting-receiving dual port RAM module.

3. according to the described retransmission unit of claim 1, it is characterized in that the pci interface module comprises: the configuration register of finishing the mapping function in PCI space; The control signal of coming according to pci bus produces the read/write address of transmitting-receiving dual port RAM module and provides address information and the bus reiving/transmitting state machine of data message; Buffer memory also separates the next address of pci bus and the PCI address date buffer of data message; Message pick-up that provides according to bus reiving/transmitting state machine and the PCI control section that provides the pci bus control signal; Pci bus is carried out parity check and provided the parity check part of corresponding information.

4, the method between different bus, transmitted of a kind of packet, it is characterized in that to support simultaneously the direct forwarding of 64 byte packet header information of three packets, at first to read the interrupt register of EHI, determine which bag has been accepted to finish in three packets, and then the address of reading the definite data packet head that will read of corresponding packet information word, read header data according to appropriate address again and send the 3rd layer of processing module (CPU) to carry out operations such as route querying, flow classification, address resolution; The 3rd layer of processing module finished after the operation of header data it being sent it back the PacketHeader RAM of second layer Switching Module, revise corresponding packet information word simultaneously, point out the 3rd layer of operation that processing module is done header data, then by writing the built-in system of lining up the data packet head information back second layer Switching Module after command register will be handled.

5, the method for between different bus, transmitting by the described packet of claim 4, it is characterized in that the 3rd layer of processing module do not carried out any processing to header data or transport process middle wrapping head data are made mistakes, can ignore this operation or abandon this packet by packet information word corresponding positions indication second layer Switching Module is set.

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