CN101750577A - Semiconductor test system - Google Patents
Semiconductor test system Download PDFInfo
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- CN101750577A CN101750577A CN200810187152A CN200810187152A CN101750577A CN 101750577 A CN101750577 A CN 101750577A CN 200810187152 A CN200810187152 A CN 200810187152A CN 200810187152 A CN200810187152 A CN 200810187152A CN 101750577 A CN101750577 A CN 101750577A
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Abstract
The invention provides a semiconductor test system which comprises a test card structure of at least one type and a plurality of different types of semiconductor object-to-be-tested testers. The upper surface of the test card of at least one type is provided with a plurality of probe coupling interfaces. Each semiconductor object-to-be-tested tester at least has a connector and an interface board; the upper surface and the lower surface of the interface board are respectively provided with a plurality of upper layer interface board coupling interfaces and a plurality of lower layer interface board coupling interfaces; and the types of the upper layer interface board coupling interfaces are different according to the different types of the semiconductor object-to-be-tested testers. Therefore, through the matching of the connectors and the interface boards, the different types of the semiconductor object-to-be-tested testers can use the same type of test card.
Description
Technical field
The present invention relates to a kind of semiconductor test system, be meant that especially a kind of different tester table can share the semiconductor test system of the probe of same types.
Background technology
After wafer (wafer) manufacturing is finished, just need enter the wafer sort stage to guarantee its functor standardization.Generally, wafer sort is to utilize tester table and probe card configuration (probe card) to come each crystal grain on the test wafer, with the electrical specification of guaranteeing crystal grain and usefulness according to original design specification.And along with chip functions is stronger more complicated, also just more important with accurate testing requirement at a high speed.
In addition, probe card configuration is applied to integrated circuit (IC) as yet before the encapsulation, does function test at naked crystalline substance with probe (probe needle), filtering out defective products, and then the encapsulation engineering after carrying out.Therefore, it is in the integrated circuit manufacturing manufacturing cost to be influenced one of sizable critical processes.
In the general test process, at first, again probe card configuration is fixed on the tester table on the tester table crystal grain on the wafer being located, so that the weld pad on the crystal grain is aimed at the probe of probe card configuration, and contact with it.
Yet generally each different tester table need cooperate different connectors, interface board and probe card configuration, so the connector of different tester tables, interface board and probe card configuration can't be shared.Therefore, the situation of testing producing lines traffic congestion takes place when finding a certain tester table at test wafer, because different tester tables are under the situation that can't share the same probe card structure in the prior art, the problem of traffic congestion can't be resolved in the above-mentioned prior art.
Summary of the invention
Technical matters to be solved by this invention provides a kind of semiconductor test system, and by the cooperation of an a connector and an interface board, the test card structure of same types selectively is applied in the semiconductor determinand tester table of a plurality of different types.
In order to solve the problems of the technologies described above, embodiments of the invention provide technical scheme as follows:
According to wherein a kind of scheme of the present invention, a kind of semiconductor test system is provided, it comprises: the semiconductor determinand tester table of the test card structure of at least a pattern and many different types.Wherein, the surface of the test card structure of this at least a pattern has a plurality of probe coupled interface.Each semiconductor determinand tester table has an a connector and an interface board at least, the upper surface of this connector and lower surface have a plurality of upper stratas coupled interface respectively and a plurality of lower floor couples interface, the upper surface of this interface board and lower surface have respectively that a plurality of high-level interface plates couple interface and a plurality of lower floors interface board couples interface, and the pattern that each high-level interface plate couples interface is different according to the semiconductor determinand tester table of above-mentioned different types, described lower floor interface board couples interface and couples the interface ground that corresponds to each other with described upper strata respectively and mutually electrically connect, and the described probe of this test card structure couples interface and couples interface electric connection mutually accordingly with described lower floor; Therefore, by the cooperation of this connector and this interface board, the semiconductor determinand tester table of different types can use the test card structure of same types.
Embodiments of the invention have following beneficial effect:
By the cooperation of an a connector and an interface board, the test card structure of same types selectively is applied in the semiconductor determinand tester table of a plurality of different types.
Description of drawings
Fig. 1 is the wherein side-looking decomposing schematic representation of three semiconductor determinand tester tables in the semiconductor test system of the present invention;
Fig. 2 is the side-looking combination synoptic diagram of first semiconductor determinand tester table among Fig. 1;
Fig. 3 is the side-looking combination synoptic diagram of second semiconductor determinand tester table among Fig. 1; And
Fig. 4 is the side-looking combination synoptic diagram of the 3rd semiconductor determinand tester table among Fig. 1.
The primary clustering symbol description
Semiconductor determinand tester table M1, M2, M3
Measuring head H1, H2, H3
Interface plate F1, F2, F3
The high-level interface plate couples interface F12, F22, F32
Lower floor's interface board couples interface F11, F21, F31
Connector T
Upper strata coupled interface T2
The coupled interface T1 of lower floor
Test card structure P1
Probe coupled interface P10
Probe P11
Determinand A
Embodiment
For technical matters, technical scheme and advantage that embodiments of the invention will be solved is clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
See also Fig. 1 to shown in Figure 4, the invention provides a kind of semiconductor test system, it comprises: the semiconductor determinand tester table (M1, M2, M3) of the test card structure P1 of at least a pattern and many different types.
Wherein, the upper surface of this test card structure P1 (for example probe card configuration) has a plurality of probes and couples interface P10, and the lower surface of this test card structure P1 is provided with a plurality of probe P11, to be used to carry out the performance test of a determinand A (for example wafer).In addition, described probe couples the outer peripheral areas that interface P10 is arranged at this test card structure P1 upper surface.
In addition, each semiconductor determinand tester table (M1, M2, M3) has a measuring head (H1, H2, H3), a connector (for example probe column (pogo tower)) T and an interface board (F1, F2, F3) at least.Each interface plate (F1, F2, F3) is arranged at each measuring head (H1, H2, H3) below.
In addition, the upper surface of this connector T and lower surface have a plurality of upper strata coupled interface T2 and a plurality of coupled interface T1 of lower floor respectively.Described upper strata couples the outer peripheral areas that interface T2 is arranged at this connector T upper surface, and described lower floor couples the outer peripheral areas that interface T1 is arranged at this connector T lower surface.The pattern that each lower floor couples interface T1 is all identical, and the pattern that each upper strata couples interface T2 is all identical.
In addition, upper surface of each interface board (F1, F2, F3) and lower surface have respectively that a plurality of high-level interface plates couple interface (F12, F22, F32) and a plurality of lower floors interface board couples interface (F11, F21, F31).Described high-level interface plate couples the outer peripheral areas that interface (F12, F22, F32) is arranged at this interface plate (F1, F2, F3) upper surface, and described lower floor interface board couples the outer peripheral areas that interface (F11, F21, F31) is arranged at this interface plate (F1, F2, F3) lower surface.The pattern that each high-level interface plate couples interface (F12, F22, F32) is different according to the measuring head (H1, H2, H3) of the semiconductor determinand tester table (M1, M2, M3) of above-mentioned different types, and each lower floor's interface board to couple the pattern of interface (F11, F21, F31) all identical.
In addition, described lower floor interface board couples interface (F11, F21, F31) and electrically connects mutually with described upper strata coupled interface T2 respectively with corresponding to each other, and the described probe of this test card structure P1 couples interface P10 and described lower floor couples interface T1 electric connection mutually accordingly.
Yet, above-mentioned described probe coupled interface P10, described high-level interface plate couple interface (F12, F22, F32), described lower floor interface board couple interface (F11, F21, F31), described upper strata coupled interface T2, and the set position of the described coupled interface T1 of lower floor just be used for for example, and be not to be used for limiting the present invention.
Therefore, by the cooperation of this connector T and this interface board (F1, F2, F3), the test card structure P1 of same types selectively is applied in the semiconductor determinand tester table (M1, M2, M3) of above-mentioned different types.
The above is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. a semiconductor test system is characterized in that, comprising:
The test card structure of at least a pattern, its upper surface have at least one probe coupled interface; And
The semiconductor determinand tester table of at least one different types, wherein each semiconductor determinand tester table has an a connector and an interface board at least, the upper surface of this connector and lower surface have at least one upper strata coupled interface respectively and at least one lower floor couples interface, the upper surface of this interface board and lower surface have respectively that at least one high-level interface plate couples interface and at least one lower floor's interface board couples interface, and the pattern that each high-level interface plate couples interface is different according to the semiconductor determinand tester table of above-mentioned different types, described lower floor interface board couples interface and couples the interface ground that corresponds to each other with described upper strata respectively and mutually electrically connect, and the described probe of this test card structure couples interface and couples interface electric connection mutually accordingly with described lower floor.
2. semiconductor test system according to claim 1 is characterized in that: the lower surface of this test card structure is provided with at least one probe.
3. semiconductor test system according to claim 1 is characterized in that: described probe couples the outer peripheral areas that interface is arranged at this test card structure upper surface.
4. semiconductor test system according to claim 1 is characterized in that: described high-level interface plate couples the outer peripheral areas that interface is arranged at this interface board upper surface, and described lower floor interface board couples the outer peripheral areas that interface is arranged at this interface board lower surface.
5. semiconductor test system according to claim 1 is characterized in that: described upper strata couples the outer peripheral areas that interface is arranged at this connector upper surface, and described lower floor couples the outer peripheral areas that interface is arranged at this connector lower surface.
6. semiconductor test system according to claim 1 is characterized in that: the pattern that each lower floor couples interface is all identical, and the pattern that each upper strata couples interface is all identical, and each lower floor's interface board to couple the pattern of interface all identical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810187152A CN101750577A (en) | 2008-12-17 | 2008-12-17 | Semiconductor test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810187152A CN101750577A (en) | 2008-12-17 | 2008-12-17 | Semiconductor test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101750577A true CN101750577A (en) | 2010-06-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810187152A Pending CN101750577A (en) | 2008-12-17 | 2008-12-17 | Semiconductor test system |
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| Country | Link |
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| CN (1) | CN101750577A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104181453A (en) * | 2013-05-24 | 2014-12-03 | 标准科技股份有限公司 | Chip testing machine |
| CN110133473A (en) * | 2018-02-09 | 2019-08-16 | 矽利康实验室公司 | Semiconductor test system with flexible and steady form factor |
-
2008
- 2008-12-17 CN CN200810187152A patent/CN101750577A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104181453A (en) * | 2013-05-24 | 2014-12-03 | 标准科技股份有限公司 | Chip testing machine |
| CN110133473A (en) * | 2018-02-09 | 2019-08-16 | 矽利康实验室公司 | Semiconductor test system with flexible and steady form factor |
| CN110133473B (en) * | 2018-02-09 | 2021-06-29 | 矽利康实验室公司 | Semiconductor test system with flexible and robust form factor |
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| PB01 | Publication | ||
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| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20100623 |