CN101742078A - Synchronous clock extraction device and method therefor - Google Patents
Synchronous clock extraction device and method therefor Download PDFInfo
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Abstract
The invention discloses a synchronous clock extraction device and a method therefor; wherein the method comprises the following steps: obtaining horizontal synchronous separation threshold value determined according to a signal standard system and sampling clock rate by a vertical sync separator; comparing horizontal synchronous separation threshold value with interference composite synchronizing signal sampling attribute value and obtaining delayed composite synchronizing signal with interference eliminated according to the comparison result. Therefore, with the device and method adopted, possible impulse interference in signals can be removed. In addition, phase discrimination is carried out on a first signal and the delayed composite synchronizing signal, control voltage is generated according to the phase discrimination result, a pixel clock signal is generated according to a control oscillator, frequency division is carried out on the pixel clock signal according to frequency division ratio determined by the signal standard system to obtain horizontal synchronous signals; wherein the first signal is obtained by carrying out deferred processing on the horizontal synchronous signals according to the horizontal synchronous separation threshold value, so that time delay in the synchronous signals resulting from removing impulse can be compensated.
Description
The application is that China formerly applies for a patent dividing an application of " a kind of synchronised clock extraction element and method ", and the application number of formerly applying for a patent is CN 200810005217.6, and the applying date is on January 31st, 2008.
Technical field
The present invention relates to communication and computer realm, relate in particular to the clock treatment technology.
Background technology
The synchronizing clock signals that video image needs comprises that line synchronizing signal (may also be referred to as horizontal synchronization (Horizontal Sync, HS) signal) and vertical synchronizing signal and (may also be referred to as field synchronization (VerticalSync, VS) signal).Wherein line synchronizing signal gated sweep line feed, vertical synchronizing signal gated sweep carry over, signal as the 864*625i@50Hz form, it will scan 50 by vertical synchronizing signal control per second, by need of line synchronizing signal control 312.5 row of lining by line scan, so the line frequency of this signal is 312.5*50=15.625KHz.Utilize this synchronizing clock signals, can also produce analog to digital converter (Analog-Digital Converter, ADC) sampling clock of Xu Yaoing.
Synchronizing clock signals is embedded in the analog video signal usually, as be embedded in green and (be called green and embed (Sync on Green synchronously, SOG)) in, perhaps being embedded in luminance signal (is called luminance signal and embeds (Sync on Luma synchronously, SOY)) in, perhaps be embedded in compound composite video signal (Composite Video Broadcast Signal, CVBS) in.Therefore need at first from above-mentioned analog video signal, to isolate synchronizing clock signals, could obtain the sampling clock of line synchronizing signal, vertical synchronizing signal and ADC needs then according to this synchronizing clock signals.
At present, generally by synchronised clock extraction element shown in Figure 1, realize the separation of synchronizing signal and produce the sampling clock that ADC needs.As can be seen, this synchronous clock circuit comprises: clamper (clamp) and composite sync separator (slicer), synchronously capable and vertical sync separator (abbreviation row field synchronization separator, HS and VS separator, HVS), phase-locked loop (Phase Locked Loop, PLL) and delay phase-locked loop (Delay Locked Loop, DLL).The operation principle of this synchronised clock extraction element is as follows:
By clamper and composite sync separator, from the vision signal (as SOY signal or SOG signal etc.) that embeds synchronizing signal, isolate composite sync (Composite Sync, CS) signal; CS after space field synchronization separator separating treatment, is obtained the VS signal and (Coast) signal of windowing, simultaneously CS signal and Coast signal are defeated by PLL; PLL utilizes the Coast signal that the CS signal is carried out windowing and handles, get access to the line synchronizing signal HS in the CS signal, the HS signal that obtains is carried out frequency multiplication obtain pixel clock PIX, by DLL the phase place of pixel clock is adjusted again, finally obtain the sampling clock that ADC needs.
As shown in Figure 2, provided the sequential relationship signal of from the Y/Pb/Pr signal of 864*625i@50Hz form, isolating synchronizing clock signals, Video signal wherein is the SOY signal, the CS signal is the CS signal that the SOY signal obtains after by the composite sync separator, and HS signal and VS signal are respectively line synchronizing signal and the field sync signal that the CS signal obtains after by a row separator.
Usually, the vision signal of practical application is easy to be interfered, particularly the CVBS signal.After the vision signal that is interfered is handled through the composite sync separator, the composite synchronizing signal that obtains has more impulse disturbances, to directly influence PLL work if composite synchronizing signal is subjected to impulse disturbances, even cause the PLL losing lock, thereby can't obtain pixel clock.Therefore need to remove the impulse disturbances in the synchronizing signal.
Summary of the invention
The invention provides a kind of synchronised clock extraction element and method, this scheme can be eliminated the impulse disturbances that may exist from the synchronizing signal that vision signal is obtained.
The present invention is achieved by the following scheme:
The embodiment of the invention provides a kind of synchronised clock extraction element, comprises the composite sync separator, is used for the interference signal of input and the discrete level of setting are compared, and according to comparative result, obtains to disturb composite synchronizing signal; Described synchronised clock extraction element also comprises:
Vertical sync separator is used for the interference composite synchronizing signal that described composite sync separator is obtained is carried out sample count, obtains disturbing composite synchronizing signal sample count value; And determined horizontal synchronization separates threshold value with the sampling clock frequency to obtain standard system according to signal; Described horizontal synchronization is separated threshold value compare with disturbing composite synchronizing signal sample count value, according to comparative result, the composite synchronizing signal that delay is arranged after the interference that is eliminated; It is corresponding that the delay of the described composite synchronizing signal that delay arranged and described horizontal synchronization separate threshold value.
The embodiment of the invention also provides another kind of synchronised clock extraction element, and described synchronised clock extraction element comprises:
First filter is used for the interference signal of input is carried out Filtering Processing, and the composite synchronizing signal of delay is arranged after the interference that is eliminated;
Phase-locked loop, be used for first signal and describedly have the composite synchronizing signal of delay to carry out phase demodulation, produce control voltage according to identified result, control generator produces secondary signal, according to the frequency dividing ratio of determining according to the standard system of signal described secondary signal is carried out frequency division, obtain the 3rd signal;
Described first signal utilizes filter that described the 3rd signal that is input to described filter is postponed to handle and obtains according to the employed clock frequency of composite synchronizing signal that is input to phase discriminator;
Described secondary signal is a pixel clock signal, and described the 3rd signal is a horizontal-drive signal.
The embodiment of the invention also provides a kind of synchronised clock extracting method, and this synchronised clock extracting method comprises:
The interference signal of input and the discrete level of setting are compared, and, obtain to disturb composite synchronizing signal according to comparative result;
To disturbing composite synchronizing signal to carry out sample count, obtain disturbing composite synchronizing signal sample count value; Obtain horizontal synchronization and separate threshold value; Described horizontal synchronization is separated threshold value to be compared with disturbing composite synchronizing signal sample count value, according to comparative result, being eliminated has the composite synchronizing signal of delay after disturbing, and it is corresponding that the delay of the described composite synchronizing signal that delay arranged and described horizontal synchronization separate threshold value.
The embodiment of the invention also provides another kind of synchronised clock extracting method, and described synchronised clock extracting method comprises:
Interference composite synchronizing signal to input is carried out Filtering Processing, and the composite synchronizing signal of delay is arranged after the interference that is eliminated;
To first signal with describedly have the composite synchronizing signal of delay to carry out phase demodulation, produce control voltage according to identified result, control generator produces secondary signal, according to the frequency dividing ratio of determining according to the standard system of signal described secondary signal is carried out frequency division, obtains the 3rd signal;
Described first signal utilizes filter that described the 3rd signal that is input to described filter is postponed to handle and obtains according to the employed clock frequency of the composite synchronizing signal of phase discrimination processing;
Described secondary signal is a pixel clock signal, and described the 3rd signal is a horizontal-drive signal.
By as can be seen above-mentioned, determined horizontal synchronization separates threshold value to the embodiment of the invention with the sampling clock frequency by obtaining standard system according to signal; Horizontal synchronization is separated threshold value to be compared with disturbing composite synchronizing signal sample count value, according to comparative result, be eliminated the composite synchronizing signal that delay is arranged after disturbing, so the present invention can eliminate the impulse disturbances that may exist from the synchronizing signal that vision signal is obtained.
Description of drawings
The structural representation of the synchronised clock extraction element that Fig. 1 provides for prior art;
The sequential relationship signal of from the Y/Pb/Pr signal, isolating synchronizing clock signals that Fig. 2 provides for prior art;
The structural representation of the synchronised clock extraction element that Fig. 3 provides for first embodiment of the invention;
Fig. 4 is that the signal waveform of the vertical sync separator in the first embodiment of the invention is handled schematic diagram;
Fig. 5 obtains the flow chart of lock-out pulse peak value for the vertical sync separator in the first embodiment of the invention;
Fig. 6 is the structural representation of the phase-locked loop in the first embodiment of the invention;
Fig. 7 is the structural representation of second embodiment of the invention;
Fig. 8 is the structural representation of the phase-locked loop in the second embodiment of the invention.
Embodiment
First embodiment of the invention provides a kind of synchronised clock extraction element, and its structured flowchart comprises as shown in Figure 3: clamper and composite sync separator, vertical sync separator, standard detector, phase-locked loop and delay phase-locked loop.
Above-mentioned clamper is used for embedding had in the interference signal (as, vision signal) of synchronizing signal recovering flip-flop, and will comprise the described interference signal that recovers flip-flop and flow to described composite sync separator.
The composite sync separator is used for the level of the signal of above-mentioned clamper output and the discrete level of setting are compared, and obtains disturbing composite synchronizing signal according to comparative result.
To embed synchronous interference SOY signal is example, clamper goes out the d-c reinsertion of SOY signal, the composite sync separator with the discrete level threshold ratio of the level of the SOY signal that comprises the flip-flop that recovers of clamper output and setting, obtain disturbing composite synchronizing signal according to comparative result, it is the CS signal, be higher than the discrete level of setting as the level of SOY-speech number, then the level with signal is changed to low level; Otherwise, the level of signal is changed to high level, the signal that obtains has been realized isolating the interference composite synchronizing signal from disturb luminance signal for disturbing composite synchronizing signal CS like this.
Vertical sync separator, the interference composite synchronizing signal that is used for described composite synchronizing signal is obtained is carried out sample count, obtains disturbing composite synchronizing signal sample count value; And obtain to separate threshold value according to the standard system of signal with the horizontal synchronization that the sampling clock frequency is determined, be designated as NHS; Described horizontal synchronization separation threshold value and described interference composite synchronizing signal sample count value are compared, according to comparative result, the composite synchronizing signal CS ' that delay is arranged after the interference that is eliminated.Vertical sync separator can separate threshold value NHS with this horizontal synchronization and deposit register in.
Described vertical sync separator may further include: sample counter, horizontal separation threshold value obtain unit and interference cancellation unit.
Sample counter is used for obtaining disturbing composite synchronizing signal sample count value to disturbing composite synchronizing signal to carry out sample count.
The horizontal separation threshold value obtains the unit, and determined horizontal synchronization separates threshold value with the sampling clock frequency to be used to obtain standard system according to signal.
Interference cancellation unit, be used for described horizontal synchronization separation threshold value and described composite synchronizing signal sample count value are compared, and when described composite synchronizing signal sample count value was higher than described horizontal synchronization and separates threshold value, the composite synchronizing signal that delay is arranged after disturbing was eliminated in output.
Above-mentioned vertical sync separator also comprises: the vertical separation threshold value obtains the unit and vertical synchronizing signal obtains the unit.
Wherein, the vertical separation threshold value obtains the unit, and determined vertical synchronization separates threshold value with the sampling clock frequency to be used to obtain standard system according to signal, is designated as NVS; Correspondingly, vertical synchronizing signal obtains the unit, is used for described vertical synchronization separation threshold value and composite synchronizing signal sample count value are compared, and obtains the vertical synchronizing signal of delay according to comparative result.Promptly when described composite synchronizing signal sample count value was higher than described vertical synchronization and separates threshold value, the vertical synchronizing signal that delay is arranged after disturbing was eliminated in output.
Wherein, above-mentioned horizontal separation threshold value obtains the unit and may further include:
The first horizontal separation threshold value obtains subelement, is used for according to described composite synchronizing signal sample count value, obtains the lock-out pulse peak value; According to the standard system and the sampling clock frequency of signal, obtain horizontal synchronization parameter (pulsewidth that can further disturb according to required removal is determined more accurate horizontal synchronization parameter); And, obtain horizontal synchronization and separate threshold value NHS according to described lock-out pulse peak value and described horizontal synchronization parameter.
Above-mentioned vertical separation threshold value obtains the unit and may further include:
The first vertical separation threshold value obtains subelement, is used for the count value according to the composite synchronizing signal sampling, obtains the lock-out pulse peak value; According to the standard system of sampling clock frequency and signal, obtain vertical synchronization parameter (pulsewidth that can further disturb according to required removal is determined more accurate horizontal synchronization parameter); According to described lock-out pulse peak value and described vertical synchronization parameter, obtain vertical synchronization and separate threshold value NVS.
The concrete disposition of vertical sync separator is as follows:
The polarity of CS is judged and corrected to vertical sync separator to sampling by noisy composite synchronizing signal CS; By to composite synchronizing signal CS sample count, the CS after correct obtains lock-out pulse peak value (NHS-top); On lock-out pulse peak value basis, subtract a horizontal synchronization parameter and (be designated as Δ 1, this value can be according to the standard system of sampling clock frequency, signal and the pulsewidth of required removal interference (burr), by register by human configuration, with 27MHz sampling clock, standard TSC-system (its synchronous head pulsewidth is 4.7us) is example, remove the burr that pulsewidth is 0.5us, it is calculated as follows: Tsample=1/27MHz=37ns; Lock-out pulse peak value=4.7us/Tsample=127; Want the number of samples=0.5us/Tsample=13.5 of the pulsewidth of deburring; So Δ 1 should be got the value smaller or equal to (127-14)=113) back acquisition horizontal synchronization separation threshold value NHS; Add a vertical synchronization parameter on the lock-out pulse peak value basis and (be designated as Δ 2, this value can be according to the standard system of sampling clock frequency, signal and the pulsewidth of required removal interference (burr), by register by human configuration, for example, get the size of a sync peaks) acquisition vertical synchronization separation threshold value NVS; Horizontal synchronization is separated threshold value NHS and CS sample count value compares in real time, determine that CS sample count value is higher than horizontal synchronization and separates threshold value NHS, output signal, promptly eliminate the CS ' that disturbs, (because when definite CS sample count value changed in horizontal synchronization separation threshold value NHS, therefore the ability output signal when carrying out interference elimination treatment to the isolated CS of composite sync separator, CS ' the signal that can cause obtaining has certain delay, and be NHS sampling clock cycle concrete time of delay); Simultaneously vertical synchronization is separated threshold value NVS and compare in real time, obtain the vertical synchronizing signal VS (be NVS sampling clock cycle concrete time of delay) of certain delay with the count value that CS is sampled.Above-mentioned signal waveform is handled signal as Fig. 4.
Vertical sync separator can realize obtaining lock-out pulse peak value (NHS-top) by sample counter, sample register and coincidence counter.When obtaining lock-out pulse peak value (NHS-top), the value of sample counter and the value of sample register are compared, and renewal sample register, make in to the CS sampling process, what sample register was preserved is the maximum of sample counter, when the value of sample counter arrives " 0 ", read the value of sample register, and with sample register also reset.Have only when the value of the sample register that read continuous 28 times all in 10 to 150 scope, that is counted preceding 10 times, put flag1=1 (even flag1 is effective), count again and put flag2=1 (even flag2 is effective) for 8 times, counted again afterwards 10 times, 8 times data are preserved and are asked average in the middle of just getting, and the mean value of trying to achieve as lock-out pulse peak value (NHS-top) (do like this is to cause averaging inaccurate for the preceding equilibrium of avoiding vision signal and the interference of post-equalizing pulse (as Fig. 2)).Above-mentioned is with data 28,10 and 150 describe for example, but the embodiment of the invention is not limited thereto, for example data 28 also can be that (this value is for balanced blanking before effectively escaping (6 row) and post-equalization blanking (6 is capable) greater than 13, get the sync peaks of the delegation in the middle of it again) less than any number of 190 (this value is to determine according to all line numbers of minimum standard), data 10 also can be for (this value determines according to the degree that signal is disturbed greater than 1, if disturb little, can be 1, if disturb bigger, then this value is by the merchant's decision that obtains after disturbing big pulse divided by Tsample) and less than 17 any number of (this value is the merchant's decision that obtains after divided by Tsample of the synchronous pulsewidth of maximum standard), data 150 can be (this value is determined by the merchant that the pulsewidth of minimum standard obtains after divided by Tsample) and less than peaked any number of sample counter greater than 129.The idiographic flow that vertical sync separator obtains the lock-out pulse peak value is as shown in Figure 5, and is specific as follows:
During beginning sample counter, coincidence counter, sample register and flag1 and flag2 are all put 0, the clock signal that with the sampling clock frequency is 27MHz is sampled to the CS that adjusts after the polarity, if adopt CS is high level, then allow sample counter add 1, if this moment, CS was a low level, then sample counter subtracts 1; If reaching the counter maximum, the count value of sample counter (is also referred to as the top of counter, the counter maximum is set to 511 in this example) or the counter minimum value (be also referred to as the bottom of counter, the counter minimum value is set to 0 in this example) time, then allow sample counter remain maximum or minimum value; Then, check the value of sample counter and the value of itself and sample register is compared, if the data of sample counter are big, then the value with sample counter deposits sample register in, otherwise sample register then keeps initial value, have only the value of sample counter to reach at 0 o'clock, sample register just puts 0 again, and the sample register record is the maximum of each sample counter like this, sees sample register waveform among Fig. 4; Before sample register puts 0, read the value of register, if the value of register is greater than 10 and less than 150, then allow coincidence counter add 1, and begin to allow it add up always, when the value of coincidence counter reaches 10 for the first time, putting flag1 is 1, and coincidence counter puts 0 simultaneously; After flag1 was 1, then the value of sample counter all was deposited into register i (i is 1 to 8) at every turn, and when coincidence counter was added to 8, putting flag2 was 1, and coincidence counter puts 0 simultaneously; After flag1 and flag2 were 1, if coincidence counter is added to 10, putting flag1 and flag2 was 0, and the value with 8 registers in front adds up simultaneously, and averages, and this value is saved as lock-out pulse peak value (NHS-top).
The generation of above-mentioned separated in synchronization threshold value is not limited to by sample counter and realizes, can also be disposed by artificial standard system according to sampling clock frequency and signal, is stored in the register then, so that call.In this case, above-mentioned horizontal separation threshold value obtains the unit can not comprise that the first horizontal separation threshold value obtains subelement, and comprise: the second horizontal separation threshold value obtains subelement, is used for from register obtaining to separate threshold value NHS according to the standard system of signal with the horizontal synchronization that the sampling clock frequency is disposed; Above-mentioned horizontal separation threshold value obtains the unit can not comprise that the first vertical separation threshold value obtains subelement, and comprise: the second vertical separation threshold value obtains subelement, is used for obtaining to separate threshold value NVS according to the standard system of signal with the vertical synchronization that the sampling clock frequency is disposed from register.
Vertical sync separator can obtain the signal standards standard by human configuration from register.Vertical sync separator can also be exported vertical synchronizing signal VS and give standard detector, picked up signal standard system from the standard detector with the CS ' that has certain delay.
The standard detector is used for vertical synchronizing signal VS and the CS ' that has certain delay according to vertical sync separator output, determines the standard system of signal.This standard system is transferred to phase-locked loop or above-mentioned vertical sync separator.
Above-mentioned vertical sync separator can further include: amending unit, be used for standard system according to signal, determine vertical sync period, and according to described vertical sync period described vertical synchronizing signal is obtained the vertical synchronizing signal that the unit obtains and revise, obtain revised vertical synchronizing signal VS.
Because the vertical synchronizing signal that obtains after the process digital filtering is handled and the vertical synchronizing signal of standard have certain delay, and pulsewidth does not meet standard yet, so need revise the vertical synchronizing signal that obtains after handling through digital filtering, the parameter that needs to revise mainly comprises: the delay of vertical synchronizing signal and pulsewidth.
When the delay of vertical synchronizing signal that delay is arranged is revised, can take following method:
By counter pixel clock is counted, its counting starting point is the rising edge that the vertical synchronizing signal of delay is arranged, and is designated as t0, and the count cycle is [Tvs-(t0-t1)], and wherein Tvs is by according to the definite vertical sync period of the standard system of signal; T1 is the rising edge of standard vertical synchronizing signal, the counting number be the count cycle divided by pixel clock, so just obtain the starting point of the following one-period of standard vertical synchronizing signal, Using such method just can be revised the delay of vertical synchronizing signal.
When the pulsewidth of vertical synchronizing signal that delay is arranged is revised, can take following method:
After the starting point of the following one-period that obtains above-mentioned standard vertical synchronizing signal, pulsewidth according to the signal of each standard system, pixel clock is counted, just can be revised, obtain the pulsewidth of revised vertical synchronizing signal the pulsewidth of vertical synchronizing signal that delay is arranged.
Above-mentioned vertical sync separator may further include: the window pulse signal generation unit, be used for standard system according to signal, horizontal-drive signal is counted, produced and the corresponding window pulse signal Coast of described standard system, also can be called the signal of windowing; And with described window pulse signal Coast with have the composite synchronizing signal CS ' of delay to offer phase-locked loop.
Phase-locked loop, be used for first signal and describedly have the composite synchronizing signal of delay to carry out phase demodulation, produce control voltage according to identified result, control generator produces secondary signal, according to the frequency dividing ratio of determining according to the standard system of signal described secondary signal is carried out frequency division, obtain the 3rd signal; Wherein said first signal is to separate threshold value NHS according to the horizontal synchronization that described vertical sync separator obtains, and described the 3rd signal postponed to handle obtaining; Described secondary signal is a pixel clock signal, and described the 3rd signal is a horizontal-drive signal.
The circuit structure of phase-locked loop as shown in Figure 6, it comprises: phase discriminator, charge pump, loop filter, voltage controlled oscillator, frequency divider and delay counter.
Delay counter is used for postponing to handle according to the 3rd signal of described horizontal synchronization separation threshold value to frequency divider output, obtains described first signal.The reset terminal of this delay counter links to each other with the output of frequency divider, and its carry end links to each other with the input of phase discriminator as the feedback of phase-locked loop, and its output links to each other with the input of phase discriminator.The horizontal synchronization that this delay counter is used for that described vertical sync separator is obtained separates threshold value as cycle period, and according to described cycle period, the signal of voltage controlled oscillator according to the employed clock frequency output of the composite synchronizing signal that is input to phase discriminator postponed to handle, obtain reference signal, the horizontal-drive signal of delay is promptly arranged.
Because the reset terminal of delay counter links to each other with the output of frequency divider, the working clock frequency of delay counter is the pixel clock frequency of frequency divider output like this, each saltus step of frequency divider needs a delay counter cycle period to arrive the input of phase discriminator, and the HS that obtains from PLL like this is exactly the real-time horizontal-drive signal in the vision signal.
Phase discriminator is used for described first signal and describedly has the composite synchronizing signal of delay to carry out phase demodulation; First signal that is about to delay counter output is as its input signal, and with described input signal and described vertical sync separator is resulting has the phase place of the composite synchronizing signal of delay to compare.
Because the CS signal is inconsistent with the frequency of row horizontal synchronization in the frequency of vertical blanking period (during comprising vertical synchronization) pulse, therefore the signal in as far as possible avoiding using during this, for this reason, above-mentioned phase discriminator, also further comprise: control sub unit, be used at vertical blanking period, according to the window pulse signal (also can be called the signal of windowing) that described vertical sync separator produced, the phase demodulation of the composite synchronizing signal that delay is arranged that first signal of described delay counter output and described vertical sync separator are exported is controlled, make identified result remain unchanged, charge pump is not charged, do not discharge, so that make voltage controlled oscillator keep original state, phase-locked loop is in (free-run) state of keeping.
Concrete disposition is as follows:
Phase discriminator with the count value fb of the composite synchronizing signal CS ' that certain delay is arranged, the window pulse signal Coast of vertical sync separator output and delay counter output as input, at vertical blanking period, utilize this window pulse signal Coast to determine the control window, and the composite synchronizing signal CS ' of described control window outside compared with the phase place of the fb of counter output, produce the switching signal that is used to control charge pump according to comparative result, this switching signal makes charge pump not charge, not discharge.When removing other of vertical blanking period, control Coast signal, make it invalid, the phase discriminator operate as normal, be about to the output of delay counter and described vertical sync separator is resulting has the phase place of the composite synchronizing signal of delay to compare, and produce the switching signal be used to control charge pump according to comparative result, phase-locked loop quick-recovery lock-out state soon again like this.
Charge pump is used for the identified result according to described phase discriminator, produces control voltage.Promptly the switch controlling signal according to this phase discriminator output discharges and recharges, and produces charge signal, i.e. voltage Vc.This charge pump also can be other control voltage generation unit.
Loop filter is used for the voltage Vc of charge pump output is carried out Filtering Processing, obtains voltage Vc ' comparatively stably.
Voltage controlled oscillator is used for controlling voltage-controlled oscillating circuit and producing the concussion frequency according to the voltage Vc ' that obtains after handling through loop filter, and promptly secondary signal is called pixel clock signal, is designated as PIX.
Frequency divider is used for the standard system according to the signal of standard detector output, determines frequency dividing ratio, and carries out frequency division according to the pixel clock signal PIX that described frequency dividing ratio is exported voltage controlled oscillator and handle, and obtains the 3rd signal, i.e. horizontal-drive signal HS.
Signal with the 864*625i@50Hz standard is an example, frequency divider determines that according to this signaling mode frequency dividing ratio is 864: 1, that is this line frequency is 15.625KHz, the pixel clock signal PIX that utilizes this frequency dividing ratio that voltage controlled oscillator is exported carries out frequency division to be handled, and obtains the horizontal-drive signal HS that frequency is 27MHz.
Still the signal with the 864*625i@50Hz standard is an example, the pixel clock frequency that obtains after handling by frequency divider is 27MHz, each saltus step of frequency divider clock cycle that all to need NHS clock frequency be 27MHz arrives the input of phase discriminator like this, and as seen the HS that obtains from PLL is exactly the real-time horizontal-drive signal of SOY signal.
Delay phase-locked loop is used for pixel clock signal is carried out the phase place adjustment, obtains the sampling clock that ADC needs.
Can not comprise the standard detector among above-mentioned first embodiment, correspondingly, vertical sync separator can not be according to the standard system of the signal of standard detector output, determine vertical sync period, and according to described vertical sync period the vertical sync information that obtains is revised, obtain revised vertical synchronizing signal VS '.And, vertical sync separator, it or not signal standards standard according to the output of standard detector, line synchronizing signal is counted, produce and the corresponding window pulse signal Coast of described standard system, but,, produce and the corresponding window pulse signal Coast of described standard system the line synchronizing signal counting according to the signal standards standard that disposes.
Above-mentioned first embodiment compares with aforesaid prior art two, latter's implementation method is simpler, for interleaved SD vision signal is arranged, because the interlace signal of shoulder blanking before and after having, need window pulse signal Coast to cooperate when therefore giving the PLL frequency division, influence prior art two disposal abilities; And this programme has been done very big improvement on the basis of prior art three, not only compensated delay, and can obtain the lock-out pulse peak value automatically, and obtain horizontal synchronization and separate threshold value and separate threshold value with vertical synchronization, thereby can automatic reconfiguration CS signal and extract the VS signal, reach the purpose of Automatic Anti-interference, have the anti-interference effect that to join, also need not loaded down with trivial details configuration register simultaneously.
In addition, vision signal for different systems, the value of horizontal synchronization parameter Δ 1 and vertical synchronization parameter Δ 2 can be set flexibly according to the standard system of signal, and according to horizontal synchronization parameter Δ 1 and vertical synchronization parameter, from composite synchronizing signal, isolate horizontal-drive signal and vertical synchronizing signal, thereby reach different anti-interference effects.
In addition, all devices of the foregoing description substantially all realize at chip internal, and utilize digital circuit to realize function, save chip area than analog circuit, so have bigger cost competitive advantage.
In a word, this technical scheme have anti-interference strong, can detect automatically, register is less and flexible configuration and realize low cost and other advantages.
Phase-locked loop among above-mentioned first embodiment also can adopt existing phase-locked loop, but only can eliminate the interference of input signal like this, can not compensate because of eliminating and disturb the delay that is brought.
Second embodiment of the invention provides another kind of synchronised clock extraction element, and its structure comprises clamper, composite sync separator, first filter, vertical sync separator, standard detector, phase-locked loop and delay phase-locked loop as shown in Figure 7.
The function of clamper and composite sync separator is identical with associated description among first embodiment, is not described in detail here.
First filter is used for the isolated composite synchronizing signal of composite sync separator is carried out Filtering Processing, and obtaining being eliminated has the composite synchronizing signal of delay after disturbing;
Can eliminate part interference effect in the composite synchronizing signal by this first filter, but the composite synchronizing signal that can cause exporting there is certain delay.
Vertical sync separator is used for vertical sync separator, is used for the composite synchronizing signal of described first filter output is carried out sample count, obtains composite synchronizing signal sample count value; And determined vertical synchronization separates threshold value with the sampling clock frequency to obtain standard system according to signal; And described vertical synchronization separated threshold value and described composite synchronizing signal sample count value compares, and obtain the vertical synchronizing signal of delay according to comparative result.
Described vertical sync separator comprises:
Sample counter, the composite synchronizing signal that is used for described first filter output is carried out sample count, obtains composite synchronizing signal sample count value;
The vertical separation threshold value obtains the unit, is used for the composite synchronizing signal sample count value that obtains by described sample counter, obtains the lock-out pulse peak value; According to the standard system and the sampling clock frequency of signal, obtain the vertical synchronization parameter; According to described lock-out pulse peak value and described vertical synchronization parameter, obtain vertical synchronization and separate threshold value.Specific implementation is identical with associated description among first embodiment, is not described in detail here; Perhaps, obtain to separate threshold value with the vertical synchronization that the sampling clock frequency is disposed according to the standard system of signal;
Vertical synchronizing signal obtains the unit, is used for described vertical synchronization separation threshold value and described composite synchronizing signal sample count value are compared, and obtains the vertical synchronizing signal of delay according to comparative result.
The standard detector is used for determining the standard system of signal according to isolated vertical synchronizing signal of vertical sync separator and the composite synchronizing signal that has certain delay; Correspondingly, described vertical sync separator comprises: amending unit, be used for standard system according to signal, and determine vertical sync period, and the vertical sync information that obtains is revised according to described vertical sync period, obtain revised vertical synchronizing signal.Specific implementation is identical with associated description in the foregoing description, is not described in detail here.
Described vertical sync separator can also comprise: the window pulse signal generation unit, be used for standard system according to signal, and produce and the corresponding window pulse signal of described standard system, send this window pulse signal to phase-locked loop.
Phase-locked loop, be used for first signal and describedly have the composite synchronizing signal of delay to carry out phase demodulation, produce control voltage according to identified result, control generator produces secondary signal, according to the frequency dividing ratio of determining according to the standard system of signal described secondary signal is carried out frequency division, obtain the 3rd signal; Wherein, described first signal utilizes filter that described the 3rd signal that is input to described filter is postponed to handle and obtains according to the employed clock frequency of composite synchronizing signal that is input to phase discriminator; Described secondary signal is a pixel clock signal, and described the 3rd signal is a horizontal-drive signal.
The structure of described phase-locked loop comprises phase discriminator, charge pump, loop filter, voltage controlled oscillator, frequency divider and second filter as shown in Figure 8.
Phase discriminator is used for described first signal and describedly has the composite synchronizing signal of delay to carry out phase demodulation;
Charge pump is used for the identified result according to described phase discriminator, produces control voltage; This charge pump can also be other control voltage generation unit.
Loop filter is used for the control voltage of charge pump output is carried out Filtering Processing, obtains voltage comparatively stably.
Voltage controlled oscillator is used for producing described secondary signal according to described control voltage.
Frequency divider is used for described secondary signal is carried out frequency division according to the frequency dividing ratio of determining according to the standard system of signal, obtains described the 3rd signal.
Second filter is used for according to the employed clock frequency of composite synchronizing signal that is input to phase discriminator, and described the 3rd signal that is input to described second filter is postponed to handle, and obtains described first signal.
Above-mentioned phase discriminator, can further include: control sub unit, be used at vertical blanking period, according to the window pulse signal that described vertical sync separator produced, the phase demodulation of the composite synchronizing signal that delay is arranged that described first signal of described second filter output and described vertical sync separator are exported is controlled, make identified result remain unchanged, so that the control voltage that produces according to this identified result remains unchanged.
The concrete disposition of above-mentioned charge pump, loop filter, voltage controlled oscillator, frequency divider is identical with associated description among first embodiment, is not described in detail here.
The function of delay phase-locked loop is identical with associated description among first embodiment, is not described in detail here.
Can not comprise the standard detector among above-mentioned second embodiment, correspondingly, vertical sync separator can not be according to the standard system of the signal of standard detector output, determine vertical sync period, and the vertical sync information that obtains is revised according to described vertical sync period, obtain revised vertical synchronizing signal VS ', but, signal standards standard according to configuration, determine vertical sync period, and according to described vertical sync period the vertical sync information that obtains is revised, obtain revised vertical synchronizing signal VS '.And, vertical sync separator, it or not signal standards standard according to the output of standard detector, line synchronizing signal is counted, produce and the corresponding window pulse signal Coast of described standard system, but,, produce and the corresponding window pulse signal Coast of described standard system the line synchronizing signal counting according to the signal standards standard that disposes.
Above-mentioned second embodiment can eliminate the impulse disturbances that may exist from the composite synchronizing signal that vision signal is obtained, and can compensate in the synchronizing signal because of eliminating the time delay that impulse disturbances is brought.
Phase-locked loop among above-mentioned second embodiment also can adopt existing phase-locked loop, but only can eliminate the interference of input signal like this, can not compensate because of eliminating and disturb the delay that is brought.
Third embodiment of the invention provides a kind of synchronised clock extracting method, and this synchronised clock extracting method is corresponding with first embodiment, comprises following content:
From the interference signal of input, recover flip-flop, obtain comprising the described interference signal that recovers flip-flop.
The interference signal of input and the discrete level of setting are compared, and, obtain to disturb composite synchronizing signal according to comparative result.
To disturbing composite synchronizing signal to carry out sample count, obtain disturbing composite synchronizing signal sample count value, and obtain horizontal synchronization separation threshold value;
When obtaining horizontal synchronization separation threshold value, can obtain the lock-out pulse peak value according to disturbing composite synchronizing signal sample count value; According to the standard system and the sampling clock frequency of signal, obtain the horizontal synchronization parameter; And, obtain horizontal synchronization and separate threshold value according to described lock-out pulse peak value and described horizontal synchronization parameter.Specific implementation is identical with associated description among first embodiment, is not described in detail here.Also can from register, obtain to separate threshold value with the horizontal synchronization that the sampling clock frequency is disposed according to the standard system of signal.
Described horizontal synchronization is separated threshold value to be compared with disturbing composite synchronizing signal sample count value, according to comparative result, be eliminated the composite synchronizing signal of delay is arranged after disturbing and (determine that comparative result is when disturbing composite synchronizing signal sample count value to be higher than horizontal synchronization to separate threshold value, output signal, promptly being eliminated has the composite synchronizing signal of delay after disturbing.), it is corresponding that the delay of the described composite synchronizing signal that delay arranged and described horizontal synchronization separate threshold value.
Above-mentioned synchronised clock extracting method can further include:
Determined vertical synchronization separates threshold value with the sampling clock frequency according to the standard system of signal in acquisition; Described vertical synchronization is separated threshold value and interference composite synchronizing signal sample count value is compared, and definite comparative result is when disturbing composite synchronizing signal sample count value to be higher than vertical synchronization separation threshold value, output signal promptly obtains the vertical synchronizing signal of delay.
When obtaining vertical synchronization separation threshold value, can obtain the lock-out pulse peak value according to disturbing composite synchronizing signal sample count value; According to the standard system and the sampling clock frequency of signal, obtain the vertical synchronization parameter; According to described lock-out pulse peak value and described vertical synchronization parameter, obtain vertical synchronization and separate threshold value.Specific implementation is identical with associated description among first embodiment, is not described in detail here.Also can obtain to separate threshold value with the vertical synchronization that the sampling clock frequency is disposed according to the standard system of signal.
Above-mentioned synchronised clock extracting method can also be determined vertical sync period according to the standard system of signal, and according to described vertical sync period the vertical synchronizing signal that vertical synchronizing signal obtains the unit acquisition is revised, and obtains revised vertical synchronizing signal.Specific implementation is identical with associated description in the foregoing description, is not described in detail here.
By said process, can eliminate the interference in the input signal, and obtain revised vertical synchronizing signal.But when erasure signal disturbs, can bring certain delay, in order to eliminate this delay, third embodiment of the invention can further include following content:
To first signal with describedly have the composite synchronizing signal of delay to carry out phase demodulation, produce control voltage according to identified result, control generator produces secondary signal, according to the frequency dividing ratio of determining according to the standard system of signal described secondary signal is carried out frequency division, obtains the 3rd signal; Wherein, above-mentioned first signal separates threshold value according to described horizontal synchronization and described the 3rd signal is postponed to handle obtains; Above-mentioned secondary signal is a pixel clock signal, and above-mentioned the 3rd signal is a horizontal-drive signal.
Described the 3rd signal is postponed to handle when obtaining above-mentioned first signal separating threshold value according to described horizontal synchronization, can be according to the employed clock frequency of the composite synchronizing signal that is input to phase discriminator, utilize counter, signal to enter counter is counted, determine whether count value arrives the horizontal synchronization that is obtained and separate threshold value, if arrive, then export reference signal, and restart counting; Otherwise, continue to determine whether count value arrives the horizontal synchronization that is obtained and separate threshold value.
Third embodiment of the invention can also produce and the corresponding window pulse signal of described standard system according to the standard system of signal; At vertical blanking period, according to the window pulse signal that is produced, to described first signal and resultingly have the phase demodulation of the composite synchronizing signal of delay to control, make identified result remain unchanged, so that the control voltage that produces according to this identified result remains unchanged.
Third embodiment of the invention can also be carried out the phase place adjustment to above-mentioned pixel clock signal.
The standard system of above-mentioned signal can be determined according to described vertical synchronizing signal and the described composite synchronizing signal that delay arranged.
Fourth embodiment of the invention provides another kind of synchronised clock extracting method, and this synchronised clock extracting method is corresponding with second embodiment, comprises following content:
From the interference signal of input, recover flip-flop, obtain comprising the described interference signal that recovers flip-flop;
Described recovered the interference signal of flip-flop and the discrete level of setting compares resulting comprising, and, obtain to disturb composite synchronizing signal according to comparative result.
Interference composite synchronizing signal to input is carried out Filtering Processing, obtains the composite synchronizing signal of delay;
There is the composite synchronizing signal of delay to carry out sample count to described, obtains the composite synchronizing signal sample count value of delay; And, obtain vertical synchronization and separate threshold value; Described vertical synchronization is separated threshold value compare with described composite synchronizing signal sample count value, determine that comparative result is when disturbing composite synchronizing signal sample count value to be higher than vertical synchronization separation threshold value, output signal promptly obtains the vertical synchronizing signal of delay.
When obtaining vertical synchronization separation threshold value, can obtain the lock-out pulse peak value according to resulting composite synchronizing signal sample count value; According to the standard system and the sampling clock frequency of signal, obtain the vertical synchronization parameter; According to described lock-out pulse peak value and described vertical synchronization parameter, obtain vertical synchronization and separate threshold value; Also can obtain to separate threshold value with the vertical synchronization that the sampling clock frequency is disposed according to the standard system of signal.Specific implementation is identical with associated description among first embodiment, is not described in detail here.
The 4th embodiment can also determine the standard system of signal further according to described vertical synchronizing signal and the composite synchronizing signal that delay is arranged; According to the standard system of signal, determine vertical sync period, and the vertical synchronizing signal that obtains is revised according to described vertical sync period, obtain revised vertical synchronizing signal.
By said process, can eliminate the interference in the input signal, and obtain revised vertical synchronizing signal.But when erasure signal disturbs, can bring certain delay, in order to eliminate this delay, fourth embodiment of the invention can further include following content:
To first signal with describedly have the composite synchronizing signal of delay to carry out phase demodulation, produce control voltage according to identified result, control generator produces secondary signal, according to the frequency dividing ratio of determining according to the standard system of signal above-mentioned secondary signal is carried out frequency division, obtains the 3rd signal; Wherein, above-mentioned first signal utilizes filter that the 3rd signal that is input to described filter is postponed to handle and obtains according to the employed clock frequency of the composite synchronizing signal of phase discrimination processing; Above-mentioned secondary signal is a pixel clock signal, and above-mentioned the 3rd signal is a horizontal-drive signal.
Fourth embodiment of the invention can also produce and the corresponding window pulse signal of described standard system according to the standard system of signal; At vertical blanking period, according to described window pulse signal, described first signal that Filtering Processing is obtained and describedly have the phase demodulation of the composite synchronizing signal of delay to control makes identified result remain unchanged, so that the control voltage that produces according to this identified result remains unchanged.
Fourth embodiment of the invention can also be carried out the phase place adjustment to described pixel clock signal.
First embodiment that provides by the invention described above and the 3rd embodiment as can be seen, determined horizontal synchronization separates threshold value to the embodiment of the invention with the sampling clock frequency by obtaining standard system according to signal; Horizontal synchronization is separated threshold value compare with disturbing composite synchronizing signal sample count value, according to comparative result, the composite synchronizing signal that delay is arranged after disturbing of being eliminated, the impulse disturbances that may exist in can erasure signal.
In addition, it can also be seen that by first embodiment provided by the invention and the 3rd embodiment, by to first signal with describedly have the composite synchronizing signal of delay to carry out phase demodulation, produce control voltage according to identified result, control generator produces secondary signal, according to the frequency dividing ratio of determining according to the standard system of signal described secondary signal is carried out frequency division, obtain the 3rd signal; Wherein first signal separates threshold value according to described horizontal synchronization and described the 3rd signal is postponed to handle obtains; Secondary signal is a pixel clock signal; The 3rd signal is a horizontal-drive signal, can compensate in the synchronizing signal because of eliminating the time delay that impulse disturbances is brought.
Second embodiment that provides by the invention described above and the 4th embodiment as can be seen, the embodiment of the invention obtains the composite synchronizing signal of delay by the interference composite synchronizing signal of input is carried out Filtering Processing; To first signal with describedly have the composite synchronizing signal of delay to carry out phase demodulation, produce control voltage according to identified result, control generator produces secondary signal, according to the frequency dividing ratio of determining according to the standard system of signal described secondary signal is carried out frequency division, obtains the 3rd signal; This first signal utilizes filter that above-mentioned the 3rd signal that is input to described filter is postponed to handle and obtains according to the employed clock frequency of the composite synchronizing signal of phase discrimination processing; Secondary signal is a pixel clock signal; The 3rd signal is a horizontal-drive signal, the impulse disturbances that may exist in can erasure signal, and the impulse disturbances that may exist in can erasure signal.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (13)
1. a synchronised clock extraction element is characterized in that, described synchronised clock extraction element comprises:
First filter is used for the interference signal of input is carried out Filtering Processing, and the composite synchronizing signal of delay is arranged after the interference that is eliminated;
Phase-locked loop, be used for first signal and describedly have the composite synchronizing signal of delay to carry out phase demodulation, produce control voltage according to identified result, control generator produces secondary signal, according to the frequency dividing ratio of determining according to the standard system of signal described secondary signal is carried out frequency division, obtain the 3rd signal;
Described first signal utilizes filter that described the 3rd signal that is input to described filter is postponed to handle and obtains according to the employed clock frequency of composite synchronizing signal that is input to phase discriminator;
Described secondary signal is a pixel clock signal, and described the 3rd signal is a horizontal-drive signal.
2. synchronised clock extraction element as claimed in claim 1 is characterized in that, described phase-locked loop comprises:
Phase discriminator is used for described first signal and describedly has the composite synchronizing signal of delay to carry out phase demodulation;
Control voltage generation unit is used for the identified result according to described phase discriminator, produces control voltage;
Voltage controlled oscillator is used for producing described secondary signal according to described control voltage;
Frequency divider is used for described secondary signal is carried out frequency division according to the frequency dividing ratio of determining according to the standard system of signal, obtains described the 3rd signal;
Second filter is used for according to the employed clock frequency of composite synchronizing signal that is input to phase discriminator, and described the 3rd signal that is input to described second filter is postponed to handle, and obtains described first signal.
3. synchronised clock extraction element as claimed in claim 1 or 2 is characterized in that, described synchronised clock extraction element also comprises:
Vertical sync separator is used for the composite synchronizing signal of described first filter output is carried out sample count, obtains composite synchronizing signal sample count value; And determined vertical synchronization separates threshold value with the sampling clock frequency to obtain standard system according to signal; And described vertical synchronization separated threshold value and described composite synchronizing signal sample count value compares, and obtain the vertical synchronizing signal of delay according to comparative result.
4. synchronised clock extraction element as claimed in claim 3 is characterized in that,
Described vertical sync separator comprises:
Sample counter is used for the composite synchronizing signal of described first filter output is carried out sample count, obtains composite synchronizing signal sample count value;
The first vertical separation threshold value obtains the unit, is used for the composite synchronizing signal sample count value that obtains by described sample counter, obtains the lock-out pulse peak value; According to the standard system and the sampling clock frequency of signal, obtain the vertical synchronization parameter; According to described lock-out pulse peak value and described vertical synchronization parameter, obtain vertical synchronization and separate threshold value;
Vertical synchronizing signal obtains the unit, is used for described vertical synchronization separation threshold value and described composite synchronizing signal sample count value are compared, and obtains the vertical synchronizing signal of delay according to comparative result;
Perhaps,
Described vertical sync separator comprises:
Sample counter is used for the composite synchronizing signal of described first filter output is carried out sample count, obtains composite synchronizing signal sample count value;
The second vertical separation threshold value obtains the unit, and the standard system that is used to obtain according to signal separates threshold value with the vertical synchronization that the sampling clock frequency is disposed;
Vertical synchronizing signal obtains the unit, is used for described vertical synchronization separation threshold value and described composite synchronizing signal sample count value are compared, and obtains the vertical synchronizing signal of delay according to comparative result.
5. synchronised clock extraction element as claimed in claim 4 is characterized in that,
Described vertical sync separator also comprises: the window pulse signal generation unit, be used for standard system according to signal, and produce and the corresponding window pulse signal of described standard system;
Described phase discriminator, also comprise: control sub unit, be used at vertical blanking period, according to the window pulse signal that described vertical sync separator produced, the phase demodulation of the composite synchronizing signal that delay is arranged that described first signal of described second filter output and described vertical sync separator are exported is controlled, and makes identified result remain unchanged.
6. synchronised clock extraction element as claimed in claim 3 is characterized in that,
Described synchronised clock extraction element also comprises: the standard detector is used for determining the standard system of signal according to isolated vertical synchronizing signal of described vertical sync separator and the described composite synchronizing signal that delay is arranged;
Described vertical sync separator also comprises: amending unit, be used for standard system according to signal, and determine vertical sync period, and the vertical synchronizing signal that obtains is revised according to described vertical sync period, obtain revised vertical synchronizing signal.
7. synchronised clock extraction element as claimed in claim 1 is characterized in that, described synchronised clock extraction element also comprises:
Clamper is used for recovering flip-flop from the interference signal of input, and will comprise the described interference signal output that recovers flip-flop;
The composite sync separator is used for the interference signal of described clamper input and the discrete level of setting are compared, and according to comparative result, obtains to disturb composite synchronizing signal, and described interference composite synchronizing signal is flowed to described first filter.
8. a synchronised clock extracting method is characterized in that, described synchronised clock extracting method comprises:
Interference composite synchronizing signal to input is carried out Filtering Processing, and the composite synchronizing signal of delay is arranged after the interference that is eliminated;
To first signal with describedly have the composite synchronizing signal of delay to carry out phase demodulation, produce control voltage according to identified result, control generator produces secondary signal, according to the frequency dividing ratio of determining according to the standard system of signal described secondary signal is carried out frequency division, obtains the 3rd signal;
Described first signal utilizes filter that described the 3rd signal that is input to described filter is postponed to handle and obtains according to the employed clock frequency of the composite synchronizing signal of phase discrimination processing;
Described secondary signal is a pixel clock signal, and described the 3rd signal is a horizontal-drive signal.
9. synchronised clock extracting method as claimed in claim 8 is characterized in that, described synchronised clock extracting method also comprises:
There is the composite synchronizing signal of delay to carry out sample count to described, obtains the composite synchronizing signal sample count value of delay; And, obtain vertical synchronization and separate threshold value; And described vertical synchronization separated threshold value and described composite synchronizing signal sample count value compares, and obtain the vertical synchronizing signal of delay according to comparative result.
10. synchronised clock extracting method as claimed in claim 9 is characterized in that, described acquisition vertical synchronization separates threshold value, comprising:
According to resulting composite synchronizing signal sample count value, obtain the lock-out pulse peak value; According to the standard system and the sampling clock frequency of signal, obtain the vertical synchronization parameter; According to described lock-out pulse peak value and described vertical synchronization parameter, obtain vertical synchronization and separate threshold value; Perhaps,
Acquisition separates threshold value according to the standard system of signal with the vertical synchronization that the sampling clock frequency is disposed.
11. synchronised clock extracting method as claimed in claim 10 is characterized in that, described synchronised clock extracting method also comprises:
According to the standard system of signal, produce and the corresponding window pulse signal of described standard system;
At vertical blanking period, according to described window pulse signal, described first signal that Filtering Processing is obtained and describedly have the phase demodulation of the composite synchronizing signal of delay to control makes identified result remain unchanged.
12., it is characterized in that described synchronised clock extracting method also comprises as claim 9,10 or 11 described synchronised clock extracting methods:
According to described vertical synchronizing signal and the composite synchronizing signal that delay is arranged, determine the standard system of signal;
According to the standard system of signal, determine vertical sync period, and the vertical synchronizing signal that obtains is revised according to described vertical sync period, obtain revised vertical synchronizing signal.
13. synchronised clock extracting method as claimed in claim 8 is characterized in that, described synchronised clock extracting method also comprises:
From the interference signal of input, recover flip-flop, obtain comprising the described interference signal that recovers flip-flop;
Described recovered the interference signal of flip-flop and the discrete level of setting compares resulting comprising, and, obtain to disturb composite synchronizing signal according to comparative result.
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