CN1158869C

CN1158869C - Separator of HDTV line synchronization signal

Info

Publication number: CN1158869C
Application number: CNB011288817A
Authority: CN
Inventors: 田朝勇
Original assignee: Sichuan Changhong Electric Co Ltd
Current assignee: Sichuan Changhong Electric Co Ltd
Priority date: 2001-09-21
Filing date: 2001-09-21
Publication date: 2004-07-21
Anticipated expiration: 2021-09-21
Also published as: CN1343070A

Abstract

The present invention relates to a device which can separate trip synchronizing signals from HDTV composite synchronizing signals. The present invention comprises a control circuit and a monostable trigger circuit, wherein the input of the control circuit is a composite sync signal (vi), the input of the monostable trigger circuit is a composite sync signal (vi), the output of t he monostable trigger circuit is a control signal, and the control signal is the control input of the control circuit. The monostable time of the monostable trigger circuit is 3/4 line period, and a triggering mode is falling edge triggering. The monostable trigger has the performance of no triggering again, so the device not only can eliminate the double-frequency line pulse in the field synchronization period, but also can eliminate the interference pulse in any front 3/4 line period time, and therefore, the device can lock line synchronization pulse.

Description

HDTV line synchronizing signal separator

Technical field

The present invention relates to a kind of HDTV line synchronizing signal separator, specifically, relate to a kind of device that from the HDTV composite synchronizing signal, to isolate line synchronizing signal that has.

Background technology

At present, the high definition video signal of outputs such as HDTV receiver, set-top box has H/V-RGB signal (field sync signal, tristimulus signals at once) and two kinds of forms of Y/Pr/Pb signal (being luminance signal, color difference signal) usually, and HDTV display (HDTV Ready) also correspondingly has this two kinds of input interfaces.To the Y/Pr/Pb input, the HDTV display needs to separate trip, field sync signal from one of these three kinds of signals, offers circuit such as vision signal processing, row-field scanning, screen display.For obtaining stable high quality graphic, require isolated row, the necessary non-jitter of field sync signal, it is little to delay time, and row, field synchronization split circuit that present simulated television is adopted, only limit to about line frequency 15kHz, for the line frequency signal of HDTV up to 33.75kHz or 45kHz, the capable synchronizing separator circuit that obvious traditional tv is adopted can't be applied on the HDTV TV; External HDTV TV adopts phase-locked loop circuit more, and circuit is comparatively complicated, and cost is also higher.

Summary of the invention

The object of the present invention is to provide a kind of circuit simple, the HDTV television line synchronization signal separation device that cost is low is separated line synchronizing signal from composite synchronizing signal, and obtains high-quality, stable image.

In order to solve the problems of the technologies described above, HDTV line synchronizing signal separator of the present invention comprises:

A control circuit, it is input as composite synchronizing signal;

A single-shot trigger circuit, it is input as composite synchronizing signal, is output as control signal, and this control signal is the control input of described control circuit;

The monostable time set of single-shot trigger circuit is 3/4 line period, and triggering mode is set at trailing edge and triggers;

When the line synchronizing signal pulse trailing edge in the composite synchronizing signal arrived, single-shot trigger circuit was triggered, and outputs a control signal in the control circuit, made it be in off-state to the input composite synchronizing signal;

When single-shot trigger circuit through 3/4 line period after the time, its output control signal counter-rotating, control circuit is in conducting state to the input composite synchronizing signal, can pass through control circuit in next line synchronizing signal pulse, its trailing edge triggers single-shot trigger circuit again, control circuit is disconnected, and so circulation is about to line synchronizing signal and separates from composite synchronizing signal

Because of monostable flipflop has the performance that can not heavily trigger,, can eliminate the disturbing pulse in any preceding 3/4 line period time again, thereby horizontal synchronizing pulse can be locked so this device both can have been eliminated 2 times of line frequency pulses during the field synchronization.When device powers on, even mistake is locked in the wrong pulse, also can be after this field synchronization or next line pulse when arriving, be automatically locked in the correct horizontal pulse, thereby from composite synchronizing signal, isolate correct, stable horizontal synchronizing pulse, guarantee image stabilization.

Description of drawings

Below in conjunction with the drawings and specific embodiments apparatus of the present invention are described in further detail.

Fig. 1 in existing simulated television or the HDTV TV with the electrical schematic diagram of separated in synchronization relevant portion;

Fig. 2 is the circuit working schematic diagram of one embodiment of the present invention;

Fig. 3 is the working waveform figure of circuit shown in Figure 2;

Fig. 4 is the self-locking working waveform figure after circuit shown in Figure 2 misses synchronously.

Embodiment

Comprise composite sync split circuit 1, row synchronizing separator circuit 2, field synchronization split circuit 3, a row oscillating circuit 4, video processing circuits 5 and display device 6 at the circuit block diagram shown in Fig. 1.The analog composite video signal (CVBS) of input or HDTV luminance signal (Y) are isolated composite synchronizing signal Vi through composite sync split circuit 1 earlier, and then from composite synchronizing signal, separate trip, field sync signal through row, field

synchronization split circuit

2,3 respectively, isolated capable field sync signal is used for synchronization line field oscillating circuit 4 on the one hand, to produce and the synchronous stable row-field scanning frequency of picture signal, be used for video processing circuit 5 on the other hand and do synchronized clamping, amplification synchronously etc.Obviously, asynchronous or have a disturbing pulse as isolated row, field sync signal and picture signal, then row-field scanning and picture intelligence just can not be synchronous, thereby the image that is reappeared will rock, instability.Wherein capable synchronizing separator circuit 2 parts just involved in the present invention.

Fig. 2 is the circuit theory diagrams of a kind of execution mode of apparatus of the present invention.This device circuit comprises single-shot trigger circuit of being made up of monostable flipflop 201, resistance R t, capacitor C t and the control circuit of being made up of AND circuit 202.Wherein, the model of monostable flipflop 201 is 74HCT4538, and resistance R t and capacitor C t are timing element, timing T=0.7Rt * Ct=3/4 line period time; Rt is connected between 2 pin and power supply VCC of monostable flipflop 201, and Ct is connected between 1 pin and 2 pin of monostable flipflop 201; 1 pin ground connection of monostable flipflop 201,3 pin meet power supply VCC; 6 pin of monostable flipflop 201 are positive output end Q, link to each other with its triggering level control end 4, thereby make monostable flipflop 201 work in pulse trailing edge triggering mode, and have the characteristic that can not heavily trigger; 7 pin of monostable flipflop 201 are negative output terminal Q, import AND circuit 202 with composite synchronizing signal Vi, and the two signal of being exported behind logical AND is required line synchronizing signal Vo.

The course of work of this device circuit is as follows:

When the line synchronizing signal pulse among the composite synchronizing signal Vi arrived, its trailing edge triggered monostable flipflop 201, and output Q is output as low level, thereby will turn-off with door 202, and composite synchronizing signal Vi can not be by exporting with door 202;

When single-shot trigger circuit 201 through 3/4 line period after the time, its output signal is reversed, output Q is output as high level, thus will with door 202 conductings, composite synchronizing signal Vi by with door 202 output, when next line synchronizing signal pulse arrives, can be by exporting with door 202, its trailing edge triggers monostable flipflop 201 again, will turn-off with door 202, so circulation is about to line synchronizing signal V.From composite synchronizing signal Vi, separate.

Fig. 3 is the working waveform figure of circuit shown in Figure 2.Shown in the oscillogram, the partial pulse during the field synchronization of having drawn, wherein

pulse

1,2,3,4 is horizontal pulse, 2 ', 3 ' be 2 times of line frequency pulses during the field synchronization.Because being designed to trailing edge, triggers by monostable flipflop 201, so in the t1 moment of pulse 1, monostable flipflop 201 anodes output Q is a high level, behind time T=0.7Rt * Ct=3/4Th line period, before pulse 2 arrived, monostable flipflop 201 anode Q got back to low level state; In the t2 moment of pulse 2, monostable flipflop 201 is triggered once more, its anode Q exports high level again, and pulse 2 ' t3 when arriving constantly, because the time 1/2Th＜T=3/4Th that is experienced, the output of monostable flipflop 201 anodes still is high level, the triggering level control end also is a high level, thereby monostable flipflop 201 can not by pulse 2 ' trailing edge trigger (promptly can not heavily trigger), again through behind the 1/4Th before pulse 3 arrives, monostable flipflop 201 anode Q get back to low level state again, and in the t4 moment of pulse 3, monostable flipflop 201 is triggered again again.Like this, after monostable flipflop 201 negative terminals output was carried out " logical AND " with composite synchronizing pulse, horizontal synchronizing

pulse

1,2,3 was just separated, 2 times of line frequency pulses 2 ' wait then conductively-closed to fall.By that analogy.Obviously, to other disturbing pulse in 3/4 cycle before the horizontal synchronizing pulse, this circuit has shielding action too.

Fig. 4 is the self-locking working waveform figure after device circuit shown in Figure 2 misses synchronously, this figure has drawn and has started shooting moment when powering in case be synchronized with in 2 times of line frequency pulses by mistake, then when this field synchronization finishes, also can automatically become locked to the working waveform figure in the correct horizontal synchronizing pulse.Wherein

pulse

1,2,3 ... n is horizontal synchronizing pulse, 2 ', 3 ' ... m ' is 2 times of line frequency pulses or other disturbing pulse.When just pulse 2 and 2 ' between when powering on, then pulse 2 ' t1 constantly, monostable flipflop 201 is triggered, its anode output high level, according to aforementioned principles, up to pulse m ', this circuit will be exported the pulse at 2 times of line frequency places, cause line phase incorrect, but finish when horizontal pulse n arrives in field synchronization, because 1 line period of pulse m ' and n interval so can correctly be triggered at the trailing edge of pulse n, is from then on exported correct horizontal pulse and is kept lock-out state.Owing to is visual blanking interval during the field synchronization, thus only during this line phase depart from the unlikely image stabilization that influences.Obviously, as when powering on synchronously on the disturbing pulse during the non-field synchronization, then also can after the pulse of 1 mistake of output, can automatically become locked in the horizontal pulse, can not influence image stabilization yet.

As seen, 2 times of line frequency pulses during this device maskable HDTV field synchronization, can filter the disturbing pulse that occurs in any preceding 3/4 line period effectively, when even device powers on, synchronously in 2 times of line frequency pulses, when this field synchronization finishes, also can automatically become locked to immediately in the correct horizontal synchronizing pulse, line synchronizing signal pulse Vo is isolated from composite synchronizing signal Vi like this.

Claims

1. a HDTV line synchronizing signal separator is characterized in that: comprise

A control circuit, it is input as composite synchronizing signal (Vi);

A single-shot trigger circuit, it is input as composite synchronizing signal (Vi), is output as control signal, and this control signal is the control input of described control circuit;

When line synchronizing signal pulse (Vo) trailing edge in the composite synchronizing signal arrived, single-shot trigger circuit was triggered, and outputs a control signal in the control circuit, made it be in off-state to input composite synchronizing signal (Vi);

When single-shot trigger circuit through 3/4 line period after the time, its output control signal counter-rotating, control circuit is in conducting state to the input composite synchronizing signal, can pass through control circuit in next line synchronizing signal pulse (Vi), its trailing edge triggers single-shot trigger circuit again, control circuit is disconnected, and so circulation is about to line synchronizing signal and separates from composite synchronizing signal.

2. line synchronizing signal separator according to claim 1 is characterized in that:

Described single-shot trigger circuit is made up of monostable flipflop (201), resistance (Rt), electric capacity (Ct), and described control circuit is made up of AND circuit (202);

Resistance (Rt) and electric capacity (Ct) are timing element, timing T=0.7Rt * Ct=3/4 line period time; Rt is connected between 2 pin and power supply (VCC) of monostable flipflop (201), and Ct is connected between 1 pin and 2 pin of monostable flipflop (201); 1 pin ground connection of monostable flipflop (201), 3 pin connect power supply (VCC), and 5 pin are composite synchronizing signal (Vi) input;

6 pin of monostable flipflop (201) are positive output end (Q), link to each other with its triggering level control end 4, thereby make monostable flipflop (201) work in pulse trailing edge triggering mode, and have the characteristic that can not heavily trigger.7 pin of monostable flipflop (201) are negative output terminal (Q), import AND circuit (202) with composite synchronizing signal (Vi), and the two signal of being exported behind logical AND is required line synchronizing signal (Vo).