CN113810893B - Device and method for clock signal recovery and NFC chip - Google Patents
Device and method for clock signal recovery and NFC chip Download PDFInfo
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- CN113810893B CN113810893B CN202111360798.7A CN202111360798A CN113810893B CN 113810893 B CN113810893 B CN 113810893B CN 202111360798 A CN202111360798 A CN 202111360798A CN 113810893 B CN113810893 B CN 113810893B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W4/00—Services specially adapted for wireless communication networks; Facilities therefor
- H04W4/80—Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
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- H04W—WIRELESS COMMUNICATION NETWORKS
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Abstract
The application relates to the technical field of wireless communication and discloses a device for clock signal recovery. The method comprises the following steps: the differential input signal module is used for acquiring the antenna voltage and generating a differential input signal according to the antenna voltage; the first end of the pre-amplification module is electrically connected with one end of the differential input signal module; the pre-amplification module is used for amplifying the differential input signal; one end of the comparator is electrically connected with the second end of the pre-amplification module, and the comparator is used for comparing the amplified differential input signals to obtain a clock signal; the first end of the negative feedback module is electrically connected with the other end of the differential input signal module, the second end of the negative feedback module is electrically connected with the third end of the pre-amplification module, and the third end of the negative feedback module is electrically connected with the other end of the comparator; the negative feedback module is used for adjusting the amplification parameters of the differential input signals according to the clock signals to recover the clock signals. The application also discloses a method for clock signal recovery and an NFC chip.
Description
Technical Field
The present application relates to the field of wireless communication technologies, and for example, to an apparatus and a method for clock signal recovery, and an NFC chip.
Background
At present, with the increasingly wide application of wireless communication chips, especially the popularization of consumer products such as small-size bracelets and watches with wireless communication chip functions, the performance requirements of terminal systems on wireless communication chips are also increasing, wherein the receiving sensitivity is one of the most important indexes of wireless communication chips. Among the factors affecting the reception sensitivity index, the recovery of the clock signal is a major component.
In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:
in the prior art, clock signal recovery is realized by amplifying differential input signals and comparing the amplified differential input signals. However, such a clock signal recovery method cannot achieve phase synchronization between the differential input signal and the clock signal.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview nor is intended to identify key/critical elements or to delineate the scope of such embodiments but rather as a prelude to the more detailed description that is presented later.
The embodiment of the disclosure provides a device and a method for clock signal recovery and an NFC chip, so as to solve the problem of phase synchronization of a clock signal and a differential input signal.
In some embodiments, the means for clock signal recovery comprises: the differential input signal module is used for acquiring antenna voltage and generating a differential input signal according to the antenna voltage; the first end of the pre-amplification module is electrically connected with one end of the differential input signal module; the pre-amplification module is used for amplifying the differential input signal; one end of the comparator is electrically connected with the second end of the pre-amplification module, and the comparator is used for comparing the amplified differential input signals to obtain a clock signal; a first end of the negative feedback module is electrically connected with the other end of the differential input signal module, a second end of the negative feedback module is electrically connected with a third end of the pre-amplification module, and the third end of the negative feedback module is electrically connected with the other end of the comparator; the negative feedback module is used for adjusting the amplification parameters of the differential input signals according to the clock signals to recover the clock signals.
In some embodiments, the method for clock signal recovery comprises: acquiring an antenna voltage, and generating a differential input signal according to the antenna voltage; amplifying the differential input signal to obtain an amplified differential input signal; comparing the amplified differential input signals to obtain a clock signal; and adjusting the amplification parameters of the differential input signals according to the clock signals to realize the recovery of the clock signals.
In some embodiments, the NFC chip comprises an apparatus for clock signal recovery as described above.
The device and method for clock signal recovery and the NFC chip provided by the embodiment of the disclosure can achieve the following technical effects: acquiring an antenna voltage through a differential input signal module and generating a differential input signal according to the antenna voltage; the pre-amplification module amplifies the differential input signal; the comparator compares the amplified differential input signals to obtain a clock signal; the negative feedback module adjusts the amplification parameters of the differential input signals according to the clock signals to recover the clock signals. Therefore, the clock signal is obtained according to the differential input signal, and the amplification parameter of the differential input signal is adjusted according to the clock signal, so that the clock signal recovery mode realizes the phase synchronization of the clock signal and the differential input signal.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:
fig. 1 is a schematic structural diagram of an apparatus for clock signal recovery according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a differential input signal module according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a phase control voltage and clock signal phase relationship provided by an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another apparatus for clock signal recovery provided by an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of envelope detection for a differential input signal provided by an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of sampling a differential input signal with a clock signal according to an embodiment of the disclosure;
fig. 7 is a schematic diagram of a method for clock signal recovery according to an embodiment of the present disclosure.
Reference numerals:
1: a differential input signal module; 2: a pre-amplification module; 3: a comparator; 4: a negative feedback module; 5: an antenna; 6: a first capacitor; 7: a second capacitor; 8: a third capacitor; 9: a first resistor; 10: a second resistor; 11: a phase adjustment module; 12: an envelope detection module; 13: a mixer module; 14: an amplifier; 15: and a receiving device.
Detailed Description
So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the present disclosure described herein may be made. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the disclosed embodiments and their examples and are not intended to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation. Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meanings of these terms in the embodiments of the present disclosure can be understood by those of ordinary skill in the art as appropriate.
In addition, the terms "disposed," "connected," and "secured" are to be construed broadly. For example, "connected" may be a fixed connection, a detachable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components. Specific meanings of the above terms in the embodiments of the present disclosure can be understood by those of ordinary skill in the art according to specific situations.
The term "plurality" means two or more unless otherwise specified.
In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.
As shown in fig. 1, an apparatus for clock signal recovery according to an embodiment of the present disclosure includes a differential input signal module 1, a pre-amplification module 2, a comparator 3, and a negative feedback module 4. The differential input signal module 1 is used for acquiring an antenna voltage and generating a differential input signal according to the antenna voltage; the first end of the pre-amplification module 2 is electrically connected with one end of the differential input signal module 1; the pre-amplification module is used for amplifying the differential input signal; one end of the comparator 3 is electrically connected with the second end of the pre-amplification module 2, and the comparator is used for comparing the amplified differential input signals to obtain a clock signal; a first end of the negative feedback module 4 is electrically connected with the other end of the differential input signal module 1, a second end of the negative feedback module 4 is electrically connected with a third end of the pre-amplification module 2, and the third end of the negative feedback module 4 is electrically connected with the other end of the comparator; the negative feedback module is used for adjusting the amplification parameters of the differential input signals according to the clock signals to recover the clock signals.
By adopting the device for clock signal recovery provided by the embodiment of the disclosure, the antenna voltage is obtained through the differential input signal module and the differential input signal is generated according to the antenna voltage; the pre-amplification module amplifies the differential input signal; the comparator compares the amplified differential input signals to obtain a clock signal; the negative feedback module adjusts the amplification parameters of the differential input signals according to the clock signals to recover the clock signals. Therefore, the clock signal is obtained according to the differential input signal, and the amplification parameter of the differential input signal is adjusted according to the clock signal, so that the clock signal recovery mode realizes the phase synchronization of the clock signal and the differential input signal.
Optionally, the pre-amplification module is an adjustable gain amplifier.
As shown in connection with fig. 2, optionally, the differential input signal module 1 comprises an antenna 5 and a high-pass filtering module. The antenna is used for receiving antenna voltage; the high-pass filtering module is connected with the antenna; the high-pass filtering module is used for carrying out high-pass filtering on the antenna voltage to obtain a differential input signal.
Optionally, the high-pass filtering module includes a first capacitor 6, a second capacitor 7, a third capacitor 8, a first resistor 9, and a second resistor 10. A first receiving end of the antenna 5 is electrically connected with one end of the second capacitor 7, and a second receiving end of the antenna 5 is electrically connected with one end of the third capacitor 8; one end of the first capacitor 6 is electrically connected with a first receiving end of the antenna 5, and the other end of the first capacitor 6 is electrically connected with a second receiving end of the antenna 5; the other end of the second capacitor 7 is respectively connected with one end of the first resistor 9, the first input end of the pre-amplification module 2 and the negative feedback module 4; the other end of the third capacitor 8 is respectively connected with one end of the second resistor 10, the second input end of the pre-amplification module 2 and the negative feedback module 4; the other end of the first resistor 9 is electrically connected with the other end of the second resistor 10; the other end of the second resistor 10 is connected with VCM, and the VCM is a power supply. The differential input signal module receives the antenna voltage through the antenna, and the second capacitor, the third capacitor, the first resistor and the second resistor perform high-pass filtering on the antenna voltage to obtain a differential input signal.
Optionally, the negative feedback module comprises a phase control voltage module and a phase adjustment module. The first end of the phase control voltage module is electrically connected with the differential input signal module, the second end of the phase control voltage module is electrically connected with one end of the phase adjusting module, the third end of the phase control voltage module is electrically connected with the comparator, and the phase control voltage module is used for generating phase control voltage according to a clock signal; the other end of the phase adjusting module is electrically connected with the third end of the pre-amplifying module, and the phase adjusting module is used for adjusting the amplifying parameters of the differential input signals according to the phase control voltage so as to recover the clock signals.
The phase control voltage module generates phase control voltage according to the clock signal, and the phase adjusting module adjusts the amplification parameter of the differential input signal according to the phase control voltage, so that the phase synchronization of the clock signal and the differential input signal is realized.
Optionally, the amplification parameters are gain, bandwidth, and the like.
In some embodiments, the phase adjustment module changes the gain and bandwidth of the PreAMP module according to the phase control voltage VP _ ADJ, and amplifies the differential input signal according to the changed PreAMP module, so as to adjust the amplification parameter of the differential input signal. The comparator compares the amplified differential input signals to obtain a clock signal CLK _ REC. Therefore, the phase adjusting module changes the phase of the clock signal according to the phase control voltage. As shown in fig. 3, the Phase control voltage VP _ ADJ is proportional to the change in the Phase of the clock signal, and when the Phase control voltage VP _ ADJ is VCC, the Phase of the clock signal changes linearly by 360 degrees. The phase adjustment module adjusts the amplification parameters of the differential input signals according to the phase control voltage, the comparator compares the amplified differential input signals to obtain clock signals, and the clock signal recovery mode realizes the phase synchronization of the clock signals and the differential input signals.
Optionally, the phase control voltage module comprises an envelope detection module, a mixer module and an amplifier.
One end of the envelope detection module is electrically connected with the differential input signal module, the other end of the envelope detection module is electrically connected with the first input end of the amplifier, and the envelope detection module is used for generating an envelope detection voltage according to the differential input signal; the first end of the mixer module is electrically connected with the differential input signal module, the second end of the mixer module is electrically connected with the second input end of the amplifier, the third end of the mixer module is electrically connected with the comparator, and the mixer module is used for sampling the differential input signal according to the clock signal to obtain sampling voltage; the output end of the amplifier is electrically connected with the phase adjusting module, and the amplifier is used for amplifying the difference value between the envelope detection voltage and the sampling voltage to obtain the phase control voltage.
Thus, an envelope detection voltage is generated from the differential input signal; sampling the differential input signal according to the clock signal to obtain a sampling voltage; and amplifying the difference value between the envelope detection voltage and the sampling voltage to obtain a phase control voltage. In this way, the amplification parameter of the differential input signal is adjusted according to the phase control voltage, so that the phase synchronization of the clock signal and the differential input signal can be realized.
As shown in fig. 4, the apparatus for clock signal recovery includes a differential input signal module 1, a pre-amplifying module 2, a comparator 3, and a negative feedback module 4. The differential input signal module 1 comprises an antenna 5 and a high-pass filtering module. The high-pass filtering module comprises a first capacitor 6, a second capacitor 7, a third capacitor 8, a first resistor 9 and a second resistor 10. The negative feedback module 4 includes a phase control voltage module and a phase adjustment module 11. The phase control voltage module comprises an envelope detection module 12, a mixer module 13 and an amplifier 14. A first receiving end of the antenna 5 is electrically connected with one end of the second capacitor 7, and a second receiving end of the antenna 5 is electrically connected with one end of the third capacitor 8; one end of the first capacitor 6 is electrically connected with a first receiving end of the antenna 5, and the other end of the first capacitor 6 is electrically connected with a second receiving end of the antenna 5; the other end of the second capacitor 7 is connected to one end of the first resistor 8, the first input end of the pre-amplification module 2, the first end of the envelope detection module 12 and the first end of the mixer module 13 respectively; the other end of the third capacitor 8 is connected to one end of the second resistor 10, the second input end of the pre-amplification module 2, the second end of the envelope detection module 12 and the second end of the mixer module 13 respectively; the other end of the first resistor 9 is electrically connected with the other end of the second resistor 10; the other end of the second resistor 10 is connected with a VCM, and the VCM is a power supply; a first output end of the pre-amplification module 2 is electrically connected with a first input end of the comparator 3, and a second output end of the pre-amplification module 2 is electrically connected with a second input end of the comparator 3; a first output end of the comparator 3 is respectively connected with a third end of the mixer module 13 and the receiving device 15; the third terminal of envelope detection module 12 is electrically connected to the first input terminal of amplifier 14; the fourth end of the mixer module 13 is electrically connected to the second input end of the amplifier 14; the output end of the amplifier 14 is electrically connected with one end of the phase adjusting module 11; the other end of the phase adjustment module 11 is electrically connected to the third input end of the pre-amplification module 2.
In some embodiments, the envelope detection module envelope detects the differential input signal, obtains an envelope detection voltage, and outputs the envelope detection voltage to the amplifier; the frequency mixer module samples the differential input signal according to the clock signal to obtain a sampling voltage and outputs the sampling voltage to the amplifier; the amplifier amplifies the difference between the envelope detection voltage and the sampling voltage to obtain a phase control voltage, and outputs the phase control voltage to the phase adjusting module; the phase adjusting module adjusts the amplification parameters of the differential input signals according to the phase control voltage, changes the phases of the amplified differential input signals and outputs the differential input signals with the changed phases to the comparator; the comparator compares the differential input signals with the changed phases to obtain a clock signal. The phase adjustment module is used for adjusting the phase of the clock signal, the envelope detection module is used for tracking the amplitude of the differential input signal, and the phase adjustment system is constructed through the phase adjustment module, the envelope detection module, the mixer module and the amplifier, so that the phase of the input clock signal is automatically locked by the output clock signal, the frequency of the clock signal can be recovered, and the phase of the clock signal can be automatically recovered.
In some embodiments, the envelope detection module envelope detects the differential input signal to obtain an envelope detection voltage. Optionally, the envelope detection module is a diode envelope detection. Referring to fig. 5, fig. 5 is a schematic diagram of envelope detection for a differential input signal with time t on the abscissa and voltage V on the ordinate. The diode envelope detection performs envelope detection on the differential input signals RXP/RXN to obtain a peak voltage of the differential input signals, i.e., an envelope detection voltage Vpeak.
In some embodiments, the mixer module MIX samples the differential input signal RXP/RXN according to the clock signal CLK _ REC, obtaining a sampled voltage Vsamp. Alternatively, the mixer module samples the differential input signal according to the clock signal through a switched capacitor, an analog multiplier, and the like. The value of Vsamp depends on the sampling point of the clock signal CLK _ REC, and fig. 6 is a schematic diagram of the sampling of the differential input signal by the clock signal with time t on the abscissa and voltage V on the ordinate. Under the condition that the phases of CLK _ REC and RXP/RXN are synchronous, sampling points of clock signals fall on the peak value of the differential input signal, Vsamp reaches the maximum, and the differential input signal is also maximum; when the phase difference between CLK _ REC and RXP/RXN is 90 degrees, Vsamp is minimum and the differential input signal is zero.
Optionally by calculation
The phase control voltage is obtained, where VP _ ADJ is the phase control voltage and Gain is the Gain of the amplifier AMP. When the sampling point of CLK _ REC deviates from the peak point of RXP/RXN, the sampling voltage Vsamp is smaller than the envelope detection voltage Vpeak, and the amplifier AMP amplifies the difference between the sampling voltage and the envelope detection voltage to obtain a phase control voltage. The phase control voltage is proportional to the phase change of the clock signal becauseThe Gain of Gain is so large that the obtained phase control voltage VP _ ADJ, which controls the CLK _ REC phase to move forward until the phase of CLK _ REC is synchronized with the phase of RXP/RXN, at which time the sampling points of CLK _ REC are all at the peak points of RXP/RXN, Vsamp reaches a maximum, so that Vpeak = Vsamp. Therefore, the amplification parameters of the differential input signal are adjusted according to the phase control voltage, phase synchronization of the differential input signal and the clock signal is realized, and the CLK _ REC in the chip system can be used as a reference clock of the phase-locked loop circuit to generate clocks with more phases.
As shown in fig. 7, an embodiment of the present disclosure provides a method for clock signal recovery, including:
step S101, obtaining an antenna voltage, and generating a differential input signal according to the antenna voltage;
step S102, amplifying the differential input signal to obtain an amplified differential input signal;
step S103, comparing the amplified differential input signals to obtain a clock signal;
and step S104, adjusting the amplification parameters of the differential input signals according to the clock signals, and realizing the recovery of the clock signals.
According to the method for clock signal recovery provided by the embodiment of the disclosure, the clock signal is obtained according to the differential input signal, and the amplification parameter of the differential input signal is adjusted according to the clock signal, so that the clock signal recovery mode realizes the phase synchronization of the clock signal and the differential input signal.
Optionally, generating a differential input signal according to the antenna voltage comprises: and carrying out high-pass filtering on the antenna voltage to obtain a differential input signal.
Optionally, adjusting the amplification parameter of the differential input signal according to the clock signal includes: generating a phase control voltage according to the clock signal; and adjusting the amplification parameters of the differential input signals according to the phase control voltage. Therefore, the amplification parameters of the differential input signal are adjusted according to the phase control voltage, and the phase synchronization of the differential input signal and the clock signal is realized.
Optionally, generating the phase control voltage according to the clock signal includes: generating an envelope detection voltage from the differential input signal; sampling the differential input signal according to the clock signal to obtain a sampling voltage; and amplifying the difference value between the envelope detection voltage and the sampling voltage to obtain a phase control voltage.
The embodiment provides an NFC chip comprising the device for clock signal recovery as described above. The NFC chip obtains a clock signal according to the differential input signal, and then adjusts the amplification parameter of the differential input signal according to the clock signal, and the clock signal recovery mode realizes the phase synchronization of the clock signal and the differential input signal.
Optionally, the NFC chip further comprises a receiving device. The receiving device is electrically connected with the device for clock signal recovery, and the receiving device is used for converting the signal sent by the transmitter by using the clock signal and sending the converted signal to the digital baseband module. The clock signal is obtained according to the differential input signal, and the amplification parameter of the differential input signal is adjusted according to the clock signal, so that the clock signal recovery mode realizes the phase synchronization of the clock signal and the differential input signal, and the receiving sensitivity of the NFC chip is improved under the condition of being matched with a receiving device for use.
The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The embodiments of the present disclosure are not limited to the structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (6)
1. An apparatus for clock signal recovery, comprising:
the differential input signal module is used for acquiring antenna voltage and generating a differential input signal according to the antenna voltage;
the first end of the pre-amplification module is electrically connected with one end of the differential input signal module; the pre-amplification module is used for amplifying the differential input signal;
one end of the comparator is electrically connected with the second end of the pre-amplification module, and the comparator is used for comparing the amplified differential input signals to obtain a clock signal;
a first end of the negative feedback module is electrically connected with the other end of the differential input signal module, a second end of the negative feedback module is electrically connected with a third end of the pre-amplification module, and the third end of the negative feedback module is electrically connected with the other end of the comparator; the negative feedback module is used for adjusting the amplification parameters of the differential input signals according to the clock signals to realize the recovery of the clock signals;
the negative feedback module comprises:
a phase control voltage module, a first end of which is electrically connected with the differential input signal module, a second end of which is electrically connected with one end of the phase adjustment module, a third end of which is electrically connected with the comparator, the phase control voltage module being configured to generate a phase control voltage according to the clock signal;
the other end of the phase adjusting module is electrically connected with the third end of the pre-amplifying module, and the phase adjusting module is used for adjusting the amplification parameters of the differential input signal according to the phase control voltage so as to recover the clock signal;
the phase control voltage module includes:
one end of the envelope detection module is electrically connected with the differential input signal module, the other end of the envelope detection module is electrically connected with a first input end of the amplifier, and the envelope detection module is used for generating an envelope detection voltage according to the differential input signal;
a first end of the mixer module is electrically connected with the differential input signal module, a second end of the mixer module is electrically connected with a second input end of the amplifier, a third end of the mixer module is electrically connected with the comparator, and the mixer module is used for sampling the differential input signal according to the clock signal to obtain a sampling voltage;
the output end of the amplifier is electrically connected with the phase adjusting module, and the amplifier is used for amplifying the difference value between the envelope detection voltage and the sampling voltage to obtain a phase control voltage; the phase control voltage is proportional to the change in phase of the clock signal.
2. The apparatus of claim 1, wherein the differential input signal module comprises:
an antenna for receiving an antenna voltage;
the high-pass filtering module is connected with the antenna; the high-pass filtering module is used for carrying out high-pass filtering on the antenna voltage to obtain a differential input signal.
3. A method for clock signal recovery, comprising:
acquiring an antenna voltage, and generating a differential input signal according to the antenna voltage;
amplifying the differential input signal to obtain an amplified differential input signal;
comparing the amplified differential input signals to obtain a clock signal;
adjusting the amplification parameters of the differential input signals according to the clock signals to realize the recovery of the clock signals;
adjusting an amplification parameter of the differential input signal according to the clock signal, including:
generating a phase control voltage according to the clock signal;
adjusting the amplification parameters of the differential input signals according to the phase control voltage;
generating a phase control voltage from the clock signal, comprising:
generating an envelope detection voltage from the differential input signal;
sampling the differential input signal according to the clock signal to obtain a sampling voltage;
amplifying the difference value between the envelope detection voltage and the sampling voltage to obtain a phase control voltage; the phase control voltage is proportional to the change in phase of the clock signal.
4. The method of claim 3, wherein generating a differential input signal from the antenna voltage comprises:
and carrying out high-pass filtering on the antenna voltage to obtain a differential input signal.
5. An NFC chip comprising the apparatus for clock signal recovery of any of claims 1 to 2.
6. The NFC chip of claim 5, wherein the NFC chip further comprises:
and the receiving device is electrically connected with the device for clock signal recovery and is used for converting the signal sent by the transmitter by using the clock signal and sending the converted signal to the digital baseband module.
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| CN113810893A (en) | 2021-12-17 |
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