CN101740548A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN101740548A CN101740548A CN200910207981A CN200910207981A CN101740548A CN 101740548 A CN101740548 A CN 101740548A CN 200910207981 A CN200910207981 A CN 200910207981A CN 200910207981 A CN200910207981 A CN 200910207981A CN 101740548 A CN101740548 A CN 101740548A
- Authority
- CN
- China
- Prior art keywords
- metal line
- phase
- change material
- dielectric layer
- interlayer dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 64
- 239000002184 metal Substances 0.000 claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 239000011229 interlayer Substances 0.000 claims abstract description 34
- 239000012782 phase change material Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 3
- 239000013049 sediment Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 208000005189 Embolism Diseases 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910000763 AgInSbTe Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910005537 GaSeTe Inorganic materials 0.000 description 1
- 229910005872 GeSb Inorganic materials 0.000 description 1
- 229910000618 GeSbTe Inorganic materials 0.000 description 1
- 229910005898 GeSn Inorganic materials 0.000 description 1
- 229910005900 GeTe Inorganic materials 0.000 description 1
- 229910018321 SbTe Inorganic materials 0.000 description 1
- 229910018219 SeTe Inorganic materials 0.000 description 1
- 229910006913 SnSb Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- FESBVLZDDCQLFY-UHFFFAOYSA-N sete Chemical compound [Te]=[Se] FESBVLZDDCQLFY-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/041—Modification of switching materials after formation, e.g. doping
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/861—Thermal details
- H10N70/8616—Thermal insulation means
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8825—Selenides, e.g. GeSe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/884—Switching materials based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明的实施例涉及一种半导体器件,并且特别涉及一种可以降低半导体器件内的RC延迟的半导体器件及其制造方法。本发明的实施例提供一种半导体器件,包括:形成于半导体衬底上方的第一层间介电层;形成于第一层间介电层上方的第一金属布线和第二金属布线;形成于第一金属布线和第二金属布线上方的第二层间介电层;以及形成于第一金属布线和第二金属布线之间的相变材料层。本发明通过在所述金属布线之间形成气隙(该气隙取决于金属布线之间的区域中相变材料的相位变化)来降低半导体器件的RC延迟。
Description
技术领域
本发明的实施例涉及一种半导体器件,特别涉及一种半导体器件及其制造方法。
背景技术
随着半导体技术的发展,不断产生各种类型的问题。随着半导体器件的微型化(microminiaturization),对半导体器件的电学性质的要求也日益苛刻,因此需要有新的工艺或设计变化。
由于半导体器件的尺寸减小,出现的最显著的问题之一可能是在将外部电信号传输至晶体管时的RC延迟。在半导体器件的制造工艺期间,自然会产生RC延迟特性,例如可以用寄生电阻或者寄生电容作为其实例。在使用氧化物和金属的半导体器件中,通常会不可避免地产生寄生电阻和寄生电容。因此,对于降低寄生电阻和寄生电容的研究正方兴未艾。
例如,作为解决该问题的方法,提出使用铜(Cu)的布线工艺以及使用超低k材料的工艺。然而,由于这些材料也具有寄生电阻和寄生电容,所以它们并不是持久的解决方案。
图1是用来描述半导体器件中的RC延迟的视图。参照图1,在预定的层中形成多个金属布线11、12和13,并且在这些金属布线之间形成作为层间介电层的IMD。
在此情况下,在半导体器件中传输电信号的期间,每个金属布线11、12和13都示出为电阻特性,而IMD示出为电容特性。因此,由于电阻和电容是相关联的,所以存在电信号延迟传输的问题。
发明内容
为克服现有技术的缺陷,本发明的实施例涉及一种半导体器件,并且特别涉及一种可以降低半导体器件内的RC延迟的半导体器件及其制造方法。根据实施例的半导体器件包括:第一层间介电层,形成于半导体衬底上方;第一金属布线和第二金属布线,形成于所述第一层间介电层上方;第二层间介电层,形成于所述第一金属布线和第二金属布线上方;以及相变材料层,形成于所述第一金属布线与第二金属布线之间。
根据本发明实施例的一种用来制造半导体器件的方法,包括以下步骤:在半导体衬底上方形成第一层间介电层;在所述第一层间介电层上方形成多个金属布线;在所述第一层间介电层和所述金属布线上方沉积相变材料;通过平坦化所述相变材料,在所述金属布线之间形成相变材料层;在所述相变材料层和所述金属布线上方形成第二层间介电层;以及执行用来引起所述相变材料层的相位变化的热处理。本发明的实施例被设计成解决上述问题,并且本发明的实施例涉及在金属布线之间形成空气层以降低寄生电容的半导体器件以及其制造方法。
在所述金属布线之间形成相变材料之后,通过执行用于引起所述相变材料的相位变化的热处理,提供了一种在金属布线之间形成预定空气层的半导体器件及其制造方法。
附图说明
图1是用来描述半导体器件中的RC延迟的剖视图。
示例性图2-图6是用来描述根据实施例的制造半导体器件的方法的剖视图。
具体实施方式
示例性图2-图6是用来描述根据实施例的制造半导体器件的方法的剖视图。首先,参照示例性图2,通过执行将杂质注入半导体衬底100的工艺形成第一杂质区(即,源极区)101和第二杂质区(即,漏极区)。在半导体衬底100上方形成栅电极110。
本发明的实施例不局限于图中所示的半导体器件,而可以普遍适用于具有金属布线和层间介电层的半导体器件。可以由各种现有技术来实现在半导体衬底100中形成杂质区101和102的工艺及形成栅电极110的工艺。
同时,可以在半导体衬底100上方形成用于层间隔绝的第一层间介电层120。可以在第一层间介电层120中形成接触孔。可以在接触孔中形成接触栓塞133、134和135。还可以将第一层间介电层120称作金属前介电层(pre-metal dielectric,简写为PMD),以便与后文描述的第二层间介电层相区分。
接着,可以在第一层间介电层120上方形成与接触栓塞133、134和135电连接的金属布线130、131和132。可以以预定间隔来图案化金属布线130、131和132,以防止金属布线130、131和132互相接触。
参照示例性图3,可以在第一层间介电层120和金属布线130、131和132上方形成相变材料层140。在这里,可以通过用诸如CVD或者PVD等方法形成该相变材料层140。
此外,相变材料层140可以由以下各种材料制成,所述材料例如是将两种元素结合的GaSb、InSb、InSe、Sb2Te3和GeTe,将三种元素结合的GeSbTe、GaSeTe、InSbTe、SnSb2Te4和InSbGe,以及将四种元素结合的AgInSbTe、(GeSn)SbTe、GeSb(SeTe)和Te81Ge15Sb2S2,而相变材料层140应该是由具有其体积(volume)可缩小的性质的材料制成。
此外,如图所示,垂直地位于金属布线130、131和132上方的相变材料层140的高度可以大于形成于第一层间介电层120上方的相变材料层140的高度。
接着,参照示例性图4,可以执行平坦化相变材料层140的工艺。相变材料层140的蚀刻工艺可采用干蚀刻法,例如可以使用Cl2气体或者诸如CxHyFz等氟化物气体,但并不局限于此。因此,如图所示,相变材料层140可以被平坦化,从而使相变材料层140的高度和金属布线130、131和132的高度相同。
接着,参照图5,可以在金属布线130、131和132和相变材料层140上方形成第二层间介电层150。第二层间介电层150还可称作金属层间介电层(interlayer metal dielectric,简写为IMD),以便与第一层间介电层120相区分。
参照示例性图6,可以执行用来使形成于金属布线130、131和132之间的区域中的相变材料层140的相位变化的热处理工艺。通过该热处理工艺,相变材料层140的体积可以被减小,其结果是,如图所示,可以形成真空或者气隙160。
即,在第一金属布线130和第二金属布线131之间产生预定气隙160。还可以在第二金属布线131和第三金属布线132之间形成另一间隙。
在金属布线之间形成层间介电层的情况下,ε=4.0。在形成如上面的实施例中所述的气隙的情况下,该值示出为接近大约1.0。
例如,由于电容C可以表示为εε0A/d,则电容C与介电常数成正比,与距离d成反比。即,材料的介电常数越小,尺寸越小,距离越远,则电容值可以被减小,且RC延迟也可以被降低。结果,在ε值减小的实施例中,RC延迟被显著降低。
因此,可以通过形成气隙(该气隙取决于金属布线之间的区域中相变材料的相位变化)来降低半导体器件的RC延迟。
本发明实施例的半导体器件可以适用于范围广泛的半导体器件技术,并且可以由各种各样的半导体材料制造。由于目前大多数市售的半导体器件都是在硅衬底中制造的,并且通常所见的大部分实施例的应用会涉及硅衬底,所以随后的描述对在硅衬底中实现的半导体器件的实施例进行了讨论。不过,在绝缘体上硅(SOI)、锗和其它半导体材料中应用本发明的实施例也会颇有裨益。因此,本发明的实施例并不局限于在硅半导体材料中制造的那些器件,而是还可以包含由本领域普通技术人员能得到的一种或多种半导体材料及技术(诸如使用玻璃衬底上的多晶硅的薄膜晶体管(TFT)等技术)制造的那些器件。
对本领域普通技术人员而言,显然可以在所公开的实施例中进行各种变型和修改。因此,所公开的实施例应该涵盖各种显而易见的变型和修改,只要其落在所附权利要求及其等同物的范围内即可。
Claims (10)
1.一种设备,包括:
第一层间介电层,形成于半导体衬底上方;
第一金属布线和第二金属布线,形成于所述第一层间介电层上方;
第二层间介电层,形成于所述第一金属布线和第二金属布线上方;以及
相变材料层,形成于所述第一金属布线和第二金属布线之间。
2.根据权利要求1所述的设备,其中在所述第一层间介电层和所述第二层间介电层之间形成气隙。
3.根据权利要求2所述的设备,其中所述相变材料层和所述气隙形成于所述第一金属布线和所述第二金属布线之间。
4.根据权利要求2所述的设备,其中所述气隙呈真空状态。
5.根据权利要求1所述的设备,其中所述第一金属布线和所述第二金属布线形成有介于所述第一金属布线和所述第二金属布线之间的空隙区。
6.根据权利要求5所述的设备,其中所述空隙区呈真空状态。
7.一种方法,包括以下步骤:
在半导体衬底上方形成第一层间介电层;
在所述第一层间介电层上方形成多个金属布线;
在所述第一层间介电层和所述金属布线上方沉积相变材料;
通过平坦化所述相变材料,在所述金属布线之间形成相变材料层;
在所述相变材料层和所述金属布线上方形成第二层间介电层;以及
执行用来引起所述相变材料层的相位变化的热处理。
8.根据权利要求7所述的方法,其中在通过平坦化所述相变材料而形成所述相变材料层时,所述金属布线的厚度与所述相变材料层的厚度相同。
9.根据权利要求7所述的方法,其中在执行热处理工艺时,所述相变材料层的体积被减小,使得在所述金属布线之间产生预定气隙。
10.根据权利要求9所述的方法,其中所述气隙呈真空状态。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080109294A KR101002124B1 (ko) | 2008-11-05 | 2008-11-05 | 반도체 소자 및 상기 반도체 소자의 제조 방법 |
KR10-2008-0109294 | 2008-11-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN101740548A true CN101740548A (zh) | 2010-06-16 |
Family
ID=42130293
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200910207981A Pending CN101740548A (zh) | 2008-11-05 | 2009-11-04 | 半导体器件及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8071971B2 (zh) |
KR (1) | KR101002124B1 (zh) |
CN (1) | CN101740548A (zh) |
TW (1) | TW201019414A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104868053A (zh) * | 2015-04-30 | 2015-08-26 | 宁波大学 | 一种用于相变存储器的Ge-Sb-Te-Se薄膜材料及其制备方法 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8647439B2 (en) * | 2012-04-26 | 2014-02-11 | Applied Materials, Inc. | Method of epitaxial germanium tin alloy surface preparation |
US11810854B2 (en) * | 2019-05-15 | 2023-11-07 | Tokyo Electron Limited | Multi-dimensional vertical switching connections for connecting circuit elements |
US11069616B2 (en) * | 2019-05-16 | 2021-07-20 | Tokyo Electron Limited | Horizontal programmable conducting bridges between conductive lines |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0834916A2 (en) * | 1996-10-07 | 1998-04-08 | Motorola, Inc. | Method for manufacturing a semiconductor structure comprising regions formed with low dielectric constant material |
US6211561B1 (en) * | 1998-11-16 | 2001-04-03 | Conexant Systems, Inc. | Interconnect structure and method employing air gaps between metal lines and between metal layers |
US20050230836A1 (en) * | 2004-04-20 | 2005-10-20 | Clarke James S | Method of forming air gaps in a dielectric material using a sacrificial film and resulting structures |
US20060092693A1 (en) * | 2004-11-01 | 2006-05-04 | Bomy Chen | Phase change memory device employing thermally insulating voids and sloped trench, and a method of making same |
US20070126040A1 (en) * | 2005-11-21 | 2007-06-07 | Hsiang-Lan Lung | Vacuum cell thermal isolation for a phase change memory device |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6881668B2 (en) | 2003-09-05 | 2005-04-19 | Mosel Vitel, Inc. | Control of air gap position in a dielectric layer |
JP2008529269A (ja) * | 2005-01-25 | 2008-07-31 | エヌエックスピー ビー ヴィ | バックエンドプロセスを使用する相変化抵抗体の製造 |
US20080096344A1 (en) * | 2006-10-24 | 2008-04-24 | Macronix International Co., Ltd. | Method for Manufacturing a Resistor Random Access Memory with a Self-Aligned Air Gap insulator |
-
2008
- 2008-11-05 KR KR1020080109294A patent/KR101002124B1/ko not_active IP Right Cessation
-
2009
- 2009-10-29 US US12/608,055 patent/US8071971B2/en active Active
- 2009-11-04 CN CN200910207981A patent/CN101740548A/zh active Pending
- 2009-11-04 TW TW098137489A patent/TW201019414A/zh unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0834916A2 (en) * | 1996-10-07 | 1998-04-08 | Motorola, Inc. | Method for manufacturing a semiconductor structure comprising regions formed with low dielectric constant material |
US6211561B1 (en) * | 1998-11-16 | 2001-04-03 | Conexant Systems, Inc. | Interconnect structure and method employing air gaps between metal lines and between metal layers |
US20050230836A1 (en) * | 2004-04-20 | 2005-10-20 | Clarke James S | Method of forming air gaps in a dielectric material using a sacrificial film and resulting structures |
US20060092693A1 (en) * | 2004-11-01 | 2006-05-04 | Bomy Chen | Phase change memory device employing thermally insulating voids and sloped trench, and a method of making same |
US20070126040A1 (en) * | 2005-11-21 | 2007-06-07 | Hsiang-Lan Lung | Vacuum cell thermal isolation for a phase change memory device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104868053A (zh) * | 2015-04-30 | 2015-08-26 | 宁波大学 | 一种用于相变存储器的Ge-Sb-Te-Se薄膜材料及其制备方法 |
CN104868053B (zh) * | 2015-04-30 | 2017-08-25 | 宁波大学 | 一种用于相变存储器的Ge‑Sb‑Te‑Se薄膜材料及其制备方法 |
Also Published As
Publication number | Publication date |
---|---|
KR101002124B1 (ko) | 2010-12-16 |
TW201019414A (en) | 2010-05-16 |
US8071971B2 (en) | 2011-12-06 |
KR20100050153A (ko) | 2010-05-13 |
US20100108979A1 (en) | 2010-05-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9647209B2 (en) | Integrated phase change switch | |
US8334570B2 (en) | Metal gate stress film for mobility enhancement in FinFET device | |
CN202930361U (zh) | 一种半导体器件 | |
CN101533848B (zh) | 非易失性存储器器件及相关的方法和处理系统 | |
CN100590861C (zh) | 可编程通孔器件及其制造方法以及集成逻辑电路 | |
CN102667946B (zh) | 相变存储元件以及制造相变存储元件的方法 | |
US20070040159A1 (en) | Manufacturing method and structure for improving the characteristics of phase change memory | |
CN102089880A (zh) | 非易失性存储器器件的制造方法 | |
CN110858562B (zh) | 半导体元件制造方法及其制得的半导体元件 | |
JP2016192514A (ja) | 記憶装置及びその製造方法 | |
CN101740548A (zh) | 半导体器件及其制造方法 | |
KR101356329B1 (ko) | 가변 미앤더 라인 저항 | |
TWI743767B (zh) | 整合裝置之配置及形成整合裝置之配置之方法 | |
US20070111333A1 (en) | Method for manufacturing a resistively switching memory cell and memory device based thereon | |
US11296148B2 (en) | Variable resistance memory devices | |
CN112701222B (zh) | 一种阻变存储器及其制备方法 | |
CN101140922A (zh) | 半导体结构制造方法和其制造的半导体结构 | |
CN103560205B (zh) | 相变存储结构及制作方法 | |
CN102856384B (zh) | 使用后栅极工艺制造的场控晶体管结构 | |
CN112736198A (zh) | 一种阻变存储器及其制备方法 | |
CN103839919B (zh) | 电极的制造方法、熔丝装置及其制造方法 | |
CN107833967B (zh) | 相变化记忆体及其制造方法 | |
CN220359687U (zh) | 开关结构与半导体结构 | |
CN219719008U (zh) | 半导体结构 | |
CN112635668B (zh) | 一种阻变存储器及其制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20100616 |