CN101740539A - Square planar pin-free encapsulating unit and manufacturing method and lead frame thereof - Google Patents
Square planar pin-free encapsulating unit and manufacturing method and lead frame thereof Download PDFInfo
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- CN101740539A CN101740539A CN200810175561A CN200810175561A CN101740539A CN 101740539 A CN101740539 A CN 101740539A CN 200810175561 A CN200810175561 A CN 200810175561A CN 200810175561 A CN200810175561 A CN 200810175561A CN 101740539 A CN101740539 A CN 101740539A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
Abstract
The invention relates to a square planar pin-free encapsulating unit. The square planar pin-free encapsulating unit comprises a lead frame, a chip, a plurality of leads and an encapsulating colloid, wherein the lead frame comprises a chip seat and a plurality of pins; the chip seat and the plurality of the pins are provided with a first surface and an opposite second surface respectively; an active surface of the chip is provided with a plurality of welding pads; an inactive surface of the chip is connected with the chip seat; the plurality of the leads are in electric connection with the chip and the pins respectively; and the encapsulating colloid covers the chip, the leads and the lead frame and makes the chip seat and the second surfaces of the plurality of pins exposed out, wherein the outermost pin of the lead frame is provide with an extension part and an opposite recess for accommodating solder when the encapsulating unit is subjected to reflow welding and providing the combination in the horizontal direction and the vertical direction so as to increase a bonding area. The square planar pin-free encapsulating unit has the advantage of improving the combining intensity of the encapsulating unit.
Description
Technical field
The present invention relates to a kind of square planar pin-free encapsulating unit, refer to a kind of square planar pin-free encapsulating unit especially with the pin that strengthens solder bonds intensity.
Background technology
Square planar pin-free encapsulating unit is a kind of encapsulation unit that makes chip carrier and pin bottom surface expose to the packing colloid lower surface, generally adopts the surface technology that couples that encapsulation unit is coupled on the printed circuit board (PCB), forms the circuit module of a specific function thus.Couple in the operation on the surface, the chip carrier of square planar pin-free encapsulating unit and pin are for directly being soldered on the printed circuit board (PCB).
For example, the 6th, 201,292 and 7,049, No. 177 United States Patent (USP) discloses a kind of existing square planar pin-free encapsulating unit, below cooperates Fig. 1, and the coupling method of existing square planar pin-free encapsulating unit to printed circuit board (PCB) is described.
Existing square planar pin-free encapsulating unit 100, comprise with lower member: (a) lead frame 110, have chip carrier 111 and a plurality of pin 113, and this chip carrier 111 and these a plurality of pins 113 have first surface 120 and opposing second surface 130 respectively; (b) chip 140, have active surface 150 and relative non-active surface 160, have a plurality of weld pads 151 on this active surface 150, and wherein, the non-active surface 160 of this chip 140 connects on the first surface 120 that places this chip carrier 111; (c) a plurality of leads 170 electrically connect described weld pad 151 and described pin 113 respectively, and described lead 170 is engaged in the first surface 120 of described pin 113; And (d) packing colloid 180, coat this chip 140, described lead 170 and this lead frame 110, but make outside the second surface 130 of this chip carrier 111 and these a plurality of pins 113 is revealed in; Wherein, the second surface 130 of this chip carrier 111 presents a plane with the second surface 130 of this pin 113.
Printed circuit board (PCB) 190 comprises a substrate 191, grounding parts 193 and a plurality of conductive part 195.Grounding parts 193 is in order to the arrangement zone as the chip carrier 111 of square planar pin-free encapsulating unit 100, and its area is substantially equal to the area of chip carrier; Then as the point of the electric connection on the printed circuit board (PCB) 190, its area is substantially equal to the area of the exposed surface of each pin on the square planar pin-free encapsulating unit to conductive part 195.
Then, be coated with the weldering program, use scolder 197 is coated on the surface of grounding parts 193 and each conductive part 195.Carry out the surface afterwards again and couple program, square planar pin-free encapsulating unit 100 is placed on the printed circuit board (PCB) 190, and make each pin 113 and chip carrier 111 be aligned to corresponding conductive part 195 and grounding parts 193 respectively.
At last, carry out a reflow program (solder-reflow process), use the scolder reflow between each pin and the conductive part and between chip carrier and the grounding parts, so just finished the couple operation of square planar pin-free encapsulating unit to printed circuit board (PCB).
Yet, because in the reflow operation, the scolder of fusing can be to the center bunching, so the scolder after the reflow is slightly upwards swelled, make bonded area diminish, and because the second surface of this chip carrier and the second surface of this pin are all flat surfaces, this only plane combination also makes that solder bonds intensity is relatively poor, thereby produces the not good problem of reliability.
Therefore, how to solve the relatively poor problem that produces of above-mentioned existing solder bonds intensity, and develop a kind of square planar pin-free encapsulating unit of novelty, real is the problem that present anxious desire solves.
Summary of the invention
The shortcoming of background technology the invention provides the square planar pin-free encapsulating unit that a kind of pin bottom surface has recess in view of the above, with the solder bonds intensity of improve the standard direction and vertical direction.
The present invention discloses a kind of square planar pin-free encapsulating unit, comprising: (a) lead frame, comprise chip carrier and a plurality of pin, and this chip carrier and these a plurality of pins have first surface and opposing second surface respectively; (b) chip has active surface and relative non-active surface, has a plurality of weld pads on this active surface, and wherein, the non-active surface of this chip connects on the first surface that places this chip carrier; (c) a plurality of leads electrically connect described weld pad and described pin respectively, and described lead are engaged in the first surface of described pin; And (d) packing colloid, coat this chip, described lead and this lead frame, but make outside the second surface of this chip carrier and these a plurality of pins is revealed in; Wherein, the first surface place of the pin of this lead frame outermost is formed with extension, and extends to the direction away from first surface, and opposing second surface is formed with recess, in order to when this square planar pin-free encapsulating unit carries out reflow, make this recess hold scolder.
The present invention also discloses a kind of method of making square planar pin-free encapsulating unit, comprise: support plate is provided, and this support plate comprises a plurality of lines of cut of being defined in this support plate surface, is formed at the par that a plurality of projection and this a plurality of projection centered on this line of cut; This have form metal level on the support plate surface of projection after, this metal level of patterning is to obtain lead frame, this lead frame has the chip carrier with first surface and opposing second surface and a plurality of pin that is formed on this par, wherein, the pin of part is formed at this projection place and coats this projection, and the pin that is formed at this projection place has extension and recess; Follow chip join on this chip carrier; Form a plurality of leads again, to electrically connect chip and pin; Form packing colloid on this support plate, to coat this pin, chip carrier, chip and lead; Remove this support plate, make to expose outside this lead frame; And along described line of cut cutting and separating to obtain a plurality of square planar pin-free encapsulating units.
The present invention discloses the lead frame that a kind of square surface does not have lead foot in addition, comprising: chip carrier; And a plurality of pins around this chip carrier, this chip carrier and these a plurality of pins have first surface and opposing second surface respectively; Wherein, the first surface place of the pin of this lead frame outermost is formed with extension, and to extending away from the direction of first surface, and opposing second surface is formed with recess, in order to hold scolder.
Below in conjunction with technique scheme, beneficial effect of the present invention is described.The recess of the second surface of the present invention by being formed at pin, utilize this recess when this square planar pin-free encapsulating unit carries out reflow, to hold scolder, combination on level and the vertical direction is provided, and has increased bonding area, thereby improved solder bonds intensity.
Description of drawings
Fig. 1 is the generalized section of existing square planar pin-free encapsulating unit;
Fig. 2 A to Fig. 2 G is the generalized section of square planar pin-free encapsulating unit of the present invention and method for making thereof;
Fig. 2 A ' is for showing the generalized section that is formed at the lead frame on the support plate;
Fig. 2 A " be formed at the generalized section of the lead frame on the support plate for showing another;
Fig. 3 A is the generalized section of another square planar pin-free encapsulating unit of the present invention; And
Fig. 3 B to Fig. 3 D is for showing the recess schematic diagram that is formed at the chip carrier second surface of the present invention.
[main element symbol description]
100,200 square planar pin-free encapsulating units
110,210 lead frames
111,211 chip carriers
113,213 pins
120,220 first surfaces
130,230 second surfaces
140,240 chips
150,250 active surfaces
151,251 weld pads
160,260 non-active surfaces
170,270 leads
180,280 packing colloids
190,290 printed circuit board (PCB)s
191 substrates
193,293 grounding parts
195,295 conductive parts
197,297 scolders
212 support plates
214 surfaces
216 matrix adhesive areas
218 lines of cut
219 matrix units
221 pars
223 projections
225 extensions
227 ones
241 adhesive
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, the person of an ordinary skill in the technical field can understand other advantages of the present invention and effect easily by the content that this specification disclosed.
First embodiment
See also Fig. 2 A to Fig. 2 G, be the schematic diagram of square planar pin-free encapsulating unit of the present invention and method for making thereof.
Shown in Fig. 2 A, a support plate 212 is provided, the material of support plate 212 can be (but being not limited to) for example metal material such as copper.The surface 214 of this support plate 212 comprises a matrix adhesive area 216, and these matrix adhesive area 216 definition have a plurality of lines of cut 218 and matrix unit 219.
Consult Fig. 2 A ' again, these support plate 212 each matrix units 219 have par 221 and a plurality of projection 223 is formed on this line of cut 218 and around this par 221, described projection 223 is substantially equal to the area of a square planar pin-free encapsulating unit 200 around the area of these par 221 gained; Then, on this support plate 212, utilize plating and Patternized technique technology to form the metal level of patterning, metal level has, gold/palladium/nickel/palladium layer or gold/nickel/copper/palladium layer for example, and with this patterned metal layer as lead frame 210, this lead frame 210 has chip carrier 211 and a plurality of pin 213, and wherein, this chip carrier 211 is formed on this par 221 and the area of chip carrier 211 is substantially equal to area of chip; The pin 213 of part is formed between this chip carrier 211 and this projection 223 and the pin 213 of part is formed at these projection 223 places and coats this projection 223, therefore, with respect to this projection, the pin 213 that is formed at these projection 223 places has extension 225 and recess 227.
Perhaps, as Fig. 2 A " shown in, line of cut 218 inboards of each matrix unit 219 of support plate also have the projection 223 around this par 221, and therefore, the area of this par 221 is little than the area shown in Fig. 2 A '.
Particularly, with reference to Fig. 2 A ', the disclosed square surface of the present invention does not have the lead frame 210 of lead foot, comprising: chip carrier 211; And a plurality of pins 213 around this chip carrier 211, this chip carrier 211 and these a plurality of pins 213 have first surface 220 and opposing second surface 230 respectively; Wherein, first surface 220 places of the pin 213 of these lead frame 210 outermost are formed with extension 225, and to extending away from the direction of first surface 220, and opposing second surface 230 is formed with recess 227, in order to hold scolder.
Similarly, according to Fig. 2 A " shown in, the first surface place of whole pins of this lead frame can be formed with extension, and extends to the direction away from first surface, and opposing second surface is formed with recess.In addition, the second surface of the chip carrier of this lead frame can also be formed with recess, in order to when this square planar pin-free encapsulating unit carries out reflow, makes this recess hold scolder.
Shown in Fig. 2 B, carry out sticking brilliant step, the chip 240 that has a plurality of weld pads 251 on the active surface 250 is provided, and makes the non-active surface 260 of relative this active surface 250 of chip 240 engage this chip carrier 211 by adhesive 241.Among the present invention, the example of adhesive includes, but is not limited to elargol.
Shown in Fig. 2 C, carry out the electric connection step of chip and pin, it utilizes the mode of routing (wire-bonding) to form a plurality of leads 270, and described lead 270 electrically connects the weld pad 251 and pin 213 of chip 240.
Shown in Fig. 2 D, carry out a sealing step, it utilizes the mode of pressing mold or gluing to form packing colloid, and packing colloid 280 is formed on this support plate 212, to coat this pin 213, chip carrier 211, chip 240 and lead 270.
Shown in Fig. 2 E, execution is just like the etching step of Wet-type etching, removing this support plate, thereby manifests the bottom surface 261 of this lead frame 210 and the bottom surface 261 of packing colloid 280, and owing to remove the support plate that this has projection, the pin 213 that before had been formed at this projection place relatively has recess 227.
Shown in Fig. 2 F, then carry out step of cutting, it is along described each matrix unit of line of cut 218 cutting and separating, to obtain square planar pin-free encapsulating unit 200 of the present invention.
By aforementioned method for making, the present invention also discloses a kind of square planar pin-free encapsulating unit 200, comprise: lead frame 210, comprise chip carrier 211 and a plurality of pin 213, this chip carrier 211 and these a plurality of pins 213 have first surface 220 and opposing second surface 230 respectively;
A plurality of leads 270 electrically connect described weld pad 251 and described pin 213 respectively, and described lead 270 is engaged in the first surface 220 of described pin 213; And
Wherein, first surface 220 places of the pin 213 of these lead frame 210 outermost are formed with extension 225, and to direction extension away from first surface 220, and opposing second surface 230 is formed with recess 227, in order to when this square planar pin-free encapsulating unit 200 carries out reflow, make this recess hold scolder.More specifically, the pin of described outermost has step structure, and the recess of this pin is positioned at the lateral border of this encapsulation unit.
In another instantiation of the present invention, all the first surface place of pin all is formed with extension, and extends to the direction away from first surface, and opposing second surface is formed with recess.
Shown in Fig. 2 G, be coated with weldering and reflow step in regular turn, one printed circuit board (PCB) 290 is provided, this printed circuit board (PCB) 290 has default grounding parts 293 and conductive part 295, use scolder 297 is coated on the surface of grounding parts 293 and each conductive part 295, again square planar pin-free encapsulating unit 200 is placed on the printed circuit board (PCB) 290 afterwards, and makes each pin 213 and chip carrier 211 be aligned to corresponding conductive part 295 and grounding parts 293 respectively.
At last, carry out a reflow program (solder-reflow process), use scolder 297 reflows between each pin 213 and the conductive part 295 and between chip carrier 211 and the grounding parts 293, so just finished the couple operation of square planar pin-free encapsulating unit 200 of the present invention to printed circuit board (PCB) 290, in addition, because the pin with recess of square planar pin-free encapsulating unit of the present invention is positioned on the line of cut, therefore after reflow, this scolder can coat the pin of this encapsulation unit side, thereby better bond strength is provided.
Therefore, the pin of square planar pin-free encapsulating unit of the present invention has recess, in order to holding scolder, and then improves the standard and the bond strength of vertical direction; Moreover the first surface place of this pin is formed with extension, and extends to the direction away from first surface, and therefore pin of the present invention provides more areas that combine with packing colloid, has also strengthened the bond strength of pin and packing colloid.
Second embodiment
See also Fig. 3 A to Fig. 3 D, be the schematic diagram of square planar pin-free encapsulating unit second embodiment of the present invention.For simplifying this figure, corresponding aforementioned same or analogous element all adopts same numeral to represent in the present embodiment simultaneously.
The square planar pin-free encapsulating unit of present embodiment and method for making thereof and previous embodiment are roughly the same, main difference is that the second surface of this chip carrier also is formed with recess, in order to when this square planar pin-free encapsulating unit carries out reflow, make this recess hold scolder.The formation method of the recess of the second surface of this chip carrier can be after remove this support plate, is formed with recess at the second surface of this chip carrier.
As shown in Figure 3A, the recess 227 of this chip carrier 211 is formed at the middle position of these chip carrier 211 second surfaces 230.
In addition, shown in Fig. 3 B and Fig. 3 C, the recess 227 of this middle position is that the recess 227 of rectangle or this middle position is circle.
Shown in Fig. 3 D, the recess 227 of this chip carrier 211 also can be formed at the peripheral position of these chip carrier 211 second surfaces 230.
On the other hand, by Fig. 3 A to Fig. 3 D as can be known, the recess that square surface of the present invention does not have an included chip carrier of the lead frame of lead foot can be formed at the middle position of this chip carrier second surface, and the shape of this recess do not have special restriction, so the recess of this middle position can be rectangle or circle.In addition, the recess of this chip carrier also can be formed at the peripheral position of this chip carrier second surface.
The recess of the second surface of square planar pin-free encapsulating unit of the present invention by being formed at pin, utilize this recess when this square planar pin-free encapsulating unit carries out reflow, to hold scolder, combination on level and the vertical direction is provided, and increase bonding area, in addition, inwardly be formed with step structure owing to be positioned at the pin of encapsulation unit lateral border,, more can improve the encapsulation unit bond strength so can when reflow, make scolder coat the pin of this lateral border.
Above-described specific embodiment, only for to release characteristics of the present invention and effect in order to example, but not in order to limit the category of implementing of the present invention, do not breaking away under above-mentioned spirit of the present invention and the technology category, the disclosed content of any utilization and the equivalence finished changes and modify all still should be the appending claims scope and contains.
Claims (16)
1. square planar pin-free encapsulating unit comprises:
Lead frame comprises chip carrier and a plurality of pin, and this chip carrier and these a plurality of pins have first surface and opposing second surface respectively;
Chip has active surface and relative non-active surface, has a plurality of weld pads on this active surface, and wherein, the non-active surface of this chip connects on the first surface that places this chip carrier;
A plurality of leads electrically connect described weld pad and described pin respectively, and described lead are engaged in the first surface of described pin; And
Packing colloid coats this chip, described lead and this lead frame, but makes outside the second surface of this chip carrier and these a plurality of pins is revealed in;
It is characterized in that, the first surface place of the pin of this lead frame outermost is formed with extension, and extends to the direction away from first surface, and opposing second surface is formed with recess, in order to when this square planar pin-free encapsulating unit carries out reflow, make this recess hold scolder.
2. square planar pin-free encapsulating unit according to claim 1 is characterized in that the pin of this outermost has step structure, and the recess of this pin is positioned at the lateral border of this encapsulation unit.
3. square planar pin-free encapsulating unit according to claim 1 is characterized in that, the first surface place of the pin that these are whole is formed with extension, and extends to the direction away from first surface, and opposing second surface is formed with recess.
4. square planar pin-free encapsulating unit according to claim 1 is characterized in that the second surface of this chip carrier also is formed with recess, in order to when this square planar pin-free encapsulating unit carries out reflow, makes this recess hold scolder.
5. square planar pin-free encapsulating unit according to claim 4 is characterized in that the recess of this chip carrier is formed at the middle position of this chip carrier second surface.
6. square planar pin-free encapsulating unit according to claim 4 is characterized in that the recess of this chip carrier is formed at the peripheral position of this chip carrier second surface.
7. a square surface does not have the lead frame of lead foot, comprising:
Chip carrier; And
A plurality of pins around this chip carrier, this chip carrier and these a plurality of pins have first surface and opposing second surface respectively;
It is characterized in that the first surface place of the pin of this lead frame outermost is formed with extension, and to extending, and opposing second surface is formed with recess, in order to hold scolder away from the direction of first surface.
8. square surface according to claim 7 does not have the lead frame of lead foot, it is characterized in that, the pin of this outermost has step structure, and the recess of this pin is positioned at the lateral border of this encapsulation unit.
9. square surface according to claim 7 does not have the lead frame of lead foot, it is characterized in that, the first surface place of the pin that these are whole is formed with extension, and extends to the direction away from first surface, and opposing second surface is formed with recess.
10. square surface according to claim 7 does not have the lead frame of lead foot, it is characterized in that, the second surface of this chip carrier also is formed with recess, in order to when this square planar pin-free encapsulating unit carries out reflow, makes this recess hold scolder.
11. square surface according to claim 10 does not have the lead frame of lead foot, it is characterized in that, the recess of this chip carrier is formed at the middle position of this chip carrier second surface.
12. square surface according to claim 10 does not have the lead frame of lead foot, it is characterized in that, the recess of this chip carrier is formed at the peripheral position of this chip carrier second surface.
13. the method for making of a square planar pin-free encapsulating unit is characterized in that, comprises the steps:
Support plate is provided, and this support plate comprises a plurality of lines of cut of being defined in this support plate surface, is formed at the par that a plurality of projection and this a plurality of projection centered on this line of cut;
In this have form metal level on the support plate surface of projection after, this metal level of patterning is to obtain lead frame, this lead frame has the chip carrier with first surface and opposing second surface and a plurality of pin that is formed on this par, wherein, the pin of part is formed at this projection place and coats this projection, and the pin that is formed at this projection place has extension and recess;
With chip join on this chip carrier;
Form a plurality of leads, to electrically connect chip and pin;
Form packing colloid on this support plate, to coat this pin, chip carrier, chip and lead;
Remove this support plate, make to expose outside this lead frame; And
Along described line of cut cutting and separating to obtain a plurality of square planar pin-free encapsulating units.
14. the method for making of square planar pin-free encapsulating unit according to claim 13 is characterized in that, also comprises by scolder the chip carrier and the pin of this matrix unit is engaged in printed circuit board (PCB).
15. the method for making of square planar pin-free encapsulating unit according to claim 13 is characterized in that, also be included in remove this support plate after, be formed with recess at the second surface of this chip carrier.
16. the method for making of square planar pin-free encapsulating unit according to claim 15 is characterized in that, the recess of this chip carrier is formed at the peripheral position of this chip carrier second surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810175561XA CN101740539B (en) | 2008-11-07 | 2008-11-07 | Square planar pin-free encapsulating unit and manufacturing method and lead frame thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810175561XA CN101740539B (en) | 2008-11-07 | 2008-11-07 | Square planar pin-free encapsulating unit and manufacturing method and lead frame thereof |
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| Publication Number | Publication Date |
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| CN101740539A true CN101740539A (en) | 2010-06-16 |
| CN101740539B CN101740539B (en) | 2011-11-30 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102867801A (en) * | 2011-07-08 | 2013-01-09 | 矽品精密工业股份有限公司 | Semiconductor carrier and package and fabrication method thereof |
| CN103855103A (en) * | 2012-11-30 | 2014-06-11 | 三菱电机株式会社 | Semiconductor device and manufacturing method thereof |
| CN104538318A (en) * | 2014-12-24 | 2015-04-22 | 南通富士通微电子股份有限公司 | Fan-out wafer level chip packaging method |
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| CN102867801A (en) * | 2011-07-08 | 2013-01-09 | 矽品精密工业股份有限公司 | Semiconductor carrier and package and fabrication method thereof |
| CN103855103A (en) * | 2012-11-30 | 2014-06-11 | 三菱电机株式会社 | Semiconductor device and manufacturing method thereof |
| CN104538318A (en) * | 2014-12-24 | 2015-04-22 | 南通富士通微电子股份有限公司 | Fan-out wafer level chip packaging method |
| CN104538318B (en) * | 2014-12-24 | 2017-12-19 | 通富微电子股份有限公司 | A kind of Fanout type wafer level chip method for packing |
| CN109698187A (en) * | 2017-10-20 | 2019-04-30 | 日月光半导体制造股份有限公司 | Semiconductor device packages |
| CN109037083A (en) * | 2018-07-27 | 2018-12-18 | 星科金朋半导体（江阴）有限公司 | A kind of packaging method of QFN fingerprint recognition chip |
| CN109119396A (en) * | 2018-09-14 | 2019-01-01 | 上海凯虹科技电子有限公司 | Lead frame and the packaging body for using the lead frame |
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