CN101729838A

CN101729838A - Image recording system

Info

Publication number: CN101729838A
Application number: CN200910312214A
Authority: CN
Inventors: 陈颖图; 楚要钦
Original assignee: AVIC No 631 Research Institute
Current assignee: AVIC No 631 Research Institute
Priority date: 2009-12-24
Filing date: 2009-12-24
Publication date: 2010-06-09

Abstract

The invention relates to an image recording system, which comprises a processor, a memory medium, a FLASH memory, a SDRAM and two asynchronous FIFO memories. The technical problem to be solved in the invention is to provide the image recording system to overcome the shortcomings in the prior art. The image recording system can greatly saves the system space and makes the size small, and can be applicable to various environments.

Description

A kind of image recording system

Technical field

The present invention relates to a kind of image recording system.

Background technology

Because image information has characteristics such as amount of information is abundant, directly perceived lively, so image information is intactly noted in real time, is the necessary means of in scientific research and the practical engineering application image being analysed in depth and being handled.But, all had higher requirement in aspects such as the miniaturization of the memory capacity of the transmission rate of data, system, system, stability along with the continuous development of image recording system technology.And the storage of at present traditional image record is owing to be subjected to the influence of many-sided factors such as storage medium, host-host protocol, signal integrity, external environment, can't reach the more miniaturization of system and more at a high speed, more stable Imagery Data Recording stores.

Existing image recording system has following defective owing to be subjected to influence of various factors such as storage medium, host-host protocol, signal integrity, external environment:

1, the system intelligent degree is low, and complex interfaces is unfavorable for artificial exploitation;

2, whole system is too huge, is difficult to be applied to other similar system;

3, systematic function is not high, is difficult to satisfy various markets application demand;

4, the stability of a system is not strong, can variety of issue often occur, causes being difficult to using.

Existing IDE electric board is as data storage medium, have that volume is little, capacity is big, interface intelligentized degree height, speed advantages of higher, therefore, select the IDE electric board can give full play to the advantage of storage medium, develop that speed height, memory space are big, the image stored record system of dependable performance.

Aspect peripheral bus, pci bus obtains popularizing rapidly and development with its unique design and advantages such as high-performance, opening that are independent of processor, has been widely used in the transfer of data of high-speed data acquisition, storage system.Its bus bandwidth is 32 and scalable to 64, and bus speed can reach 33/66MHz, when Synchronization Control, sudden transmission message transmission rate up to 132MB/s (32,33MHz), 264MB/s (64,33MHz) or 528MB/s (64,66MHz).

Therefore, development is a kind of is that the miniature high-speed image recording system of storage medium has very important significance based on the pci bus standard with the high-speed high capacity electric board.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of image recording system, to overcome the defective that exists in the prior art.

Technical scheme of the present invention is:

A kind of image recording system, its special character is: comprise processor, storage medium, FLASH memory, SDRAM and 2 asynchronous FIFO memories,

Form respectively in the described FPGA ide interface, image transmit interface, image data interface, sdram controller and, wherein,

Ide interface and image transmit interface, are used for the translation interface standard, pci interface on the realization processor and the exchanges data between the storage medium interface;

Image data interface is used to receive the external image data;

Sdram controller is used to control SDRAM and carries out caching image data;

The FLASH memory is used to store start-up routine;

Described 2 asynchronous FIFO memories are used for data are cushioned, and have mated the sequential between pci bus and the storage medium.

Comprise serial ports, be used for whole system is monitored;

Form Asynchronous Serial Interface and synchronous serial interface in the described FPGA, it changes the back by level respectively and is connected with serial ports, and is connected with FLASH/ROM interface on the processor.

Comprise the image processing compression chip, be used for view data is compressed;

Form image compression interface in the described FPGA, it is connected with the image processing compression chip with sdram controller respectively.

Above-mentioned processor adopting PowerPC processor MPC8245,

Described serial ports is 16C550,

It is that 2.5 cun, capacity are 16G, support that ATA-6 standard, peak transfer rate 100MB/s, lasting transmission rate are the electric board of 36MB/s that described storage medium adopts size,

Described FPGA adopts the XC2V1000-6FG456 fpga chip,

Described each FIFO memory size is 1K * 16bit.

Technique effect of the present invention is:

1, utilize current application low-power consumption high-performance widely PowerPC processor and peripheral circuit as system platform, whole system has high-performance, the most of function of whole system is realized by FPGA, saved system space largely, make and to be applicable to various environment by volume little (whole system only takies 128mm * 78mm * 20mm spatial volume).

2, utilize high-performance FPGA to realize comprising most of interface functions such as system call, image processing, storage and serial line interface, the height that reaches whole system is integrated.

3, comprise host-host protocols such as PCI2.2 standard, ATA-6 standard inner realization of FPGA, be used for the high-speed transfer of view data, big capacity storage control, reach the high speed performance of image recording system.

4, in systems soft ware, open the file system function that it contains, be used for the image file after the stored record is optimized configuration management, reach the high stability of image recording system.

Description of drawings

Fig. 1 is a system architecture diagram of the present invention.

Fig. 2 is a pci bus DMA transmission cycle sequential chart.

Fig. 3 is a FPGA built-in function block diagram.

Embodiment

1, Hardware platform design:

Referring to Fig. 1, core of hardware platform is PowerPC processor MPC8245, the nuclear of the inner integrated MPC603e of this processor (highest point reason speed 300MHz), a 100MHz high-speed SRAM memory interface and a PCI bridge that satisfies the PCI2.2 standard, the high energy of this PCI bridge is realized the data transmission bauds of 132MB/s, performance satisfies the native system requirement, its also integrated 2 dma controller is supported the DMA transmission between the PCI Weapon-handle-of-bamboo-strips cheat wife of one's mother's brother 20. Gua Gui Xiu CI, the internal memory Weapon-handle-of-bamboo-strips cheat wife of one's mother's brother CI-PCI in addition.

Storage medium uses is 2.5 cun electric board, and capacity 16G supports the ATA-6 standard, peak transfer rate 100MB/s, and lasting transmission rate is 36MB/s.Whole hardware platform only takies the area of 128mm * 78mm.

On pci bus, carry out high speed data transfer and can adopt direct memory storage DMA technology, the DMA technology is the method for big data quantity transmission between a kind of memory of being finished by dma controller and external equipment or the memory, neither pass through CPU, do not need the intervention of CPU yet, the performance of whole system is improved greatly, can reach the maximum data transfer rate of pci bus standard, referring to the cycle sequential chart of the pci bus DMA of Fig. 2 transmission.

2, FPGA design: the present invention can adopt the XC2V1000-6FG456 fpga chip of Xilinx company, XC2V1000-6FG456 is the high-performance FPGA of Virtex-II series, support the internal clocking of the highest 420MHz, have the internal RAM of 1,000,000,5120 logical blocks, 720Kbit to can be used for making up FIFO.Chip internal provides the pci interface of 33/66MHz and the PCI-X interface of 66/133MHz, and SRAM and DRAM interface at a high speed also is provided.Utilize the Block RAM of FPGA inside to produce 2 asynchronous FIFO memories, make pci bus and electric board respectively when different the ordered pair memory operate, thereby solve the problem of different sequential couplings.

The major function of FPGA is to finish each link control in the view data flow process, is asynchronous, the synchronous serial interface of PowerPC processor and extraneous communication expansion simultaneously, and the periodic Control of memory access is provided, referring to the FPGA built-in function block diagram of Fig. 3.

Because the sequential of pci bus and electric board does not match, data at a high speed can't be by the pci bus electric board that writes direct, therefore memory of needs cushions or mates, make pci bus and electric board respectively when different the ordered pair memory operate, thereby solve the problem of different sequential couplings.Consider the factors such as integrated and stability of circuit, (each FIFO size is 1K * 16bit) to utilize the Block RAM of FPGA inside to produce 2 asynchronous FIFO memories.Based on the characteristic of the first-in first-out of FIFO, data utilize FIFO to cushion, and are no more than the time that is filled with the FIFO degree of depth as long as write the used time of electric board, and can reach data does not have and lose storage fully.

3, Design of System Software: system produces different software flows according to different transmission commands, FPGA handles and transmits view data according to system requirements, realize the high speed acquisition storage of view data, the image file of gathering after storing is optimized configuration management through file system, reaches accurate, the stable recording of view data.

Configurable VxWorks 5.5 real-time multi-task operating systems of native system are in charge of the course of work of hardware resource distribution, scheduling and application software in the system and task executions order.Operating system software mainly has following function:

A, quick real-time response ability;

B, exception handling ability;

C, house dog disposal ability;

D, multi-task scheduling ability;

E, support data cache (CACHE);

F, dynamic memory management ability;

G, message queue ability;

H, can cut out ability;

I, system clock tenability, auxiliary clock tenability;

J, provide api interface for the user.

In addition, this systems soft ware self has file system function, is used for managing image file, supports the FAT32 file format, makes the compatibility of system stronger.

After the start, native system can produce different software flows according to different transmission commands, FPGA handles and transmits view data according to system requirements, realize the high speed acquisition storage of view data, the image file of gathering after storing is optimized configuration management through file system, reaches accurate, the stable recording of view data.

The invention provides one based on the PowerPC processor platform, the FPGA technology is the miniaturized system of core, and the most of function of whole system is realized by FPGA, has saved system space largely.System finishes functions such as the processing, transmission of view data and record storage, file management, and accord with PCI 2.2 and ATA-6 protocol specification have high speed, stable characteristics.

The present invention can be applied to high-speed memory system, and the miniaturization that it had, the characteristics of high stability make it to be not easy to be subjected to the influence in environment, space, have good application prospects.

Claims

1. image recording system is characterized in that: comprise processor, storage medium, FLASH memory, SDRAM and 2 asynchronous FIFO memories,

Image data interface is used to receive the external image data;

Sdram controller is used to control SDRAM and carries out caching image data;

The FLASH memory is used to store start-up routine;

2. image recording system according to claim 1 is characterized in that: comprise serial ports, be used for whole system is monitored; Form Asynchronous Serial Interface and synchronous serial interface in the described FPGA, it changes the back by level respectively and is connected with serial ports, and is connected with FLASH/ROM interface on the processor.

3. image recording system according to claim 1 and 2 is characterized in that: comprise the image processing compression chip, be used for view data is compressed; Form image compression interface in the described FPGA, it is connected with the image processing compression chip with sdram controller respectively.

4. image recording system according to claim 3, it is characterized in that: described processor adopting PowerPC processor MPC8245, described serial ports is 16C550, it is that 2.5 cun, capacity are 16G, support that ATA-6 standard, peak transfer rate 100MB/s, lasting transmission rate are the electric board of 36MB/s that described storage medium adopts size, described FPGA adopts the XC2V1000-6FG456 fpga chip, and described each FIFO memory size is 1K * 16bit.