CN101707196A - Improved electrostatic discharge protective device, corresponding method and integrated circuit - Google Patents
Improved electrostatic discharge protective device, corresponding method and integrated circuit Download PDFInfo
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- CN101707196A CN101707196A CN200910051382A CN200910051382A CN101707196A CN 101707196 A CN101707196 A CN 101707196A CN 200910051382 A CN200910051382 A CN 200910051382A CN 200910051382 A CN200910051382 A CN 200910051382A CN 101707196 A CN101707196 A CN 101707196A
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Abstract
The invention provides an improved ESD protective device, which is used for eliminating the current flowing through an ESD protective device when in normal electrifying and comprises a detecting circuit, a driving circuit and a discharge tube, wherein the driving circuit comprises a one-stage or multistage phase inverter, and the final-stage phase inverter is a CMOS phase inverter, wherein the CMOS phase inverter comprises a loading tube and a driving tube. The improved ESD protective device is characterized in that a first voltage division circuit is connected between the loading tube and the driving tube. The invention also provides a corresponding control method and an integrated circuit. The improved ESD protective device limits the electric potential of a grid electrode of the discharge tube by using the first voltage division circuit to connect the loading tube and the driving tube of the last-stage phase inverter of the discharge tube, thus solving the problem that the NMOS tube 31 can not be conducted when in normal electrifying and further eliminating the corresponding adverse influence using the system to electrify.
Description
Technical field
The present invention relates to electrostatic discharge protective device, especially the electrostatic discharge protective device on power supply and ground particularly, relates to and is used to eliminate the electrostatic discharge protective device that flows through the electric current of electrostatic discharge protection component when normally powering on.
Background technology
In the reliability design of CMOS integrated circuit, an important link is exactly the design problem of static discharge (ESD, electrostatic discharge) protective circuit.So-called ESD phenomenon is exactly that the external environment condition of chip or internal structure can accumulate a certain amount of electric charge in the manufacturing, transportation, use in integrated circuit (IC) chip, and the electric charge of these accumulation can spark by the pin of chip.Static discharge moment, the peak current by IC interior can reach several amperes, and the big electric current of this transient state is enough to chip is burnt.There is statistics to show, has in the reason of ic failure more than 1/3 and cause owing to ESD.Yet the ESD phenomenon is present in the whole process of production, encapsulation, transportation and use of integrated circuit, and therefore effective ways that improve IC reliability are exactly or/and outside according to the different suitable esd protection circuits of needs adding at chip internal.
For integrated circuit, static discharge is described with three kinds of physical models usually, be respectively manikin (HBM, human body model), machine mould (MM, machine model) and charging device model (CDM, charged-device model), represent the dissimilar static discharges in the real world separately.The ESD protection circuit of IO and the ESD protection circuit between POWER (power clamp) have constituted the ESD protection of entire I C jointly.
Aspect the ESD protection between POWER, when ESD voltage is added between VDD and the GND, except meeting causes IC internal circuit damage, also often triggers some parasitic semiconductor element conductings and burn.In the CMOS integrated circuit, SCR element that the modal parasitic antenna that burns is exactly p-n-p-n and the BJT transistor of n-p-n.Along with the continuous development of integrated circuit fabrication process, the spacing of parasitic antenna is also more and more littler, and this makes them have higher gain and is more prone to be triggered.Therefore, the esd protection unit between power supply and the ground need possess opening speed fast, can bearing great current, characteristics such as conducting voltage is low, itself is not fragile.Power supply esd protection element circuit commonly used at present is a MOS discharge tube by the control of static discharge circuit for detecting.
In the prior art, esd detection circuit is made of the RC circuit, and wherein, resistance R can use polysilicon (poly) resistance to realize.The advantage of Poly resistance is that resistance is relatively accurate.But, because the ON time long enough of ESD current drain device in the time of will guaranteeing esd discharge, the value of resistance R is bigger, and the square resistance of poly resistance less (less than 10ohm/sheet square) in some processing procedures, so the chip area of this resistance is bigger.In order to save area, this resistance can be realized with MOS.The breadth length ratio of adjusting MOS is easy to obtain the resistance of needs, and area is little more a lot of than poly resistance.Compare with poly resistance, though MOS resistance has been saved area, but introduced new problem, the ESD current drain device that promptly should be in cut-off state when normally powering on has electric current and flows through, and can influence application system when serious and normally power on.
Summary of the invention
At defective of the prior art, the purpose of this invention is to provide a kind of improved electrostatic discharge protective device.
According to an aspect of the present invention, a kind of improved electrostatic discharge protective device is provided, be used to eliminate the electric current that flows through electrostatic discharge protection component when normally powering on, comprise testing circuit, drive circuit and discharge tube, wherein, described drive circuit comprises one or more levels inverter, and the afterbody inverter is the CMOS inverter, and wherein, described CMOS inverter comprises load pipe and driving tube, it is characterized in that, be connected with first bleeder circuit between described load pipe and the driving tube.
Preferably, described first bleeder circuit comprises at least one the first transistor.
Preferably, described the first transistor is the PMOS pipe.
Preferably, described the first transistor is the NMOS pipe.
Preferably, described the first transistor is a diode.
Preferably, described the first transistor is the NPN pipe.
Preferably, described the first transistor is the PNP pipe.
According to a further aspect in the invention, a kind of control method that flows through the electric current of electrostatic discharge protection component when normally powering on that is used to eliminate in improved electrostatic discharge protective device also is provided, it is characterized in that, comprise step: a. provides grid potential to discharge tube during normally powering on; And the b. discharge tube is in not on-state under the control of described grid potential.
According to a further aspect of the invention, also provide a kind of integrated circuit, comprise power pins, internal circuit and ESD protection circuit, it is characterized in that, also comprise first bleeder circuit that is used for controlling ESD protection circuit discharge tube grid potential.
Preferably, described first bleeder circuit comprises the first transistor.
The present invention is by being connected the current potential that described first bleeder circuit limits described discharge tube grid between the load pipe of discharge tube previous stage inverter and the driving tube, thereby when normally powering on, described NMOS pipe 31 can not conducting, and then has eliminated the adverse effect that the application system is powered on.
Description of drawings
By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that other features, objects and advantages of the present invention will become:
Fig. 1 and Fig. 2 illustrate according to prior art jointly, the structural representation of the ESD protection circuit on power supply and ground;
Fig. 3 illustrates according to circuit shown in Figure 2, the variation characteristic schematic diagram of the electric current of the described discharge tube 31 of flowing through in normal power up;
Fig. 4 illustrates according to the first embodiment of the present invention, the structural representation of electrostatic discharge protective device;
Fig. 5 illustrates according to a second embodiment of the present invention, the structural representation of electrostatic discharge protective device;
Fig. 6 illustrates a third embodiment in accordance with the invention, the structural representation of electrostatic discharge protective device;
Fig. 7 illustrates a fourth embodiment in accordance with the invention, the structural representation of electrostatic discharge protective device;
Fig. 8 illustrates according to a fifth embodiment of the invention, the structural representation of electrostatic discharge protective device;
Fig. 9 illustrates according to a sixth embodiment of the invention, the structural representation of electrostatic discharge protective device;
Figure 10 illustrates according to a seventh embodiment of the invention, the structural representation of electrostatic discharge protective device;
Figure 11 illustrates according to the eighth embodiment of the present invention, the structural representation of electrostatic discharge protective device;
Figure 12 illustrates according to the ninth embodiment of the present invention, the structural representation of electrostatic discharge protective device;
Figure 13 illustrates according to the tenth embodiment of the present invention, the structural representation of electrostatic discharge protective device;
Figure 14 illustrates according to one of the first embodiment of the present invention and changes example, the structural representation of the inverter of CMOS described in the electrostatic discharge protective device 22;
Figure 15 illustrates according to a second embodiment of the present invention one and changes example, the structural representation of the inverter of CMOS described in the electrostatic discharge protective device 22;
Figure 16 illustrates one of a third embodiment in accordance with the invention and changes example, the structural representation of the inverter of CMOS described in the electrostatic discharge protective device 22;
Figure 17 illustrates one of a fourth embodiment in accordance with the invention and changes example, the structural representation of the inverter of CMOS described in the electrostatic discharge protective device 22; And
Figure 18 illustrates according to a fifth embodiment of the invention one and changes example, the structural representation of the inverter of CMOS described in the electrostatic discharge protective device 22.
Embodiment
Fig. 1 and Fig. 2 illustrate according to prior art jointly, the structural representation of the ESD protection circuit on power supply and ground.Particularly; in Fig. 1; the ESD protection circuit on power supply and ground comprises testing circuit 1, drive circuit 2 ' and discharge tube 3; wherein; described testing circuit 1 is used to detect electrostatic discharge event; when detecting static discharge, described testing circuit 1 is by the described discharge tube 3 of the described drive circuit 2 ' control ESD electric current of releasing.More specifically; because the ESD voltage rise time is short; described discharge tube 3 gets final product conducting and form temporary low resistive state between VDD and GND in the short time of its generation; thereby the ESD electric current can be bypassed through esd protection circuit, thereby the SCR and the BJT element of chip internal circuit and parasitism can not destroy because of ESD.
Next, Fig. 2 describes the structure of power supply of the prior art with the esd protection circuit on ground on the basis of Fig. 1 further.Particularly, in Fig. 2, described testing circuit 1 comprises MOS resistance 11 and capacitive device 12, wherein, described MOS resistance 11 and described capacitive device 12 have been formed a control circuit based on the RC time constant, preferably, in the present embodiment, described MOS resistance 11 employing PMOS resistance (and change in the example at one, described MOS resistance can adopt NMOS resistance), described drive circuit 2 ' can adopt one or more levels inverter, it is used to drive described discharge tube 31, preferably, above-mentioned inverter is the CMOS inverter, and described discharge tube 31 is connected across the ESD electric current to release between VDD and the GND between the VDD of power supply and the GND, wherein, described drive circuit 2 ' input connect the drain electrode of described PMOS pipe 11, the grid of described discharge tube 31 and described drive circuit 2 ' output be connected.More specifically, when having on the VDD with respect to GND is that the ESD of positive polarity is when taking place, described capacitive device 12 is in short-circuit condition substantially, with described drive circuit 2 ' the current potential of input drag down, make 31 grid potential of described discharge tube raise, thereby make described discharge tube 31 conductings with the ESD electric current of releasing; And be the ESD of negative polarity when taking place when having with respect to GND on the VDD, described discharge tube 31 entozoic diode forward conductings are with the ESD electric current of releasing.Those skilled in the art understand, described according to actual needs discharge tube 3 can adopt NMOS pipe or PMOS pipe, those skilled in the art can with reference to above-mentioned at the NMOS pipe explanation and existing techniques in realizing by the above-mentioned PMOS pipe ESD electric current of releasing, do not repeat them here.Those skilled in the art also understand, and described capacitive device 12 can adopt multiple electronic device to constitute, for example poly electric capacity and mos capacitance, and those skilled in the art can not repeat them here in conjunction with the described capacitive device 12 of existing techniques in realizing.
Fig. 3 illustrates according to circuit shown in Figure 2, in normal power up, the flow through variation characteristic schematic diagram of electric current of described discharge tube 31. particularly, curve 41 illustrates the variation characteristic of vdd voltage in the normal power up, curve 42 illustrates the variation characteristic of the electric current I 3 of the described discharge tube 31 of flowing through in the normal power up, more specifically, in VDD is power-up to a period of time that is slightly larger than the MOS threshold voltage vt, having electric current I peak in the described discharge tube 31 flows through, the reason that this electric current produces is when the vdd voltage value is near the MOS threshold voltage vt, the resistance that described MOS resistance 11 is realized is excessive, described testing circuit 1 is by described discharge tube 31 conductings of described drive circuit 2 ' make. further, the size of above-mentioned electric current I peak is directly proportional with the size of described discharge tube 31, when the anti-ESD Capability Requirement of IC is higher, the size of described discharge tube 31 can be very big, above-mentioned electric current I peak can reach tens milliamperes and even up to a hundred milliamperes, consider that from the angle of system applies above-mentioned electric current I peak does not wish to occur.
Above-mentioned Fig. 1 to Fig. 3 is described ESD protection circuit of the prior art; at the defective that exists in the prior art; described electrostatic discharge protective device provided by the invention comprises first bleeder circuit; wherein; described first bleeder circuit is connected between the drain electrode of the drain electrode of described load pipe 221 and described driving tube 222; particularly; the input of described first bleeder circuit connects the drain electrode of described load pipe 221; the output of described first bleeder circuit connects the drain electrode of described driving tube 222; those skilled in the art understand; described bleeder circuit can limit the grid potential of described discharge tube 3; making can not conducting at discharge tube 3 described in the normal power up, has eliminated the electric current I peak shown in Fig. 3.Further, described first bleeder circuit preferably includes at least one the first transistor, and preferably, described the first transistor can adopt electronic devices such as PMOS pipe, NMOS pipe, diode, NPN pipe and PNP pipe.Next be described by Fig. 4 to 13 pair of electrostatic discharge protective device according to the present invention.It will be appreciated by those skilled in the art that in the prior art the CMOS inverter is made of PMOS pipe and NMOS pipe usually, wherein, with the PMOS pipe as the load pipe, with the NMOS pipe as driving tube, when the current potential of CMOS inverter input is electronegative potential, the conducting of load pipe, driving tube ends; When the current potential of CMOS inverter input was high potential, the load pipe ended, the driving tube conducting.Those skilled in the art are appreciated that about the description of load pipe and driving tube in conjunction with prior art, do not repeat them here.
Particularly, Fig. 4 illustrates according to the first embodiment of the present invention, the structural representation of electrostatic discharge protective device.Particularly, in the present embodiment, described electrostatic discharge protective device comprises testing circuit 1, drive circuit 2 and NMOS pipe 31, wherein, described testing circuit 1 comprises PMOS resistance 11 and capacitive device 12, described drive circuit 2 comprises drive sub-circuits 21 and CMOS inverter 22, further, described CMOS inverter 22 comprises load pipe 221 (preferably adopting the PMOS pipe), driving tube 222 (preferably adopting the NMOS pipe) and PMOS pipe 223, wherein, the source electrode of described load pipe 221 connects the VDD bus, the source electrode of described driving tube 222 connects the GND bus, be connected with described PMOS pipe 223 between described load pipe 221 and the described driving tube 222, more specifically, the source electrode of described PMOS pipe 223 connects the drain electrode of described load pipe 221, and the drain electrode of described PMOS pipe 223 connects the drain electrode of described driving tube 222, the grid of described PMOS pipe 223 is connected with drain electrode, and the grid of described NMOS pipe 31 connects the drain electrode of described PMOS pipe 223.Those skilled in the art understand, described PMOS pipe 223 makes the threshold voltage vt of the highest grid potential of described NMOS pipe 31 than the low MOS of VDD, the grid potential of described NMOS pipe 31 is limited, described NMOS pipe 31 can not conducting when normally powering on, eliminate above-mentioned electric current I peak, thereby eliminated the adverse effect that the application system is powered on.
Fig. 5 illustrates according to a second embodiment of the present invention, the structural representation of electrostatic discharge protective device.Particularly, in the present embodiment, described electrostatic discharge protective device comprises testing circuit 1, drive circuit 2 and NMOS pipe 31, those skilled in the art understand, different with first embodiment shown in Figure 4 is, described testing circuit 1 comprises NMOS pipe 11 ' and capacitive device 12, described CMOS inverter 22 comprises load pipe 221 (preferably adopting the PMOS pipe), driving tube 222 (preferably adopting the NMOS pipe) and NMOS pipe 224, further, be connected with described NMOS pipe 224 between described load pipe 221 and the described driving tube 222, more specifically, the drain electrode of described NMOS pipe 224 connects the drain electrode of described load pipe 221, the source electrode of described NMOS pipe 224 connects the drain electrode of described driving tube 222, and the grid of described NMOS pipe 224 is connected with drain electrode, and the grid of described NMOS pipe 31 connects the source electrode of described NMOS pipe 224.
Fig. 6 illustrates a third embodiment in accordance with the invention, the structural representation of electrostatic discharge protective device. particularly, in the present embodiment, described electrostatic discharge protective device comprises testing circuit 1, drive circuit 2 and NMOS pipe 31, those skilled in the art understand, different with first embodiment shown in Figure 4 is, described CMOS inverter 22 comprises load pipe 221, driving tube 222 and diode 225, further, be connected with described diode 225 between described load pipe 221 and the described driving tube 222, more specifically, the positive pole of described diode 225 connects the drain electrode of described load pipe 221, the negative pole of described diode 225 connects the drain electrode of described driving tube 222, and the grid of described NMOS pipe 31 connects the negative pole of described diode 225.
Fig. 7 illustrates a fourth embodiment in accordance with the invention, the structural representation of electrostatic discharge protective device.Particularly, in the present embodiment, described electrostatic discharge protective device comprises testing circuit 1, drive circuit 2 and NMOS pipe 31, those skilled in the art understand, different with first embodiment shown in Figure 4 is, described CMOS inverter 22 comprises load pipe 221 (preferably adopting the PMOS pipe), driving tube 222 (preferably adopting the NMOS pipe) and NPN pipe 226, further, be connected with described NPN pipe 226 between described load pipe 221 and the described driving tube 222, more specifically, the collector electrode of described NPN pipe 226 connects the drain electrode of described load pipe 221, the emitter of described NPN pipe 226 connects the drain electrode of described driving tube 222, the base stage of described NPN pipe 226 is connected with collector electrode, and the grid of described NMOS pipe 31 connects the emitter of described NPN pipe 226.
Fig. 8 illustrates according to a fifth embodiment of the invention, the structural representation of electrostatic discharge protective device.Particularly, in the present embodiment, described electrostatic discharge protective device comprises testing circuit 1, drive circuit 2 and NMOS pipe 31, those skilled in the art understand, different with first embodiment shown in Figure 4 is, described CMOS inverter 22 comprises load pipe 221 (preferably adopting the PMOS pipe), driving tube 222 (preferably adopting the NMOS pipe) and PNP pipe 227, further, be connected with described PNP pipe 227 between described load pipe 221 and the described driving tube 222, more specifically, the emitter of described PNP pipe 227 connects the drain electrode of described load pipe 221, the collector electrode of described PNP pipe 227 connects the drain electrode of described driving tube 222, the base stage of described PNP pipe 227 is connected with collector electrode, and the grid of described NMOS pipe 31 connects the collector electrode of described PNP pipe 227.
Above-mentioned Fig. 4 embodiment extremely shown in Figure 8 adopts the situation of NMOS pipes to be illustrated at described discharge tube 3, next adopts the situation of PMOS pipes to describe by the embodiment shown in Fig. 9 to Figure 13 at described discharge tube 3.Particularly, Fig. 9 illustrates according to a sixth embodiment of the invention, the structural representation of electrostatic discharge protective device.Particularly, in the present embodiment, described electrostatic discharge protective device comprises testing circuit 1, drive circuit 2 and PMOS pipe 31 ', wherein, described testing circuit 1 comprises PMOS resistance 11 and capacitive device 12, described drive circuit 2 comprises drive sub-circuits 21 and CMOS inverter 22, further, described CMOS inverter 22 comprises load pipe 221 (preferably adopting the PMOS pipe), driving tube 222 (preferably adopting the NMOS pipe) and PMOS pipe 223 ', wherein, the source electrode of described load pipe 221 connects the VDD bus, the source electrode of described driving tube 222 connects the GND bus, be connected with between described load pipe 221 and the described driving tube 222 described PMOS pipe 223 ', more specifically, described PMOS pipe 223 ' source electrode connect the drain electrode of described load pipe 221, described PMOS pipe 223 ' drain electrode connect the drain electrode of described driving tube 222, described PMOS pipe 223 ' grid is connected with drain electrode, described PMOS manages 31 ' grid connect described PMOS and manage 223 ' source electrode.
Figure 10 illustrates according to a seventh embodiment of the invention, the structural representation of electrostatic discharge protective device.Particularly, in the present embodiment, described electrostatic discharge protective device comprises testing circuit 1, drive circuit 2 and PMOS pipe 31 ', those skilled in the art understand, different with the 6th embodiment shown in Figure 9 is, described CMOS inverter 22 comprises load pipe 221 (preferably adopting the PMOS pipe), driving tube 222 (preferably adopting the NMOS pipe) and NMOS pipe 224 ', further, be connected with between described load pipe 221 and the described driving tube 222 described NMOS pipe 224 ', more specifically, described NMOS pipe 224 ' drain electrode connect the drain electrode of described load pipe 221, described NMOS pipe 224 ' source electrode connect the drain electrode of described driving tube 222, described NMOS pipe 224 ' grid is connected with drain electrode, described PMOS manages 31 ' grid connect described NMOS and manage 224 ' drain electrode.
Figure 11 illustrates according to the eighth embodiment of the present invention, the structural representation of electrostatic discharge protective device. particularly, in the present embodiment, described electrostatic discharge protective device comprises testing circuit 1, drive circuit 2 and PMOS pipe 31 ', those skilled in the art understand, different with the 6th embodiment shown in Figure 9 is, described CMOS inverter 22 comprises load pipe 221, driving tube 222 and diode 225 ', further, be connected with between described load pipe 221 and the described driving tube 222 described diode 225 ', more specifically, described diode 225 ' positive pole connect the drain electrode of described load pipe 221, described diode 225 ' negative pole connect the drain electrode of described driving tube 222, described PMOS pipe 31 ' grid connect described diode 225 ' positive pole.
Figure 12 illustrates according to the ninth embodiment of the present invention, the structural representation of electrostatic discharge protective device.Particularly, in the present embodiment, described electrostatic discharge protective device comprises testing circuit 1, drive circuit 2 and PMOS pipe 31 ', those skilled in the art understand, different with the 6th embodiment shown in Figure 9 is, described CMOS inverter 22 comprises load pipe 221 (preferably adopting the PMOS pipe), driving tube 222 (preferably adopting the NMOS pipe) and NPN pipe 226 ', further, be connected with between described load pipe 221 and the described driving tube 222 described NPN pipe 226 ', more specifically, described NPN pipe 226 ' collector electrode connect the drain electrode of described load pipe 221, described NPN pipe 226 ' emitter connect the drain electrode of described driving tube 222, described NPN pipe 226 ' base stage is connected with collector electrode, described PMOS manages 31 ' grid connect described NPN and manage 226 ' collector electrode.
Figure 13 illustrates according to the tenth embodiment of the present invention, the structural representation of electrostatic discharge protective device.Particularly, in the present embodiment, described electrostatic discharge protective device comprises testing circuit 1, drive circuit 2 and PMOS pipe 31 ', those skilled in the art understand, different with the 6th embodiment shown in Figure 9 is, described CMOS inverter 22 comprises load pipe 221 (preferably adopting the PMOS pipe), driving tube 222 (preferably adopting the NMOS pipe) and PNP pipe 227 ', further, be connected with between described load pipe 221 and the described driving tube 222 described PNP pipe 227 ', more specifically, described PNP pipe 227 ' emitter connect the drain electrode of described load pipe 221, described PNP pipe 227 ' collector electrode connect the drain electrode of described driving tube 222, described PNP pipe 227 ' base stage is connected with collector electrode, described PMOS manages 31 ' grid connect described PNP and manage 227 ' emitter.
Figure 14 illustrates according to one of the first embodiment of the present invention and changes example, the structural representation of the inverter of CMOS described in the electrostatic discharge protective device 22.Particularly, in the present embodiment, different with first embodiment shown in Figure 4 is, described CMOS inverter 22 comprises load pipe 221 (preferably adopting the PMOS pipe), driving tube 222 (preferably adopting the NMOS pipe), PMOS pipe 2231, PMOS pipe 2232 and PMOS pipe 2233, more specifically, described PMOS pipe 2231, PMOS pipe 2232 and PMOS pipe 2233 separately grid (utmost point) leak between the drain electrode of the drain electrode that is connected on described load pipe 221 behind (utmost point) short circuit and described driving tube 222.In a preference, the grid of described discharge tube 3 connects the drain electrode of described load pipe 221; And in another preference, the grid of described discharge tube 3 connects the drain electrode of described driving tube 222.Those skilled in the art can increase or reduce the PMOS pipe that is connected between described load pipe and the driving tube according to actual needs, and this does not influence flesh and blood of the present invention, does not repeat them here.
Figure 15 illustrates according to a second embodiment of the present invention one and changes example, the structural representation of the inverter of CMOS described in the electrostatic discharge protective device 22.Particularly, in the present embodiment, different with second embodiment shown in Figure 5 is, described CMOS inverter 22 comprises load pipe 221 (preferably adopting the PMOS pipe), driving tube 222 (preferably adopting the NMOS pipe), NMOS pipe 2241, NMOS pipe 2242 and NMOS pipe 2243, more specifically, described NMOS pipe 2241, NMOS pipe 2242 and NMOS pipe 2243 separately grid (utmost point) leak between the drain electrode of the drain electrode that is connected on described load pipe 221 behind (utmost point) short circuit and described driving tube 222.In a preference, the grid of described discharge tube 3 connects the drain electrode of described load pipe 221; And in another preference, the grid of described discharge tube 3 connects the drain electrode of described driving tube 222.Those skilled in the art can increase or reduce the NMOS pipe that is connected between described load pipe and the driving tube according to actual needs, and this does not influence flesh and blood of the present invention, does not repeat them here.
Figure 16 illustrates one of a third embodiment in accordance with the invention and changes example, the structural representation of the inverter of CMOS described in the electrostatic discharge protective device 22.Particularly, in the present embodiment, different with the 3rd embodiment shown in Figure 6 is, described CMOS inverter 22 comprises load pipe 221 (preferably adopting the PMOS pipe), driving tube 222 (preferably adopting the NMOS pipe), diode 2251, diode 2252 and diode 2253, more specifically, the drain electrode of described load pipe 221 connects the positive pole of described diode 2251, the negative pole of described diode 2251 connects the positive pole of described diode 2252, the negative pole of described diode 2252 connects the positive pole of described diode 2253, and the negative pole of described diode 2253 connects the drain electrode of described driving tube 222.In a preference, the grid of described discharge tube 3 connects the drain electrode of described load pipe 221; And in another preference, the grid of described discharge tube 3 connects the drain electrode of described driving tube 222.Those skilled in the art can increase or reduce the diode that is connected between described load pipe and the driving tube according to actual needs, and this does not influence flesh and blood of the present invention, does not repeat them here.
Figure 17 illustrates one of a fourth embodiment in accordance with the invention and changes example, the structural representation of the inverter of CMOS described in the electrostatic discharge protective device 22.Particularly, in the present embodiment, different with the 4th embodiment shown in Figure 7 is, described CMOS inverter 22 comprises load pipe 221 (preferably adopting the PMOS pipe), driving tube 222 (preferably adopting the NMOS pipe), NPN pipe 2261, NPN pipe 2262 and NPN pipe 2263, more specifically, described NPN pipe 2261, NPN pipe 2262 and NPN pipe 2263 be base stage and collector electrode short circuit separately, the drain electrode of described load pipe 221 connects the collector electrode of described NPN pipe 2261, the emitter of described NPN pipe 2261 connects the collector electrode of described NPN pipe 2262, the emitter of described NPN pipe 2262 connects the collector electrode of described NPN pipe 2263, and the emitter of described NPN pipe 2263 connects the drain electrode of described driving tube 222.In a preference, the grid of described discharge tube 3 connects the drain electrode of described load pipe 221; And in another preference, the grid of described discharge tube 3 connects the drain electrode of described driving tube 222.Those skilled in the art can increase or reduce the NPN pipe that is connected between described load pipe and the driving tube according to actual needs, and this does not influence flesh and blood of the present invention, does not repeat them here.
Figure 18 illustrates according to a fifth embodiment of the invention one and changes example, the structural representation of the inverter of CMOS described in the electrostatic discharge protective device 22.Particularly, in the present embodiment, different with the 5th embodiment shown in Figure 8 is, described CMOS inverter 22 comprises load pipe 221 (preferably adopting the PMOS pipe), driving tube 222 (preferably adopting the NMOS pipe), PNP pipe 2271, PNP pipe 2272 and PNP pipe 2273, more specifically, described PNP pipe 2271, PNP pipe 2272 and PNP pipe 2273 be base stage and collector electrode short circuit separately, the drain electrode of described load pipe 221 connects the emitter of described PNP pipe 2271, the collector electrode of described PNP pipe 2271 connects the emitter of described PNP pipe 2272, the collector electrode of described PNP pipe 2272 connects the emitter of described PNP pipe 2273, and the collector electrode of described PNP pipe 2273 connects the drain electrode of described driving tube 222.In a preference, the grid of described discharge tube 3 connects the drain electrode of described load pipe 221; And in another preference, the grid of described discharge tube 3 connects the drain electrode of described driving tube 222.Those skilled in the art can increase or reduce the PNP pipe that is connected between described load pipe and the driving tube according to actual needs, and this does not influence flesh and blood of the present invention, does not repeat them here.
It will be appreciated by those skilled in the art that above-mentioned Fig. 4 to embodiment shown in Figure 13, described drive sub-circuits 21 can comprise odd level or even level inverter.And change in the example at one, described drive sub-circuits 21 can be omitted, and for example when described CMOS inverter 22 was enough to drive load, described drive sub-circuits can be omitted, and this does not influence flesh and blood of the present invention, does not repeat them here.
Described Fig. 4 to Fig. 7 shows the multiple framework of described testing circuit 1 respectively, those skilled in the art understand, to more changeableization example embodiment illustrated in fig. 13, described testing circuit 1 can be changed to any in the above-mentioned multiple framework according to actual needs at described Fig. 4; Correspondingly, described drive sub-circuits can be changed to the even level inverter or be changed to the odd level inverter by the even level inverter by the odd level inverter.
Fig. 4 the invention provides a kind of control method that flows through the electric current of electrostatic discharge protection component when normally powering on that is used to eliminate to embodiment illustrated in fig. 18 and variation example in improved electrostatic discharge protective device according to the present invention.Preferably include following steps:
Step a. provides grid potential to discharge tube during normally powering on; And
Step b. discharge tube is in not on-state under the control of described grid potential.
It will be appreciated by those skilled in the art that by being connected of described CMOS inverter 22 and described discharge tube, can realize providing the purpose of grid potential to described discharge tube.
Fig. 4 also provides a kind of integrated circuit to embodiment illustrated in fig. 18 and variation example according to the present invention.Particularly, it comprises power pins, internal circuit and ESD protection circuit, and preferably, this integrated circuit also comprises first bleeder circuit that is used for controlling ESD protection circuit discharge tube grid potential.It will be appreciated by those skilled in the art that preferably described first bleeder circuit comprises the first transistor, and is for example shown in Figure 4.Preferably, described the first transistor can comprise any in one or more following transistors: PMOS pipe, NMOS pipe, diode, NPN pipe and PNP pipe.
Further, it will be appreciated by those skilled in the art that integrated circuit provided by the invention can be various types of circuit, and change according to concrete enforcement needs.In other words, the scheme that all need can adopt the foregoing description to provide to the integrated circuit that static discharge protects, for example chip such as various processors.Particularly, those skilled in the art can be in conjunction with prior art and above-mentioned enforcement, change example realizes such integrated circuit, does not repeat them here.
More than specific embodiments of the invention are described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, those skilled in the art can make various distortion or modification within the scope of the claims, and this does not influence flesh and blood of the present invention.
Claims (16)
1. improved electrostatic discharge protective device, be used to eliminate the electric current that flows through the ESD protective device when normally powering on, comprise testing circuit, drive circuit and discharge tube, wherein, described drive circuit comprises one or more levels inverter, and the afterbody inverter is the CMOS inverter, wherein, described CMOS inverter comprises load pipe and driving tube, it is characterized in that, is connected with first bleeder circuit between described load pipe and the driving tube.
2. electrostatic discharge protective device according to claim 1 is characterized in that, described first bleeder circuit comprises at least one the first transistor.
3. electrostatic discharge protective device according to claim 2, it is characterized in that, described the first transistor is the PMOS pipe, wherein, the source electrode of described PMOS pipe connects the drain electrode of described load pipe, the drain electrode of described PMOS pipe connects the drain electrode of described driving tube, and the grid of described PMOS pipe is connected with drain electrode, and the grid of described discharge tube is connected with the drain electrode or the source electrode of described PMOS pipe.
4. electrostatic discharge protective device according to claim 2, it is characterized in that, described the first transistor is the NMOS pipe, wherein, the drain electrode of described NMOS pipe connects the drain electrode of described load pipe, the source electrode of described NMOS pipe connects the drain electrode of described driving tube, and the grid of described NMOS pipe is connected with drain electrode, and the grid of described discharge tube is connected with the source electrode or the drain electrode of described NMOS pipe.
5. electrostatic discharge protective device according to claim 2, it is characterized in that, described the first transistor is a diode, wherein, the positive pole of described diode connects the drain electrode of described load pipe, the negative pole of described diode connects the drain electrode of described driving tube, and the grid of described discharge tube is connected with the negative or positive electrode of described diode.
6. electrostatic discharge protective device according to claim 2, it is characterized in that, described the first transistor is the NPN pipe, wherein, the collector electrode of described NPN pipe connects the drain electrode of described load pipe, the emitter of described NPN pipe connects the drain electrode of described driving tube, and the base stage of described NPN pipe is connected with collector electrode, and the grid of described discharge tube is connected with the collector electrode or the emitter of described NPN pipe.
7. electrostatic discharge protective device according to claim 2, it is characterized in that, described the first transistor is the PNP pipe, wherein, the emitter of described PNP pipe connects the drain electrode of described load pipe, the collector electrode of described PNP pipe connects the drain electrode of described driving tube, and the base stage of described PNP pipe is connected with collector electrode, and the grid of described discharge tube is connected with the emitter or the collector electrode of described PNP pipe.
8. electrostatic discharge protective device according to claim 2, it is characterized in that, described the first transistor comprises a plurality of PMOS pipes, wherein, be connected across after the series connection of described a plurality of PMOS pipe between the drain electrode of the drain electrode of described load pipe and described driving tube, the grid of described PMOS pipe is connected with drain electrode, and the grid of described discharge tube is connected with the drain electrode of described load pipe or the drain electrode of described driving tube.
9. electrostatic discharge protective device according to claim 2, it is characterized in that, described the first transistor comprises a plurality of NMOS pipes, wherein, be connected across after the series connection of described a plurality of NMOS pipe between the drain electrode of the drain electrode of described load pipe and described driving tube, the grid of described NMOS pipe is connected with drain electrode, and the grid of described discharge tube is connected with the drain electrode of described load pipe or the drain electrode of described driving tube.
10. electrostatic discharge protective device according to claim 2, it is characterized in that, described the first transistor comprises a plurality of diodes, wherein, be connected across after the described a plurality of diode series connection between the drain electrode of the drain electrode of described load pipe and described driving tube, the grid of described discharge tube is connected with the drain electrode of described load pipe or the drain electrode of described driving tube.
11. electrostatic discharge protective device according to claim 2, it is characterized in that, described the first transistor comprises a plurality of NPN pipes, wherein, be connected across after the series connection of described a plurality of NPN pipe between the drain electrode of the drain electrode of described load pipe and described driving tube, the base stage of described NPN pipe is connected with collector electrode, and the grid of described discharge tube is connected with the drain electrode of described load pipe or the drain electrode of described driving tube.
12. electrostatic discharge protective device according to claim 2, it is characterized in that, described the first transistor comprises a plurality of PNP pipes, wherein, be connected across after the series connection of described a plurality of PNP pipe between the drain electrode of the drain electrode of described load pipe and described driving tube, the base stage of described PNP pipe is connected with collector electrode, and the grid of described discharge tube is connected with the drain electrode of described load pipe or the drain electrode of described driving tube.
13. one kind is used to eliminate the control method that flows through the electric current of electrostatic discharge protection component when normally powering in improved electrostatic discharge protective device, it is characterized in that, comprises step:
A. during normally powering on, provide grid potential to discharge tube; And
B. discharge tube is in not on-state under the control of described grid potential.
14. an integrated circuit comprises power pins, internal circuit and ESD protection circuit, it is characterized in that, also comprises first bleeder circuit that is used for controlling ESD protection circuit discharge tube grid potential.
15. integrated circuit according to claim 14 is characterized in that, described first bleeder circuit comprises the first transistor.
16. integrated circuit according to claim 15 is characterized in that, described the first transistor comprises any in one or more following transistors:
-PMOS pipe;
-NMOS pipe;
-diode;
-NPN pipe; And
-PNP pipe.
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| CN200910051382XA CN101707196B (en) | 2009-05-15 | 2009-05-15 | Improved electrostatic discharge protective device, corresponding method and integrated circuit |
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| CN200910051382XA CN101707196B (en) | 2009-05-15 | 2009-05-15 | Improved electrostatic discharge protective device, corresponding method and integrated circuit |
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| CN101707196B CN101707196B (en) | 2011-12-21 |
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| US6556398B1 (en) * | 1999-10-05 | 2003-04-29 | Winbond Electronics Corporation | Voltage tolerance ESD protection circuit |
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