CN101702184B

CN101702184B - Dynamic reconfigurable bus macrostructure

Info

Publication number: CN101702184B
Application number: CN2009101990559A
Authority: CN
Inventors: 杨华秋; 来金梅
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2009-11-19
Filing date: 2009-11-19
Publication date: 2012-05-30
Anticipated expiration: 2029-11-19
Also published as: CN101702184A

Abstract

The invention belongs to the technical field of micro-electronics, in particular to a bus macrostructure based on PGA of longitudinal CLB and applied to dynamic reconfigurable hardware. CLB units of the bus macro have four types of configurations which respectively correspond to four directions of signal transmission, i.e. from left to right, from right to left, from top to bottom and from bottom to top, wherein two types of macros having horizontal trend can be used as bus macros in the same line and used for longitudinally cutting the circuit; and two types of macros having vertical trend can be used as bus macros in the same row and used for horizontally cutting the circuit. The bus macrostructure can accurately, physically and longitudinally or transversely cut a reconfigurable hardware circuit in the PGA into a fixed logic and a dynamic reconfigurable logic, thereby ensuring that the reconfigurable logic does not influence the fixed logic part when being reconfigured by an external circuit.

Description

Dynamic reconfigurable bus macrostructure

Technical field

The invention belongs to microelectronics technology, be specifically related to the required bus macrostructure of a kind of dynamic reconfigurable hardware, relate in particular to a kind of interior bus macrocircuit structure of FPGA that is used for vertical CLB structure.

Background technology

Dynamic reconfigurable hardware platform (DynamicallyReconfigurable Hardware Platform) [1 based on FPGA (Field Programmable Gate Array); 2] be the configurable characteristic that utilizes FPGA; In conjunction with certain circuit structure; Through the inner partial function of dynamic recognition fpga chip, utilize the FPGA internal resource thereby reach timesharing, on-the-fly modify the purpose of FPGA function.The dynamic reconfigurable hardware platform of FPGA improves the adaptive faculty and the stability of system in the utilization factor that improves fpga chip, and reducing aspects such as system redundancy and power consumption has performance preferably.

Based on the realization of the dynamic reconfigurable platform of FPGA the consideration of following aspect being arranged, is respectively hardware carrier---fpga chip; Reconstruct implementation---control interface; The reconfigurable circuit system architecture---based on module or based on difference, and the circuit structure method etc.; The algorithm of reconstruct and application---feedback and control foundation.The present invention pays close attention to the reconfigurable hardware system based on module.In the reconfigurable hardware system based on module; The technology of a key be will with reconfigurable circuit module from physically with the fixed logic module segmentation of not participating in reconstruct, and module and fixed logic intermodule after the reconstruct are kept and the identical interface position of reconstruct front module.A kind of feasible scheme is to accomplish the interface interconnection of intermodule in the reconfigurable system through fixing bus structure.

The Xilinx of fpga chip design corporation provides complete hardware and software development platform to be used to realize the dynamic reconfigurable system, and to based on aspect the reconfigurable circuit system architecture of module, it is grand to the bus of different series chip that Xilinx provides.Wherein, for FPGA family chip, like the Virtex-II family chip based on horizontal CLB; It provides by the bus of CLB and interconnect fabric grand (Bus Macro) [2,4], is used for the dividing inner module; And for the FPGA family chip based on vertical CLB; Like Viertex and SPARTAN-IIE family chip, the bus grand [2,3] by the TBUF structure only is provided then.Have more dirigibility and more save resource by the bus of CLB structure is grand, so be necessary to be configured to based on the bus of the FPGA of vertical CLB grand.

List of references:

[1]Application?Note?XAPP290(V1.0)：Virtex，Virtex-E，Virtex-II，Virtex-IIPro?Families

[2]Xilinx?Inc.PlanAhead?User?Guide

[3]Xilinx，Inc.，Spartan/Spartan-II/Spartan-3FPGA?Family?Complete?DataSheet

[4]Xilinx，Inc.，Virtex/Virtex-II/Virtex-4/Virtex-5FPGA?Family?CompleteData?Sheet.

[5]Guanghua?Pan，Jinmei?Lai，Liguang?Chen，“Design?and?implementation?ofsequential?function?of?CLB?in?FPGA”，Electronic?Journal，2008.(08).

Summary of the invention

The objective of the invention is to the FPGA that has used vertical CLB unit and interconnection, it is grand to propose a kind of bus of CLB resource structure of utilizing, and is used for cutting apart the disparate modules of dynamic reconfigurable system.

Vertical physics and the logical organization as shown in Figure 1 [5] of CLB in FPGA, the input MUX (IMUX) of CLB and output MUX (OMUX) lay respectively at below and the top of SLICE, and the signal trend is for vertical.Haply, signal upwards gets into IMUX (Input MUX) through GRM (General Routing MUX), upwards gets into SLICE again, more upwards through OMUX (Output MUX) output.According to the requirement of dynamic reconfigurable hardware system, each module is as shown in Figure 2, and from physically being divided into longitudinal strip, the sideband signal transmission direction is horizontal.It is thus clear that, in order to make the signal lateral transport, must utilize horizontal interconnection line, and this interconnection gauze to appear at about two row CLB in.Based on the bus of CLB grand through exampleization adjacent two be listed as CLB as the transition logic; And the interconnection that retrains between these two row CLB makes it when linking to each other with any circuit, all to fix; Just can with these two row CLB as about the border of two modules, thereby the realization Circuits System is physically by vertical cutting.

The present invention utilizes the adjacent CLB of two row as bus is grand circuit vertically to be cut apart, wherein as the grand CLB configuration of cells of bus shown in Fig. 3-1～Fig. 3-4, have four kinds of macroelements, be used for vertically or transverse cuts circuit.Fig. 3-1 is depicted as side signal transmission to the bus macroelement that uses for from left to right the time, is designated as the A unit.Fig. 3-2 is depicted as side signal transmission to the bus macroelement for when turn left in the right side, using, and is designated as the B unit.Fig. 3-3 is depicted as side signal transmission to the bus macroelement that uses for from top to bottom the time, is designated as the C unit.Fig. 3-4 is depicted as side signal transmission to the bus macroelement that uses for from the bottom up the time,, be designated as the D unit.Two kinds of grand can being used for circuit is vertically cut of level trend wherein as the grand use of same column bus; Two kinds of grand can being used for circuit level is cut of capwise as the grand use of same row bus.Each bus macroelement comprises input border SLICE and two SLICE of output boundary SLICE, fixes from the ICR interconnect resource that the input that outputs to output boundary SLICE of input border SLICE is used.

The logic function of bus macroelement is direct-connected line, and the logical resource of use comprises LUT (Look Up Table, look-up table) and the fixed interconnection resource of using from the input that outputs to output boundary SLICE of input border SLICE.LUT is configured to direct-connected logic.The grand principle that LUT is used of bus is: the use that outputs to output boundary SLICE interconnection line of input border SLICE: do not use the resource of GRM, Pin is to using the ICR interconnect resource of minimum progression between Pin as far as possible.So in four macroelements shown in Fig. 3-1～Fig. 3-4, the fixing ICR interconnect resource that uses is: in A unit and the B unit, the LUT output of input border SLICE directly gets into the most contiguous port of IMUX under the output boundary SLICE through OMUX.In the D unit, utilize the high-speed carry chain to realize interconnection from the bottom up.In the C unit, because vertically the CLB structure can only be accomplished interconnection through GRM to unfavorable by following signal transmission down.Fig. 3-1 is the grand fixed logic that will use of bus to Fig. 3-4 bend mark part, and the remainder logical resource all is open, and other parts of system can be used.

This bus macrostructure that the present invention proposes accurately is divided into fixed logic and dynamic reconfigurable logic with the reconfigurable hardware circuit in the FPGA from physically vertical or horizontal, thereby makes reconfigurable logic by external circuit reconstruct the time, not influence the fixed logic part.

Owing to the resource among the FPGA that has reasonably used vertical CLB structure, the bus macrostructure that the present invention proposes not only is easy to realize, and can makes signal reach the purpose that reduces time-delay through rational interconnection.The strip bus that the summary macroelement that puts forward based on the present invention is formed; Can be with the vertical perhaps horizontal partition of FPGA inner circuit system; Then through generating the part bit stream of a plurality of reconfigurable modules; Accomplish the needed hardware resource of dynamic reconfigurable system, cooperate external control, realize the dynamic reconfigurable hardware platform.

Description of drawings

The vertical CLB structural representation of Fig. 1.

Fig. 2 reconfigurable hardware circuit system structural drawing.

Fig. 3-1 bus macroelement from left to right.

The bus macroelement that Fig. 3-2 turns left from the right side.

Fig. 3-3 bus macroelement from top to bottom.

Fig. 3-4 bus macroelement from the bottom up.

Fig. 4 dynamic reconfigurable platform construction process flow diagram.

Embodiment

The bus macrostructure that the present invention proposes embodies value in the application of dynamic reconfigurable, cooperate overall flow to play a role.

The bus macrostructure that utilizes the present invention to propose realizes that the concrete steps of dynamic reconfigurable hardware are as shown in Figure 4, specifically describes as follows:

(1) circuit module is divided.Circuit is divided module; Top-level module is just by constituting with lower module: stuck-module, first reconfigurable module, second reconfigurable module; First bus is grand; Second bus is grand etc., and wherein all of the port of reconfigurable module all should link to each other with other modules through bus is grand, and all of the port signal all should be unidirectional.

(2) module position constraint.Be constrained to rational zone with all modules and bus are grand, generally recommend each module all to be constrained to strip longitudinally, through the logic interconnection of the grand completion level trend of bus longitudinally.If needed, also can use the vertically interconnection of trend of the grand realization of horizontal bus.

(3) generate overall bitstream.

(4) revise reconfigurable module, generate a plurality of overall bitstream and extract the part bit stream or directly generate restructural part bit stream.The part bit stream should comprise grand half the, as shown in Figure 2 of reconfigurable logic circuit and bus.

Through the external control logic, on demand the part bit stream is used for the circuit in the dynamic restructuring FPGA, make it timesharing and accomplish different task.

Claims

1. dynamic reconfigurable bus macrostructure based on the on-site programmable gate array FPGA of vertical CLB; It is characterized in that utilizing the adjacent CLB of two row as bus is grand circuit vertically to be divided into fixed logic and dynamic reconfigurable logic, the grand CLB configuration of cells of said bus has 4 kinds: side signal transmission is designated as the A unit to the bus macroelement for time use from left to right; Side signal transmission is to the bus macroelement for when turn left in the right side, using; Be designated as the B unit, side signal transmission is designated as the C unit to being the bus macroelement that uses from top to bottom the time; Side signal transmission is designated as the D unit to being the bus macroelement that uses from the bottom up the time; Two kinds of grand can being used for circuit is vertically cut of level trend as the grand use of same column bus; Two kinds of grand can being used for circuit level is cut of capwise as the grand use of same row bus; Each bus macroelement comprises input border SLICE and two SLICE of output boundary SLICE, fixes from the ICR interconnect resource that the input that outputs to output boundary SLICE of input border SLICE is used;

In 4 bus macroelements, the fixing ICR interconnect resource that uses is: in A unit and the B unit, the look-up table output of input border SLICE directly gets into the most contiguous port of input MUX under the output boundary SLICE through the output MUX; In the D unit, utilize the high-speed carry chain to realize interconnection from the bottom up; In the C unit, accomplish interconnection through general wiring matrix;

Wherein, CLB represents configurable logic blocks, and SLICE represents logic chip.