CN102411655A

CN102411655A - Internal line connection method for field-programmable gate array

Info

Publication number: CN102411655A
Application number: CN2011102550854A
Authority: CN
Inventors: 孙铁力
Original assignee: GUOWEI ELECTRONICS CO Ltd SHENZHEN
Current assignee: GUOWEI ELECTRONICS CO Ltd SHENZHEN; Shenzhen State Micro Electronics Co Ltd
Priority date: 2011-08-31
Filing date: 2011-08-31
Publication date: 2012-04-11

Abstract

The invention provides an internal line connection method for a field-programmable gate array. The method comprises the following steps of: dividing internal modules of the field-programmable gate array along edges of the internal modules; constructing, namely constructing transverse connection modules and longitudinal connection modules according to the types of the internal modules respectively; and connecting, namely connecting the internal modules in turn by using the transverse connection modules which are connected with the internal modules in a transverse direction and the longitudinal connection modules which are connected with the internal modules in a longitudinal direction, wherein the transverse connection modules and the longitudinal connection modules comprise at least one of internal connection lines of which the starting points are inside the internal modules, access connection lines which are connected with the inner part of the internal modules and the edges of the internal modules, and cross connection lines of which the start points are inside the edges of the internal modules respectively.

Description

A kind of method of on-site programmable gate array internal interconnection line

Technical field

The present invention relates to a kind of method of on-site programmable gate array internal interconnection line.

Background technology

FPGA (Field-Programmable Gate Array; Be field programmable gate array) comprising: by LUT (the Lookup Table that realizes user logic; Be look-up table), trigger and latch; And MUX (Multiplexer, MUX) and the interconnection line of realizing annexation.EDA (Electronic Design Automation, i.e. electric design automation) instrument will be an emphasis to FPGA top layer interconnection modeling wherein to will be to each module modeling of FPGA, the top layer interconnections:

COUNT _INTER=K _INTER* TILE _COUNTX* TILE _COUNTY(formula 1),

TILE wherein _COUNTXAnd TILE _COUNTXFunctional unit (internal module) array size of representing FPGA respectively, K _INTERBe the related interconnection line number of each functional unit, relevant with the interconnection line framework, scope generally is 90 to 400, for example, in the Virtex2 of Xilinx company series, its K _INTERApproximate 300.

Among the commercial FPGA of main flow, K _INTER>=300, TILE _COUNTY* TILE _COUNTY>=104, and along with the progress of technology, three coefficients also can increase.

Along with the expansion of the internal module array of FPGA, several ten thousand in addition millions of between linear growth, and along with the complicacy of FPGA structure, K _INTERBecome big, the speed of growth becomes faster.Conventional interconnection line model has two kinds: a kind of is to the every independent modeling of interconnection line, spatially or be not good selection on the processing time; Another kind is the interconnection line that merges same type, but because the difference on interconnection line logic and the view, the feasible interconnection line model of handling becomes complicated, and is difficult to improve the complexity of the problems referred to above, the commercial FPGA of the big array of intractable.

Summary of the invention

Technical matters to be solved by this invention is the method that proposes a kind of interconnection line efficiently.

To this, the invention provides a kind of interconnection line method of attachment of the FPGA internal module that can efficiently carry out.

A kind of method of on-site programmable gate array internal interconnection line comprises the steps:

Partiting step: the internal module of field programmable gate array is scratched along its edge respectively;

Constitution step: according to the type of said internal module; Respectively it is constructed horizontal link block and vertical link block; Said horizontal link block comprises respectively with vertical link block: initial all at the inner internal connection line of this internal module, be connected the access connecting line at inside and this internal module edge of this internal module and initial all at least a in the connecting line of passing through at this internal module edge respectively;

Connection Step: said internal module respectively through with its connection horizontal to the horizontal link block that is connected, and interconnect successively with its vertical link block that vertically is connected;

Wherein, the said internal connection line on the said horizontal link block, the two-end-point that inserts connecting line and pass through connecting line are distributed in respectively on the dual-side of this horizontal link block; Said internal connection line on said vertical link block, the two-end-point that inserts connecting line and pass through connecting line are distributed in respectively on the both sides up and down of this vertical link block.

Compared with prior art the invention has the advantages that; Because with the functional unit is the minimum unit of describing; Its quantity does not change with the fpga chip array size; Only relevant with the kind (Family) of device, like this can maximized simplification internal module line, improved the efficient of connecting line greatly.

Specifically; The present invention is divided into three types with the interconnection line fragment: at the interconnection line (LINEINNER) of functional unit internal start and termination; Perhaps starting from functional unit inside ends at the interconnection line at functional unit edge (LINEINTER) in functional unit inside to originate in the functional unit edge termination; Initial sum stops all at the interconnection line at functional unit edge, comprises linking the inner interconnection line (LINETHROUGH) of functional unit simultaneously.

The model of describing interconnection line mainly comprises two aspects, is respectively the net table of indication interconnection line logic connecting relation and describes the pattern that interconnection line shows (be PATTERN, can with reference to the FPGA Editor of Xilinx company) in explicit function GUI ().Wherein the interconnection line logic connecting relation is that the initial sum terminating point of PATTERN confirms that by the interconnection line logic connecting relation we can revise the position of intermediate point by the decision of interconnection line architect.The present invention is that interconnection line is broken off on the border according to the characteristics of the array height repetition of FPGA with the functional unit, comes simplified model in the interconnection line fragment of the identical Pattern of functional unit built.

For example; Repeatability according to FPGA; The functional unit of chip is divided into configuration logic (CLB), interface block (IOB); Piece is stored functional units such as (BRAM) at random, and target is to make the interconnection line Pattern in the functional unit of same type consistent, and guarantees when functional unit splices, can the interconnection line fragment assembly be become complete interconnection line.So only need the interconnection line fragment in the representation function unit, mean that same Family can shared these descriptions.

Preferably, the type selecting of said internal module adopts configuration logic, and interface block or piece are stored at random.

Description of drawings

Fig. 1 is the common Double line rough schematic view of industry.

Fig. 2 is the result of partition functionality unit in an embodiment of the present invention.

Fig. 3 is that two converters are realized laterally (F1) and vertically (F2) link block in an embodiment of the present invention.

Fig. 4 is the functional unit synoptic diagram that adds horizontal and vertical link block in an embodiment of the present invention.

Fig. 5 is the result of splicing with the functional unit of constructing among Fig. 4 embodiment.

Embodiment

Below in conjunction with accompanying drawing, more excellent embodiment of the present invention is done further detailed description:

Fig. 1 is common Double line synoptic diagram, and the Double line connects three MUX on the horizontal direction, has indicated each MUX among the figure and has sent a Double line on the N/S/W/E four direction, receives two Double lines on the N/S/W/E four direction simultaneously.Can be known that by figure the pattern of interconnection line (PATTERN) is quite complicated, the PATTERN sum is identical with the quantity of Double line.

Fig. 2 is the result of partition functionality unit, can be known by figure:

COUNTCORNER=0，

COUNTEDGE=0，

COUNTNEDGE=COUNTSEDGE=4，

COUNTEEDGE=?COUNTWEDGE?=?4，

Satisfy the requirement of formula 2.

Fig. 3 is that two converters are realized F1 and F2.Wherein F1 is that horizontal direction is W to E, the perhaps converter of E to W direction, and F2 is that vertical direction is N to S, the perhaps converter of S to N direction, the order of exchange interconnection line fragment can be simplified the structure of converter.

Inner at functional unit; The interconnection line fragment is divided into three types: at the interconnection line (LINEINNER) of functional unit internal start and termination; Perhaps starting from functional unit inside ends at the interconnection line at functional unit edge (LINEINTER) in functional unit inside to originate in the functional unit edge termination; Initial sum stops all at the interconnection line at functional unit edge, comprises linking the inner interconnection line (LINETHROUGH) of functional unit simultaneously.

For ∨ Line ∈ LINEINNER, only Pattern is consistent in the needs assurance identical functions unit gets final product.For ∨ Line ∈ LINEINTER, need to guarantee that Pattern is consistent in the identical functions unit, also to satisfy a functional unit point on the edge of and want correct splicing.For ∨ Line ∈ LINETHROUGH, need to guarantee that Pattern is consistent in the identical functions unit, also to satisfy functional unit a plurality of points on the edge of and want correct splicing.The condition of preceding two kinds of Line is easier to satisfy; For ∨ Line ∈ LINETHROUGH; In the partition functionality unit; The quantity that ∨ Line drops on the point on the functional unit edge to satisfy COUNTCORNER=0 && COUNTEDGE=0 && COUNTNEDGE=COUNTSEDGE &&COUNTEEDGE=COUNTWEDGE} (formula 2), and promptly for any one interconnection line fragment not point drop on the corner, do not have the interconnection line fragment to drop on the limit; And the quantity that drops on the point on N/S or the W/E direction will equate respectively that these three conditions can satisfy through the position of adjustment partition functionality unit basically.In the splicing functional unit, let the correct combination of interconnection line fragment, can know in conjunction with formula 2, must have that surjection F1:{NEDGE}-{ SEDGE} and F2:{WEDGE}-{ EEDGE} (formula 3) satisfies condition.Therefore can realize F1 and F2, the condition when satisfying splicing at virtual converter of the inner placement of functional unit.

Fig. 4 is the functional unit unit that adds behind two converters, can find out through on the converter back edge name a person for a particular job with reciprocal certain a bit be positioned at same delegation (horizontal direction) or same row (vertical direction).

Fig. 5 is the result of splicing with the functional unit of constructing, and is of equal value with the interconnection line of figure one.

The implementation method of this implementation is: 1. the logic connecting relation of describing the top layer interconnection line.2. define each minimum repetitive functional unit.3. design level and vertical converter.4. splice each functional unit.

The embodiment of Fig. 5 can also further be optimized, and has reduced the intersection between the interconnection line, makes circuit diagram more directly perceived.

Above content is to combine concrete preferred implementation to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace, all should be regarded as belonging to protection scope of the present invention.

Claims

1. the method for an on-site programmable gate array internal interconnection line is characterized in that, comprises the steps:

2. the method for on-site programmable gate array internal interconnection line as claimed in claim 1 is characterized in that, the type of said internal module comprises: configuration logic, interface block, piece is stored at random.

3. according to claim 1 or claim 2 the method for on-site programmable gate array internal interconnection line is characterized in that said internal module is a rectangle.

4. the method for on-site programmable gate array internal interconnection line as claimed in claim 3 is characterized in that, said horizontal link block is a rectangle.

5. the method for on-site programmable gate array internal interconnection line as claimed in claim 3 is characterized in that, said vertical link block is a rectangle.