CN104536755B - Programmable logic device reconstructing method and device - Google Patents
Programmable logic device reconstructing method and device Download PDFInfo
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- CN104536755B CN104536755B CN201410835994.9A CN201410835994A CN104536755B CN 104536755 B CN104536755 B CN 104536755B CN 201410835994 A CN201410835994 A CN 201410835994A CN 104536755 B CN104536755 B CN 104536755B
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Abstract
A kind of programmable logic device reconstructing method of the present invention and device, this method comprises: determining the resource-area to be reconstructed of programmable logic device；Resource dividing to be reconstructed is divided at least one basic unit, basic unit includes at least one reconfigurable device；Each basic unit is reconstructed respectively.Implementation through the invention, the resource-area to be reconstructed in programmable logic device is determined as needed, and it is divided into basic unit, each basic unit is reconstructed respectively, realize using basic unit as the reconfiguration technique of minimal reconstruction unit, with it is existing using basic device compared with the reconfiguration technique of minimal reconstruction unit, minimal reconstruction range increases, required control signal and number of data streams will all be reduced when reconstruct, reduce many and diverse degree of device and reconfiguration cost of programmable logic device.
Description
Technical field
The present invention relates to the application field of programmable logic device, a kind of particularly programmable logic device reconstruct side
Method and device.
Background technique
For programmable logic such as FPGA (Field-Programmable Gate Array, field programmable gate array)
Device, it is only necessary to which desired circuit function can be obtained by being converted designed circuit to after bit stream file imports by developing instrument
Can, flow cost is saved compared with special purpose logic devices, and more flexible, repeat programming to realize Different Logic function
Energy.
Programmable logic device can also have some disadvantages while user-friendly, such as use 7000 system of zynq
When the SoC FPGA of column carries out circuit design, existing FPGA Reconfiguration Technologies are by the way of configuring frame, to basic logic unit
(basic devices such as look-up table, trigger, CLB, IOB) realize fine-grained reconstruct, and this mode is needed according to target after reconstruct
The bit stream file of circuit evolving whole circuit, and the bit stream data that reconstruct needs, these basic devices are sent to these basic devices
It updates configuration and completes reconstruct, this kind of fpga chip structure design realizes that difficulty is big, chip area is big, chip cost is high.
Therefore, how a kind of programmable logic device reconfiguration technique having lower cost is provided, is those skilled in the art
Member's technical problem urgently to be resolved.
Summary of the invention
The present invention provides a kind of programmable logic device reconstructing method and devices, to reduce the weight of programmable logic device
Constitute this.
The present invention provides a kind of programmable logic device reconstructing methods, in one embodiment, this method comprises: determining
The resource-area to be reconstructed of programmable logic device；Resource dividing to be reconstructed is divided at least one basic unit, basic unit packet
Include at least one reconfigurable device；Each basic unit is reconstructed respectively.
Further, the basic unit in above-described embodiment further includes restructural between reconfigurable device and other devices
Connection.
Further, the reconfigurable device in above-described embodiment includes configurable logic blocks CLB.
Further, in above-described embodiment will resource dividing be reconstructed be divided at least one basic unit include: by
It reconstructs resource-area and is divided at least one basic unit according to physical region；Alternatively, will resource-area be reconstructed according to physical region
And objective function is divided at least one basic unit.
Further, the objective function in above-described embodiment includes: the function that basic unit needs to realize, or wait reconstruct
Resource-area needs the function of realizing.
Further, each basic unit being reconstructed respectively in above-described embodiment includes: to be distinguished according to objective function
Generate the new bit stream file of each basic unit；The new bit stream file of each basic unit is configured to corresponding basic unit.
The present invention provides a kind of programmable logic device to reconstruct device, and in one embodiment, which comprises determining that
Module, for determining the resource-area to be reconstructed of programmable logic device；Division module, for will resource dividing be reconstructed be divided into
A few basic unit, basic unit includes at least one reconfigurable device；Reconstructed module, for respectively to each basic unit into
Row reconstruct.
Further, the basic unit in above-described embodiment further includes restructural between reconfigurable device and other devices
Connection.
Further, the reconfigurable device in above-described embodiment includes configurable logic blocks CLB.
Further, the division module in above-described embodiment is specifically used for: resource-area to be reconstructed is drawn according to physical region
It is divided at least one basic unit；Alternatively, resource-area to be reconstructed according to physical region and objective function is divided at least one
Basic unit.
Further, the objective function in above-described embodiment includes: the function that basic unit needs to realize, or wait reconstruct
Resource-area needs the function of realizing.
Further, the reconstructed module in above-described embodiment is specifically used for generating each basic unit respectively according to objective function
New bit stream file；The new bit stream file of each basic unit is configured to corresponding basic unit.
Beneficial effects of the present invention:
Scheme provided by the invention determines the resource-area to be reconstructed in programmable logic device, and its stroke as needed
Be divided into basic unit, basic unit includes at least one reconfigurable device, these reconfigurable devices after bit stream data is written just
Basic logic function may be implemented, i.e., each basic unit can realize some functions of objective circuit, on this basis,
Each basic unit is reconstructed respectively, is realized using basic unit as the reconfiguration technique of minimal reconstruction unit, with existing with base
This device is that the reconfiguration technique of minimal reconstruction unit is compared, and minimal reconstruction range increases, when reconstruct required control signal and
Number of data streams will all be reduced, and reduce many and diverse degree of device and reconfiguration cost of programmable logic device.
Detailed description of the invention
Fig. 1 is the flow chart for the programmable logic device reconstructing method that first embodiment of the invention provides；
Fig. 2 is the schematic diagram that the programmable logic device that second embodiment of the invention provides reconstructs device；
Fig. 3 is the flow chart for the programmable logic device reconstructing method that third embodiment of the invention provides；
Fig. 4 is the partiting step schematic diagram of FPGA device in third embodiment of the invention；
Fig. 5 is the reconstruct schematic diagram of resource-area to be reconstructed in third embodiment of the invention；
Fig. 6 is the realization schematic diagram of single basic unit in third embodiment of the invention.
Specific embodiment
Further annotation explanation now is made to the present invention by way of specific embodiment combination attached drawing.
First embodiment:
Fig. 1 is the flow chart for the programmable logic device reconstructing method that first embodiment of the invention provides, as shown in Figure 1,
In the present embodiment, programmable logic device reconstructing method provided by the invention the following steps are included:
S101: the resource-area to be reconstructed of programmable logic device is determined；
This step supports the restructural resource-area of dynamic restructuring firstly the need of determining in programmable logic device, programmable to patrol
There are many type for collecting device, and the present invention is illustrated by taking FPGA as an example: user is according to Attributions selections such as the complexities of objective circuit
The FPGA is divided into restructural resource-area and not restructural resource-area, restructural resource-area and refers to this by the FPGA of certain model
Resource in region has dynamic reconfigurable, different bit stream datas can be written not by time division multiplexing in circuit operation
Different functions is realized with the time, not restructural resource-area refers to that the resource in the region does not support dynamic to be written in circuit operation
Bit stream data is to realize different functions.
After user selectes FPGA as needed, restructural resource-area on device can be learnt according to device specification
Range, then user can function according to the reconstruct sub-circuit in the objective circuit of desired change and restructural resource-area
Range determines one or more resource-areas to be reconstructed on device, and resource-area to be reconstructed can be the one of restructural resource-area
It partially (fully belongs to restructural resource-area), also may include that the not restructural resource-area in partial reconfigurable resource-area and part (is used
The circuit function of reconstruct is not needed in realization objective circuit).
S102: resource dividing to be reconstructed is divided at least one basic unit, basic unit includes that at least one is restructural
Device；
It is determining after reconstructing resource-area, will drawn wait reconstruct the resource in resource-area (including CLB, editable interconnection line etc.)
It is divided at least one basic unit, each basic unit includes at least one reconfigurable device (such as CLB), thus can be
Some basic functions are realized after write-in bit stream file.
Reconfigurable device quantity between different basic units can be different, can be real according to required for the basic unit
Existing objective function is divided, if the objective function that certain basic units need to realize is simple, can only include
One reconfigurable device, it is corresponding, if the objective function that some basic units need to realize is more complicated, so that it may including more
The reconfigurable device of quantity.
It in some embodiments, is each subfunction point in the objective function of realization required for objective circuit for the ease of user
With corresponding basic unit, can be set to each basic unit includes that (these are restructural for the reconfigurable device of identical quantity
Device, which cooperates, may be implemented some small functions of objective circuit), ensure that each basic unit in write-in bit stream in this way
Can realize certain function after data, and the restructural resource that has of each basic unit be it is identical, in this base
On plinth, so that it may objective circuit is decomposed into many small functions, and is the corresponding basic unit of these small function distributions, without
First judge the complexity that function small in this way is realized, in the division for carrying out basic unit, division mode is simple.
S103: being respectively reconstructed each basic unit, can by developing instrument by the bit stream file of objective circuit about
Beam is realized to basic unit.
In some embodiments, the basic unit in above-described embodiment further include can between reconfigurable device and other devices
The connection of reconstruct.In practical applications, reconfigurable device needs to be communicated with other devices at work, such as complete
At the work-based logic relationship etc. between the acquisition of bit stream file, reconfigurable device, the present embodiment is by by reconfigurable device and its
Restructural connection is also divided into basic unit between his device, so that the function of basic unit is more complete, it is restructural
Connection include editable interconnection line, IOB resource etc..
In some embodiments, by taking FPGA device as an example, the reconfigurable device in above-described embodiment is configurable logic mould
Block CLB, the restructural resource type certainly in some special application fields, used FPGA device is different, corresponding,
Reconfigurable device is exactly the restructural resource in this kind of FPGA device.
In some embodiments, resource dividing to be reconstructed is divided at least one basic unit packet in above-described embodiment
It includes: resource-area to be reconstructed according to physical region is divided at least one basic unit；Alternatively, will resource-area be reconstructed according to object
Reason region and objective function are divided at least one basic unit.The division mode for present embodiments providing basic unit, according to
Physical region is divided or is divided according to physical region and objective function, so that all devices in basic unit are in physical bit
It is continuous for setting, and this reduces many and diverse degree of communication between device each in basic unit, is thereby reduced according to basic
The length of bit stream data and many and diverse degree in the objective function of unit bit stream file generated, reduce realize it is restructural at
This.
It in some embodiments, is adjacent, and nonoverlapping between two basic units in above-described embodiment；When
So it is also possible to be spaced certain area, control can be had by the way that setting bit stream file realization is some by being spaced such that in region
The fixation sub-circuit of the functions such as system, storage.
In some embodiments, certain basic unit in above-described embodiment includes multiple (two or more) reconfigurable devices
When, the types of these reconfigurable devices be on needing the objective function realized it is associated, as basic unit needs to realize electricity
When the functions such as resistance and capacitor, internal components can include restructural resistance and capacitor etc..
In some embodiments, the objective function in above-described embodiment includes: the function that basic unit needs to realize, or
Resource-area to be reconstructed needs the function of realizing.Basic unit needs the function of realizing to refer in objective circuit, basic unit institute
The corresponding function of the bit stream file of write-in, when such as realizing the resistance function of a specific resistance value, basic unit, which includes one, to be weighed
Structure device and corresponding communication line.Resource-area to be reconstructed needs the function of realizing to refer to that objective circuit is needed wait reconstruct
The function that resource-area is realized, these functions can be made of multiple subfunctions, carry out drawing for basic unit according to these subfunctions
Point, so that each basic unit can realize corresponding subfunction, obtained basic unit is divided so functionally independently,
Reconstruct is simple.
In some embodiments, each basic unit being reconstructed respectively in above-described embodiment includes: according to target function
The new bit stream file of each basic unit can be generated respectively；The new bit stream file of each basic unit is configured to corresponding basic
Unit.New bit stream file refers to basic unit information such as required bit stream data when realizing objective function, will be each basic
The new bit stream file of unit, which is configured to corresponding basic unit and refers to, imported into corresponding basic unit for new bit stream file,
And the bit stream file in basic unit is replaced with new bit stream file, reconstruct is completed, to realize objective function.
In some embodiments, above-described embodiment is in the new bit stream text for generating each basic unit respectively according to objective function
Before part, further include the steps that determining objective function according to reconstruct sub-circuit in objective circuit.The present embodiment passes through according to reconstruct
Sub-circuit determines objective function, cooperates with the bit stream file for generating basic unit according to objective function, realizing will reconstruct
Sub-circuit is tied to basic unit and realizes this purpose, i.e. reconstruct submodule wait reconstruct the basic unit in resource-area by realizing
Reconstruct.
In some embodiments, step S103 in embodiment illustrated in fig. 1 is comprised determining that needs to reconstruct in objective circuit
Sub-circuit is reconstructed, one or more basic units are selected according to the function that reconstruct sub-circuit needs to realize；According to reconstruct sub-circuit
The function of needing to realize generates the bit stream data of bit stream file, is generated according to the address of the basic unit for reconstruct sub-circuit selection
The address of bit stream file generates the timing of bit stream file according to the consequence for reconstruction of reconstruct sub-circuit；According to the address of bit stream file
Determine ownership basic unit, by bit stream file storage into the corresponding storage unit of ownership basic unit, control unit is according to control
Successively the bit stream data of bit stream file is written to ownership basic unit according to the timing of bit stream file for signal processed.The present embodiment mentions
The specific implementation of dynamic reconfigurable has been supplied, reconstruct is completed according to the content in bit stream file completely, is not needed and existing skill
Art carries out the comparison of front and back bit stream file like that, so that it may determine that the address of the corresponding basic unit of bit stream data and write-in correspond to
The sequencing of basic unit.
Objective circuit according to the present invention refers to that used circuit when user needs to realize certain functions, circuit make
Used time, for part sub-circuit therein need to have it is fault-tolerant (such as part demodulator there may be mistake, experiment effect as needed
Fruit dynamic corrections adjustment etc.), the specific functions such as replacement (realize different size), for such sub-circuit, the present invention is determined
Justice is reconstruct sub-circuit, and others should not fault-tolerant (will not be wrong as the realization circuit of radio-frequency antenna), replacement (antenna
Do not need to replace) the sub-circuit present invention be defined as fixed sub-circuit.
Objective circuit by being divided into the stator electricity for needing the reconstruct sub-circuit reconstructed and not needing reconstruct by the present embodiment
Road, and be only to reconstruct sub-circuit to distribute basic unit, and fix sub-circuit and then use not restructural resource-area in FPGA device
Resource realize, further reduce and basic unit limited in FPGA occupied.The present embodiment will be by will only reconstruct son
The function that circuit needs are realized resolves to the bit stream data of the bit stream file of basic unit, and the function of fixing sub-circuit does not parse
For the bit stream file of basic unit, the dissection process only for reconstruct sub-circuit is realized, is needed with existing by the mesh after reconstruct
Mark circuit all resolves to bit stream file and compares, and resolution speed is fast, realizes simple, and after generating bit stream file, does not need
Comparison is assured that basic unit according to bit stream file.
In some embodiments, embodiment illustrated in fig. 1 will also wrap after resource dividing to be reconstructed is divided into basic unit
It includes: control unit and storage unit being set for a basic unit, or control unit and storage are set for multiple basic units
Unit, or set up the step of setting control unit and storage unit separately for restructural resource dividing.One basic unit needs to realize
Reconstruct, needs to have the storage unit and the control unit of control reconfiguration time for storing bit stream file, the present embodiment provides
The set-up modes of three kinds of control units and storage unit, user can select according to actual needs, in basic unit
Reconfigurable device quantity it is more when, single basic unit can realize more complicated circuit function, at this time can with for
Control unit and storage unit is respectively set in each basic unit, corresponding, if the reconfigurable device quantity of single basic unit
When less, one control unit can be set for multiple basic units and storage unit (is realized more by time-multiplexed mode
The storage and control of a basic unit), certainly, when the basic unit total quantity that restructural resource-area is smaller or divides is seldom,
Can only be arranged a control unit and storage unit (by time-multiplexed mode realize the storages of all basic units with
Control).
Second embodiment:
Fig. 2 is the schematic diagram that the programmable logic device that second embodiment of the invention provides reconstructs device, as shown in Figure 2,
In the present embodiment, programmable logic device provided by the invention reconstruct device 2 comprise determining that module 21, division module 22 and
Reconstructed module 23, wherein
Determining module 21, for determining the resource-area to be reconstructed of programmable logic device；
Division module 22, for resource dividing to be reconstructed to be divided at least one basic unit, basic unit includes at least
One reconfigurable device；
Reconstructed module 23, for each basic unit to be reconstructed respectively.
In some embodiments, the basic unit in above-described embodiment further include can between reconfigurable device and other devices
The connection of reconstruct.
In some embodiments, the reconfigurable device in above-described embodiment is configurable logic blocks CLB.
In some embodiments, the division module 21 in above-described embodiment is specifically used for: will resource-area be reconstructed according to object
Reason region division is at least one basic unit；Alternatively, resource-area to be reconstructed is divided into according to physical region and objective function
At least one basic unit.
In some embodiments, the objective function in above-described embodiment includes: the function that basic unit needs to realize, or
Resource-area to be reconstructed needs the function of realizing.
In some embodiments, the reconstructed module 23 in above-described embodiment is specifically used for being generated respectively according to objective function each
The new bit stream file of basic unit；The new bit stream file of each basic unit is configured to corresponding basic unit.
In some embodiments, the reconstructed module 23 in above-described embodiment is also used to according to reconstructing sub-circuit in objective circuit
Determine objective function.
In practical applications, programmable logic device reconstruct device 2 provided by the invention can be realized by developing instrument
Its function can be realized by the resource in programmable logic device.
The annotation explanation carried out is done to the present invention now in conjunction with practical.
3rd embodiment:
In the present embodiment, to need to realize dynamic fault tolerant effect as applied field using Reconstruction Mechanism in aviation field
Scape, programmable logic device FPGA, for reconfigurable device is CLB；For purposes of illustration only, will only be needed by taking 1 reconstruct as an example
The circuit of realization is denoted as objective circuit 1 (circuit before reconstruct) and objective circuit 2 (circuit after reconstruct), as shown in table 1 below:
| Objective circuit | Circuit composition |
| Objective circuit 1 | Sub-circuit a, sub-circuit b, sub-circuit c, sub-circuit d, sub-circuit e |
| Objective circuit 2 | Sub-circuit a, sub-circuit b, 2 sub-circuit c, 2 sub-circuit d |
Table 1
As shown in Table 1, (sub-circuit a and b are or not objective circuit 1 and the specific identical sub-circuit a and sub-circuit b of objective circuit 2
It needs to reconstruct, as fixed sub-circuit)；Objective circuit 1 is not then identical as remaining sub-circuit of objective circuit 2 (to be needed to reconstruct, as
Reconstruct sub-circuit).
Fig. 3 is the flow chart for the programmable logic device reconstructing method that third embodiment of the invention provides, from the figure 3, it may be seen that
In the present embodiment, programmable logic device reconstructing method provided by the invention the following steps are included:
S301: FPGA device is selected as needed, and carries out the division of basic unit；
User selects suitable FPGA device according to requirements such as the function complexities of the objective circuit to be realized；Fig. 4 does not show
The devices such as editable interconnection line, DSP in FPGA device out, as shown in (A) in Fig. 4, empty circles are represented on FPGA device
The resource (can be used to realize the sub-circuit for not needing reconstruct in objective circuit) of dynamic restructuring is not supported, and solid circles represent
The resource of support dynamic restructuring on FPGA device (can be used to realize the sub-circuit for needing to reconstruct in objective circuit, can such as compile
Journey logical block CLB etc.).
FPGA device is divided into restructural resource-area and not restructural resource-area；As shown in (B) in Fig. 4, in physical areas
It is not restructural resource-area (dashed region) by the regional assignment of empty circles on domain, being can by the regional assignment of solid circles
It reconstructs in resource-area (solid line region)；In this application example, using restructural resource-area as resource-area to be reconstructed.
Resource dividing to be reconstructed is divided into basic unit；The weight in basic unit is determined according to the objective function of basic unit
Structure number of devices is physically adjacent between basic unit；It include 4 branch in each basic unit as shown in (C) in Fig. 4
The CLB of dynamic reconfigurable is held, 4 CLB cooperate and a basic training of objective circuit may be implemented after bit stream file is written
Can, resource dividing to be reconstructed is divided into 12 basic units (JB1-JB12) according to the continuous mode of physical region, corner is extra
Reconfigurable device without processing (Fig. 4 is also not shown).
S302: resource is distributed for objective circuit；
Objective circuit includes fixed sub-circuit and reconstruct sub-circuit, is distributed in not restructural resource-area for fixed sub-circuit
Resource distributes basic unit for reconstruct sub-circuit；For the resource distribution mode of fixed sub-circuit, the present invention is repeated no more, only
The resource distribution mode of reconstruct sub-circuit is illustrated, the prior art is that many CLB, DSP and editable are distributed for it is mutual
The basic devices such as line (these devices need to encode one by one), and the present invention is then that (quantity is much smaller than for its distribution basic unit
The quantity of basic device), as shown in Figure 5,2 basic units are distributed for sub-circuit c, distributes 3 substantially for sub-circuit d
Unit distributes 5 basic units for sub-circuit e；
S303: objective circuit is converted to the bit stream file of basic unit；
This step is illustrated only for the bit stream file for reconstructing sub-circuit in objective circuit, and fixed sub-circuit only needs to generate
Bit stream file, no longer illustrates；
As shown in connection with fig. 5, for respectively reconstructing the bit stream file content of sub-circuit such as in objective circuit 1 (circuit before reconstruct)
Under:
The bit stream file of sub-circuit c includes 2 subfiles (corresponding 2 basic units), be respectively as follows: bit stream data C1,
Location JB1, timing 1, bit stream data C2, address JB7, timing 1；
The bit stream file of sub-circuit d includes 3 subfiles (corresponding 3 basic units), be respectively as follows: bit stream data D1,
Location JB2, timing 1, bit stream data D2, address JB8, timing 1, bit stream data D3, address JB9, timing 1；
The bit stream file of sub-circuit e includes 5 subfiles (corresponding 5 basic units), be respectively as follows: bit stream data E1,
Location JB3, timing 1, bit stream data E2, address JB4, timing 1, bit stream data E3, address JB5, timing 1, bit stream data E4, address
JB10, timing 1, bit stream data E5, address JB11, timing 1；
As shown in connection with fig. 5, for respectively reconstructing the bit stream file content of sub-circuit such as in objective circuit 2 (circuit after reconstruct)
Under:
The bit stream file of first sub-circuit c includes 2 subfiles (corresponding 2 basic units), is respectively as follows: bit stream data
C1, address JB1, timing 2, bit stream data C2, address JB7, timing 2；
The bit stream file of second sub-circuit c includes 2 subfiles (corresponding 2 basic units), is respectively as follows: bit stream data
C1, address JB2, timing 2, bit stream data C2, address JB8, timing 2；
The bit stream file of first sub-circuit d includes 3 subfiles (corresponding 3 basic units), is respectively as follows: bit stream data
D1, address JB3, timing 2, bit stream data D2, address JB9, timing 2, bit stream data D3, address JB10, timing 2；
The bit stream file of second sub-circuit d includes 3 subfiles (corresponding 3 basic units), is respectively as follows: bit stream data
D1, address JB4, timing 2, bit stream data D2, address JB5, timing 2, bit stream data D3, address JB11, timing 2；
S304: bit stream file is tied to corresponding basic unit；
As shown in fig. 6, control unit and storage unit, storage unit is arranged for each basic unit can be stored by block
Device (BRAM) composition；Specifically,
Basic unit: mainly by the reconfigurable devices such as configurable logic block (CLB) and digital signal processor (DSP) group
At realizing mathematical operation, the functions such as logical process in work, data are inputted by I/O port, are handled by Digital Logic, can
Data after reconfigurable logic unit output processing；
Storage unit: it is mainly used for the configuration bit stream that storage needs to reconstruct, is made of block storage (BRAM)；
Control unit: received from external command, when needing replacing configuration bit stream, CPU issues RECONFIGURATION REQUEST, control unit
After receiving request, the bit stream data of corresponding timing is imported in basic unit, with the bit stream file before replacement, realizes new electricity
Road；When basic unit is configuring bit stream data, control unit issues BUSY instruction, input data is prevented, when configuration terminates
Afterwards, control unit output DONE instruction, allows to input, and notifies CPU that configuration terminates, and prepares to receive next RECONFIGURATION REQUEST；
According to upper step it is assumed that in the corresponding storage unit of basic unit JB1-5,7-11, it is all stored with 2 bit stream texts
Part, shown in table 2 specific as follows:
Table 2
S305: reconstruct is completed according to control signal；
The control unit of each basic unit is according to extraneous signal, the weight issued such as user by the key of developing instrument
Structure signal etc., control reconfiguration opportunity；
After the test for completing 1 function of objective circuit, user needs the function of test target circuit 2, presses developing instrument
Reconstruction buttons, be reconstructed at this time, particularly by control unit by timing in storage unit be 2 bit stream data import base
In this unit, to replace the bit stream data that timing is 1, realizes new circuit function, reconstruct the sub-circuit structural schematic diagram of front and back
As shown in Figure 5；
As shown in figure 5, before reconstitution, the bit stream file in basic unit is the bit stream data that timing is 1, at this point, substantially
The function of unit JB1 and JB7 realization sub-circuit c；Basic unit JB2, JB8 and JB9 realize the function of sub-circuit d；Basic unit
The function of JB3, JB4, JB5, JB10 and JB11 realization sub-circuit e；After reconstitution, the bit stream file in basic unit is that timing is
2 bit stream data, at this point, basic unit JB1 and JB7 realize the function of first sub-circuit c；Basic unit JB2 and JB8 are realized
The function of second sub-circuit c；Basic unit JB3, JB9 and JB10 realize the function of first sub-circuit d；Basic unit JB4,
JB5 and JB11 realizes the function of second sub-circuit d.
In summary, implementation through the invention, at least exist it is following the utility model has the advantages that
The resource-area to be reconstructed in programmable logic device is determined as needed, and it is divided into basic unit, substantially
Unit includes at least one reconfigurable device, these reconfigurable devices can realize basic logic after bit stream data is written
Function, i.e., each basic unit can realize some functions of objective circuit, on this basis, respectively to each basic unit into
Row reconstruct, realizes using basic unit as the reconfiguration technique of minimal reconstruction unit, with existing using basic device as minimal reconstruction list
The reconfiguration technique of member is compared, and minimal reconstruction range increases, when reconstruct required control signal and number of data streams all will reduction,
Reduce many and diverse degree of device and reconfiguration cost of programmable logic device；
Further, the reconstruct sub-circuit for needing to reconstruct in objective circuit is only tied to resource-area to be reconstructed, reduced
The waste of restructural resource.
The above is only a specific embodiment of the invention, not do limitation in any form to the present invention, all
Any simple modification, equivalent variations, combination or the modification that embodiment of above is made according to the technical essence of the invention, still
Belong to the protection scope of technical solution of the present invention.
Claims (10)
1. a kind of programmable logic device reconstructing method characterized by comprising
Determine the resource-area to be reconstructed of programmable logic device；
The resource dividing to be reconstructed is divided at least one basic unit, the basic unit includes at least one restructural device
Part；
The one or more basic units of function selection for needing to realize according to reconstruct sub-circuit to be reconstructed in objective circuit,
And the bit stream according to each basic unit generation bit stream file that the function that the reconstruct sub-circuit needs to realize is selection
Data；
The address of each bit stream file is generated according to the address of the basic unit of selection, and according to the reconstruct electricity
The consequence for reconstruction on road generates the timing of each bit stream file；
The ownership basic unit that each bit stream file is determined according to the address of each bit stream file, according to each bit stream text
Successively the bit stream data of each bit stream file is written to ownership basic unit for the timing of part.
2. programmable logic device reconstructing method as described in claim 1, which is characterized in that the basic unit further includes institute
State connection restructural between reconfigurable device and other devices.
3. programmable logic device reconstructing method as described in claim 1, which is characterized in that the reconfigurable device includes can
Configure logic module CLB.
4. programmable logic device reconstructing method as described in any one of claims 1 to 3, which is characterized in that will be described to weight
It includes: that the resource-area to be reconstructed is divided at least one according to physical region that structure resource dividing, which is divided at least one basic unit,
A basic unit；Alternatively, it is substantially single that the resource-area to be reconstructed according to physical region and objective function is divided at least one
Member.
5. programmable logic device reconstructing method as claimed in claim 4, which is characterized in that the objective function includes: institute
State the function that basic unit needs the function of realizing or the resource-area to be reconstructed to need to realize.
6. a kind of programmable logic device reconstructs device characterized by comprising
Determining module, for determining the resource-area to be reconstructed of programmable logic device；
Division module, for the resource dividing to be reconstructed to be divided at least one basic unit, the basic unit includes extremely
A few reconfigurable device；
Reconstructed module, the function for needing to realize according to reconstruct sub-circuit to be reconstructed in objective circuit select one or more
The basic unit, and position is generated according to each basic unit that the function that the reconstruct sub-circuit needs to realize is selection
The bit stream data of stream file, and it is used to generate the address of each bit stream file according to the address of the basic unit of selection,
And the timing of each bit stream file is generated according to the consequence for reconstruction of the reconstruct sub-circuit；And for according to it is described everybody
The address of stream file determines the ownership basic unit of each bit stream file, according to the timing of each bit stream file successively by institute
The bit stream data for stating each bit stream file is written to ownership basic unit.
7. programmable logic device as claimed in claim 6 reconstructs device, which is characterized in that the basic unit further includes institute
State connection restructural between reconfigurable device and other devices.
8. programmable logic device as claimed in claim 6 reconstructs device, which is characterized in that the reconfigurable device includes can
Configure logic module CLB.
9. as the described in any item programmable logic device of claim 6 to 8 reconstruct device, which is characterized in that the division mould
Block is specifically used for: the resource-area to be reconstructed is divided at least one basic unit according to physical region；Alternatively, will it is described to
It reconstructs resource-area and is divided at least one basic unit according to physical region and objective function.
10. programmable logic device as claimed in claim 9 reconstructs device, which is characterized in that the objective function includes: institute
State the function that basic unit needs the function of realizing or the resource-area to be reconstructed to need to realize.
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| PCT/CN2015/097730 WO2016107421A1 (en) | 2014-12-29 | 2015-12-17 | Reconstruction method and apparatus for programmable logic device |
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| CN104536755B (en) * | 2014-12-29 | 2019-05-10 | 深圳市国微电子有限公司 | Programmable logic device reconstructing method and device |
| US9740809B2 (en) * | 2015-08-27 | 2017-08-22 | Altera Corporation | Efficient integrated circuits configuration data management |
| CN105260545B (en) * | 2015-10-19 | 2018-09-14 | 深圳市紫光同创电子有限公司 | A kind of verification method of programmable circuit system |
| CN107544819B (en) * | 2016-06-29 | 2022-04-19 | 中兴通讯股份有限公司 | Service implementation method and device for programmable device and communication terminal |
| CN106487395A (en) * | 2016-10-18 | 2017-03-08 | 哈尔滨工业大学 | Multi-mode demodulating system based on FPGA |
| CN107491342A (en) * | 2017-09-01 | 2017-12-19 | 郑州云海信息技术有限公司 | A kind of more virtual card application methods and system based on FPGA |
| CN109491949B (en) * | 2018-11-27 | 2022-06-07 | 哈尔滨工业大学 | Zynq-based dynamic reconfigurable framework and method |
| CN110602107B (en) * | 2019-09-18 | 2021-12-28 | 山东浪潮科学研究院有限公司 | Zynq-based network cipher machine and network data encryption and decryption method |
| CN113971022B (en) * | 2021-12-22 | 2022-03-18 | 成都航天通信设备有限责任公司 | Wireless signal processing method applying fully programmable system on chip |
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| US5600845A (en) * | 1994-07-27 | 1997-02-04 | Metalithic Systems Incorporated | Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor |
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| CN104536755B (en) * | 2014-12-29 | 2019-05-10 | 深圳市国微电子有限公司 | Programmable logic device reconstructing method and device |
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| US5600845A (en) * | 1994-07-27 | 1997-02-04 | Metalithic Systems Incorporated | Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor |
| CN1434953A (en) * | 1999-12-14 | 2003-08-06 | 爱特梅尔股份有限公司 | Method for implementing physical design for dynamically reconfigurable logic circuit |
| CN1641651A (en) * | 1999-12-14 | 2005-07-20 | 爱特梅尔股份有限公司 | Method for implementing physical design for dynamically reconfigurable logic circuit |
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