CN104536755A - Reconstruction method and device for programmable logic device - Google Patents
Reconstruction method and device for programmable logic device Download PDFInfo
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- CN104536755A CN104536755A CN201410835994.9A CN201410835994A CN104536755A CN 104536755 A CN104536755 A CN 104536755A CN 201410835994 A CN201410835994 A CN 201410835994A CN 104536755 A CN104536755 A CN 104536755A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
Abstract
The invention provides a reconstruction method and device for a programmable logic device. The reconstruction method comprises the steps that a to-be-reconstructed resource area of the programmable logic device is determined; the to-be-reconstructed resource area is divided into one or more basic units, and the basic units comprise one or more reconstructable devices; reconstruction is performed on each basic unit. Through the performance of the reconstruction method and device for the programmable logic device, the to-be-reconstructed resource area of the programmable logic device is determined as needed, the to-be-reconstructed resource area is divided into the basic units, the reconstruction is performed on each basic unit, and a reconstruction technique which regards the basic units as the minimum reconstruction units is achieved; compared with an existing reconstruction technique which regards basic devices as the minimum reconstruction units, the minimum reconstruction range is enlarged, the needed quantity of control signals and data flow when the reconstruction is performed can be both reduced, and the multifarious degree and reconstruction cost of the programmable logic device is reduced.
Description
Technical field
The present invention relates to the application of programmable logic device (PLD), particularly a kind of programmable logic device (PLD) reconstructing method and device.
Background technology
For FPGA (Field-Programmable Gate Array, field programmable gate array) etc. programmable logic device (PLD), only need the circuit designed to be converted into the circuit function that just can obtain after bit stream file imports expecting by developing instrument, flow cost is saved compared with special purpose logic devices, and more flexible, can overprogram to realize Different Logic function.
Programmable logic device (PLD) is while being user-friendly to, also some shortcomings can be there are, when carrying out circuit design as used the SoC FPGA of zynq7000 series, existing FPGA Reconfiguration Technologies adopts the mode of configuration frame, to basic logic unit (look-up table, trigger, CLB, the basic device such as IOB) realize fine-grained reconstruct, this mode needs to generate the bit stream file of whole circuit according to objective circuit after reconstruct, and the bit stream data of reconstruct needs is sent to these basic devices, these basic device Reconfigurations complete reconstruct, it is large that this kind of fpga chip structural design realizes difficulty, chip area is large, chip cost is high.
Therefore, how providing a kind of programmable logic device (PLD) reconfiguration technique possessing lower cost, is those skilled in the art's technical matterss urgently to be resolved hurrily.
Summary of the invention
The invention provides a kind of programmable logic device (PLD) reconstructing method and device, to reduce the reconfiguration cost of programmable logic device (PLD).
The invention provides a kind of programmable logic device (PLD) reconstructing method, in one embodiment, the method comprises: that determines programmable logic device (PLD) treats reconstruct resource-area; To treat that reconstruct resource dividing is divided at least one elementary cell, elementary cell comprises at least one reconfigurable device; Respectively each elementary cell is reconstructed.
Further, the elementary cell in above-described embodiment also comprises reconfigurable connection between reconfigurable device and other devices.
Further, the reconfigurable device in above-described embodiment comprises configurable logic blocks CLB.
Further, will treat in above-described embodiment reconstructs resource dividing and is divided at least one elementary cell to comprise: will treat that reconstruct resource-area is divided at least one elementary cell according to physical region; Or, will treat that reconstruct resource-area is divided at least one elementary cell according to physical region and objective function.
Further, the objective function in above-described embodiment comprises: the function that elementary cell needs realize, or waits the function reconstructing resource-area needs realization.
Further, being reconstructed each elementary cell respectively in above-described embodiment comprises: the new bit stream file generating each elementary cell according to objective function respectively; The new bit stream file of each elementary cell is configured to corresponding elementary cell.
The invention provides a kind of programmable logic device (PLD) reconfiguration device, in one embodiment, this device comprises: determination module, for determine programmable logic device (PLD) wait reconstruct resource-area; Divide module, for treating that reconstruct resource dividing is divided at least one elementary cell, elementary cell will comprise at least one reconfigurable device; Reconstructed module, for being reconstructed each elementary cell respectively.
Further, the elementary cell in above-described embodiment also comprises reconfigurable connection between reconfigurable device and other devices.
Further, the reconfigurable device in above-described embodiment comprises configurable logic blocks CLB.
Further, the division module in above-described embodiment specifically for: will treat reconstruct resource-area be divided at least one elementary cell according to physical region; Or, will treat that reconstruct resource-area is divided at least one elementary cell according to physical region and objective function.
Further, the objective function in above-described embodiment comprises: the function that elementary cell needs realize, or waits the function reconstructing resource-area needs realization.
Further, the reconstructed module in above-described embodiment is specifically for generating the new bit stream file of each elementary cell respectively according to objective function; The new bit stream file of each elementary cell is configured to corresponding elementary cell.
Beneficial effect of the present invention:
Scheme provided by the invention, determine that treating in programmable logic device (PLD) reconstructs resource-area as required, and it is divided into elementary cell, elementary cell comprises at least one reconfigurable device, these reconfigurable devices just can realize basic logic function after write bit stream data, namely each elementary cell can some functions of realize target circuit, on this basis, respectively each elementary cell is reconstructed, achieving with elementary cell is the reconfiguration technique of minimal reconstruction unit, with existing with compared with the basic device reconfiguration technique that is minimal reconstruction unit, minimal reconstruction scope increases, control signal required during reconstruct and number of data streams all will reduce, reduce the numerous and diverse degree of device and the reconfiguration cost of programmable logic device (PLD).
Accompanying drawing explanation
The process flow diagram of the programmable logic device (PLD) reconstructing method that Fig. 1 provides for first embodiment of the invention;
The schematic diagram of the programmable logic device (PLD) reconfiguration device that Fig. 2 provides for second embodiment of the invention;
The process flow diagram of the programmable logic device (PLD) reconstructing method that Fig. 3 provides for third embodiment of the invention;
Fig. 4 is the partiting step schematic diagram of FPGA device in third embodiment of the invention;
Fig. 5 is the reconstruct schematic diagram waiting to reconstruct resource-area in third embodiment of the invention;
Fig. 6 be in third embodiment of the invention single elementary cell realize schematic diagram.
Embodiment
Now by embodiment mode by reference to the accompanying drawings the present invention made and further annotate explanation.
First embodiment:
The process flow diagram of the programmable logic device (PLD) reconstructing method that Fig. 1 provides for first embodiment of the invention, as shown in Figure 1, in the present embodiment, programmable logic device (PLD) reconstructing method provided by the invention comprises the following steps:
S101: that determines programmable logic device (PLD) treats reconstruct resource-area;
First this step needs the restructural resource-area determining to support in programmable logic device (PLD) dynamic restructuring, the kind of programmable logic device (PLD) is a lot, the present invention is described for FPGA: user is according to the FPGA of the Attributions selection certain models such as the complexity of objective circuit, this FPGA is divided into restructural resource-area and not restructural resource-area, restructural resource-area refers to that the resource in this region possesses dynamic reconfigurable, in circuit runs, different bit stream data can be write by time division multiplex and realize different functions without the time, restructural resource-area does not refer to that the resource in this region is not supported dynamically to write bit stream data to realize different functions in circuit runs.
After user as required selected FPGA, the scope of restructural resource-area on device just can be learnt according to device specification, then user just can according to the function of reconstruct electronic circuit in the objective circuit wanting to change and the scope of restructural resource-area, device being determined, one or more waiting reconstructs resource-area, wait to reconstruct the part (belonging to restructural resource-area completely) that resource-area can be restructural resource-area, also can comprise partial reconfigurable resource-area and part not restructural resource-area (for do not need in realize target circuit reconstruct circuit function).
S102: will treat that reconstruct resource dividing is divided at least one elementary cell, elementary cell comprises at least one reconfigurable device;
Determining behind reconstruct resource-area, to wait that the resource (comprise CLB, can edit interconnection line etc.) reconstructed in resource-area is divided at least one elementary cell, each elementary cell comprises at least one reconfigurable device (as CLB), so just can realize some basic functions after write bit stream file.
Reconfigurable device quantity between different elementary cells can be different, the objective function that can realize required for this elementary cell divides, if some elementary cell needs the objective function of realization simple, so just only can comprise a reconfigurable device, corresponding, if some elementary cells need the objective function more complicated realized, the reconfigurable device of a greater number just can be comprised.
In certain embodiments, corresponding elementary cell is distributed for the ease of subfunction each in the objective function that user realizes required for objective circuit, the reconfigurable device (these reconfigurable devices cooperatively interact can some little functions of realize target circuit) that each elementary cell comprises equal number can be set to, this ensures that there each elementary cell and can realize certain function after write bit stream data, and the restructural resource that each elementary cell possesses is identical, on this basis, just objective circuit can be decomposed into a lot of little function, and be that these little functions distribute corresponding elementary cell, and first need not judge the complexity of little like this functional realiey, carrying out the division of elementary cell, dividing mode is simple.
S103: be reconstructed each elementary cell respectively, can be tied to elementary cell to realize by the bit stream file of objective circuit by developing instrument.
In certain embodiments, the elementary cell in above-described embodiment also comprises reconfigurable connection between reconfigurable device and other devices.In actual applications, reconfigurable device operationally needs to communicate with other devices, as the work-based logic relation etc. between the acquisition of completion bit stream file, reconfigurable device, the present embodiment is by being also divided into connection reconfigurable between reconfigurable device and other devices in elementary cell, make the function of elementary cell more complete, reconfigurable connection comprises can edit interconnection line, IOB resource etc.
In certain embodiments, for FPGA device, reconfigurable device in above-described embodiment is configurable logic blocks CLB, certainly in some special applications, restructural resource type in the FPGA device used is different, corresponding, reconfigurable device is exactly the restructural resource in this kind of FPGA device.
In certain embodiments, will treat in above-described embodiment reconstructs resource dividing and is divided at least one elementary cell to comprise: will treat that reconstruct resource-area is divided at least one elementary cell according to physical region; Or, will treat that reconstruct resource-area is divided at least one elementary cell according to physical region and objective function.Present embodiments provide the dividing mode of elementary cell, divide according to physical region or divide according to physical region and objective function, the all devices in elementary cell are made to be geographically continuous print, this reduces the numerous and diverse degree of communication in elementary cell between each device, and then reduce the length of bit stream data in the bit stream file that generates according to the objective function of elementary cell and numerous and diverse degree, reduce and realize reconfigurable cost.
In certain embodiments, be adjacent between two elementary cells in above-described embodiment, and nonoverlapping; Can certainly being interval certain area, in such interval region, just can realizing by arranging bit stream file the stator circuit that some possess the functions such as control, storage.
In certain embodiments, when certain elementary cell in above-described embodiment comprises multiple (two and more than) reconfigurable device, the type of these reconfigurable devices is associated needing in the objective function realized, as elementary cell need to realize the function such as resistance and electric capacity time, its internal components just can comprise reconfigurable resistance and electric capacity etc.
In certain embodiments, the objective function in above-described embodiment comprises: the function that elementary cell needs realize, or waits the function reconstructing resource-area needs realization.Elementary cell needs the function realized to refer in objective circuit, the function that the bit stream file that elementary cell writes is corresponding, and during as realized the resistance function of a specific resistance, elementary cell comprises a reconfigurable device and corresponding communication line.The function waiting to reconstruct resource-area needs realization refers to that objective circuit needs treating the function that reconstruct resource-area realizes, these functions can be made up of multiple subfunction, the division of elementary cell is carried out according to these subfunctions, make each elementary cell can realize corresponding subfunction, the elementary cell that such division obtains is functionally independent, and reconstruct is simple.
In certain embodiments, being reconstructed each elementary cell respectively in above-described embodiment comprises: the new bit stream file generating each elementary cell according to objective function respectively; The new bit stream file of each elementary cell is configured to corresponding elementary cell.New bit stream file refers to the information such as the bit stream data that elementary cell is required when realize target function, the new bit stream file of each elementary cell is configured to corresponding elementary cell and refers to the elementary cell new bit stream file being imported to correspondence, and replace the bit stream file in elementary cell with new bit stream file, complete reconstruct, with realize target function.
In certain embodiments, above-described embodiment, before the new bit stream file generating each elementary cell according to objective function respectively, also comprises the step according to reconstructing electronic circuit determination objective function in objective circuit.The present embodiment passes through according to reconstruct electronic circuit determination objective function, cooperatively interact with the bit stream file generating elementary cell according to objective function, achieving and reconstruct electronic circuit is tied to elementary cell realizes this purpose, namely reconstructing submodule by waiting that the elementary cell reconstructed in resource-area realizes reconstruct.
In certain embodiments, the step S103 in embodiment illustrated in fig. 1 comprises: determine the reconstruct electronic circuit needing in objective circuit to reconstruct, need the function realized to select one or more elementary cell according to reconstruct electronic circuit; Need the function realized to generate the bit stream data of bit stream file according to reconstruct electronic circuit, generate the address of bit stream file according to the address of the elementary cell selected for reconstruct electronic circuit, generate the sequential of bit stream file according to the reconstruct order of reconstruct electronic circuit; Determine to belong to elementary cell according to the address of bit stream file, be stored into by bit stream file in storage unit corresponding to ownership elementary cell, the bit stream data of bit stream file is write to ownership elementary cell according to control signal according to the sequential of bit stream file by control module successively.Present embodiments provide the specific implementation of dynamic reconfigurable, reconstruct is completed completely according to the content in bit stream file, do not need the contrast carrying out anteroposterior position stream file with prior art like that, just can determine the address of the elementary cell that bit stream data is corresponding and write the sequencing of corresponding elementary cell.
Objective circuit involved in the present invention refers to that user needs the circuit used when realizing some function, circuit in use, need to possess fault-tolerant (as part detuner may exist mistake for parton circuit wherein, experiment effect dynamic corrections adjustment etc. as required), change specific functions such as (realizing different size), for such electronic circuit, the present invention is defined as reconstruct electronic circuit, and other not fault-tolerant (can not be wrong as the realizing circuit of radio-frequency antenna), the electronic circuit the present invention changing (antenna does not need to change yet) is defined as stator circuit.
The stator circuit that the present embodiment is reconstructed by the reconstruct electronic circuit that is divided into needs to reconstruct objective circuit and not needing, and be only reconstruct electronic circuit distribution elementary cell, stator circuit then adopts the resource of the not restructural resource-area in FPGA device to realize, and further reduces and takies elementary cell limited in FPGA.The bit stream data of the present embodiment by by the biological function explore that reconstruct electronic circuit needs realize being only the bit stream file of elementary cell, and the function of stator circuit does not resolve to the bit stream file of elementary cell, achieve only for the dissection process of reconstruct electronic circuit, compared with objective circuit after reconstructing all being resolved to bit stream file with existing needs, resolution speed is fast, realize simple, and after generating bit stream file, do not need contrast just can determine elementary cell according to bit stream file.
In certain embodiments, embodiment illustrated in fig. 1 after treating that reconstruct resource dividing is divided into elementary cell, also comprise: be that an elementary cell arranges control module and storage unit, or control module and storage unit are set for multiple elementary cell, or divide the step that control module and storage unit are set for restructural resource dividing.An elementary cell needs to realize reconstruct, the storage unit that needs possess for bank bit stream file and the control module of control reconfiguration time, present embodiments provide the set-up mode of three kinds of control modules and storage unit, user can select according to actual needs, time as more in the reconfigurable device quantity in elementary cell, single elementary cell just can realize the circuit function of more complicated, now just control module and storage unit can be set respectively for each elementary cell, corresponding, if during the reconfigurable device negligible amounts of single elementary cell, a control module and storage unit (being realized storage and the control of multiple elementary cell by time-multiplexed mode) can be set for multiple elementary cell, certainly, when the elementary cell total quantity that restructural resource-area is less or divide is little, a control module and storage unit (being realized storage and the control of all elementary cells by time-multiplexed mode) just can be only set.
Second embodiment:
The schematic diagram of the programmable logic device (PLD) reconfiguration device that Fig. 2 provides for second embodiment of the invention, as shown in Figure 2, in the present embodiment, programmable logic device (PLD) reconfiguration device 2 provided by the invention comprises: determination module 21, division module 22 and reconstructed module 23, wherein
Determination module 21, for determine programmable logic device (PLD) wait reconstruct resource-area;
Divide module 22, for treating that reconstruct resource dividing is divided at least one elementary cell, elementary cell will comprise at least one reconfigurable device;
Reconstructed module 23, for being reconstructed each elementary cell respectively.
In certain embodiments, the elementary cell in above-described embodiment also comprises reconfigurable connection between reconfigurable device and other devices.
In certain embodiments, the reconfigurable device in above-described embodiment is configurable logic blocks CLB.
In certain embodiments, the division module 21 in above-described embodiment specifically for: will treat reconstruct resource-area be divided at least one elementary cell according to physical region; Or, will treat that reconstruct resource-area is divided at least one elementary cell according to physical region and objective function.
In certain embodiments, the objective function in above-described embodiment comprises: the function that elementary cell needs realize, or waits the function reconstructing resource-area needs realization.
In certain embodiments, the reconstructed module 23 in above-described embodiment is specifically for generating the new bit stream file of each elementary cell respectively according to objective function; The new bit stream file of each elementary cell is configured to corresponding elementary cell.
In certain embodiments, the reconstructed module 23 in above-described embodiment is also for according to reconstructing electronic circuit determination objective function in objective circuit.
In actual applications, programmable logic device (PLD) reconfiguration device 2 provided by the invention can realize its function by developing instrument, can be realized by the resource in programmable logic device (PLD).
Existing R. concomitans reality does to the present invention the annotation explanation carried out.
3rd embodiment:
In the present embodiment, to need in aviation field to utilize Reconstruction Mechanism to realize dynamic fault tolerant effect for application scenarios, programmable logic device (PLD) is FPGA, and reconfigurable device is CLB is example; For ease of illustrating, being only reconstructed into example with 1 time, will the circuit realized being needed to be designated as objective circuit 1 (circuit before reconstruct) and objective circuit 2 (circuit after reconstruct), as shown in table 1 below:
| Objective circuit | Circuit forms |
| Objective circuit 1 | Electronic circuit a, electronic circuit b, electronic circuit c, electronic circuit d, electronic circuit e |
| Objective circuit 2 | Electronic circuit a, electronic circuit b, 2 electronic circuit c, 2 electronic circuit d |
Table 1
As shown in Table 1, the electronic circuit a that objective circuit 1 is specifically identical with objective circuit 2 and electronic circuit b (electronic circuit a and b does not need to reconstruct, and is stator circuit); All the other electronic circuits of objective circuit 1 and objective circuit 2 then not identical (need to reconstruct, be reconstruct electronic circuit).
The process flow diagram of the programmable logic device (PLD) reconstructing method that Fig. 3 provides for third embodiment of the invention, as shown in Figure 3, in the present embodiment, programmable logic device (PLD) reconstructing method provided by the invention comprises the following steps:
S301: select FPGA device as required, and carry out the division of elementary cell;
User requires to select suitable FPGA device according to the function complexity of the objective circuit that will realize etc.; The device such as the interconnection line edited, DSP in the not shown FPGA device of Fig. 4, as shown in (A) in Fig. 4, empty circles represents, and FPGA device do not support the resource of dynamic restructuring (can be used for the electronic circuit not needing in realize target circuit to reconstruct), solid circles represents the resource (can be used for the electronic circuit needing in realize target circuit to reconstruct, as programmable logic block CLB etc.) of the support dynamic restructuring on FPGA device.
FPGA device is divided into restructural resource-area and not restructural resource-area; As shown in (B) in Fig. 4, on physical region, being not restructural resource-area (dashed region) by the regional assignment of empty circles, is restructural resource-area (solid line region) by the regional assignment of solid circles; In this application example, using restructural resource-area as waiting to reconstruct resource-area.
To treat that reconstruct resource dividing is divided into elementary cell; According to the restructing device quantity in the objective function determination elementary cell of elementary cell, adjacent physically between elementary cell; As shown in (C) in Fig. 4, the CLB that 4 are supported dynamic reconfigurable is comprised in each elementary cell, 4 CLB are after write bit stream file, cooperatively interacting can a basic function of realize target circuit, to treat that reconstruct resource dividing is divided into 12 elementary cells (JB1-JB12) according to physical region continuous print mode, the unnecessary reconfigurable device in corner does not carry out processing (Fig. 4 is also not shown).
S302: be objective circuit Resources allocation;
Objective circuit comprises stator circuit and reconstruct electronic circuit, for stator circuit distributes the resource in not restructural resource-area, is that reconstruct electronic circuit distributes elementary cell; For the resource distribution mode of stator circuit, the present invention repeats no more, only the resource distribution mode of reconstruct electronic circuit is described, prior art is distributed a lot of CLB, DSP for it and can edit the basic devices (these devices need to encode one by one) such as interconnection line, the present invention is then for it distributes elementary cell (quantity is much smaller than the quantity of basic device), as shown in Figure 5, for electronic circuit c distributes 2 elementary cells, for electronic circuit d distributes 3 elementary cells, for electronic circuit e distributes 5 elementary cells;
S303: bit stream file objective circuit being converted to elementary cell;
This step is only described for the bit stream file reconstructing electronic circuit in objective circuit, and stator circuit only needs generation bit stream file, no longer illustrates;
Shown in composition graphs 5, the bit stream file content for reconstruct electronic circuit each in objective circuit 1 (circuit before reconstruct) is as follows:
The bit stream file of electronic circuit c comprises 2 son files (corresponding 2 elementary cells), is respectively: bit stream data C1, address JB1, sequential 1, bit stream data C2, address JB7, sequential 1;
The bit stream file of electronic circuit d comprises 3 son files (corresponding 3 elementary cells), is respectively: bit stream data D1, address JB2, sequential 1, bit stream data D2, address JB8, sequential 1, bit stream data D3, address JB9, sequential 1;
The bit stream file of electronic circuit e comprises 5 son files (corresponding 5 elementary cells), be respectively: bit stream data E1, address JB3, sequential 1, bit stream data E2, address JB4, sequential 1, bit stream data E3, address JB5, sequential 1, bit stream data E4, address JB10, sequential 1, bit stream data E5, address JB11, sequential 1;
Shown in composition graphs 5, the bit stream file content for reconstruct electronic circuit each in objective circuit 2 (circuit after reconstruct) is as follows:
The bit stream file of first electronic circuit c comprises 2 son files (corresponding 2 elementary cells), is respectively: bit stream data C1, address JB1, sequential 2, bit stream data C2, address JB7, sequential 2;
The bit stream file of second electronic circuit c comprises 2 son files (corresponding 2 elementary cells), is respectively: bit stream data C1, address JB2, sequential 2, bit stream data C2, address JB8, sequential 2;
The bit stream file of first electronic circuit d comprises 3 son files (corresponding 3 elementary cells), is respectively: bit stream data D1, address JB3, sequential 2, bit stream data D2, address JB9, sequential 2, bit stream data D3, address JB10, sequential 2;
The bit stream file of second electronic circuit d comprises 3 son files (corresponding 3 elementary cells), is respectively: bit stream data D1, address JB4, sequential 2, bit stream data D2, address JB5, sequential 2, bit stream data D3, address JB11, sequential 2;
S304: bit stream file is tied to corresponding elementary cell;
As shown in Figure 6, for each elementary cell arranges control module and storage unit, storage unit can be made up of block storage (BRAM); Concrete,
Elementary cell: form primarily of the reconfigurable devices such as configurable logic block (CLB) and digital signal processor (DSP), realize mathematical operation, the functions such as logical process, in work, data are inputted by IO port, through Digital Logic process, data after reconfigurable logic unit output processing;
Storage unit: be mainly used in depositing the configuration bit stream needing reconstruct, be made up of block storage (BRAM);
Control module: be received from external command, when configuration bit stream changed by needs, CPU sends RECONFIGURATION REQUEST, after control module receives request, the bit stream data of corresponding sequential is imported in elementary cell, with the bit stream file before replacing it, realizes new circuit; When elementary cell is just at configuration bit flow data, control module sends BUSY instruction, stops input data, and after configuration terminates, control module exports DONE instruction, allows input, and notifies that CPU configuration terminates, and prepares to accept next RECONFIGURATION REQUEST;
According to the hypothesis of upper step, in the storage unit that elementary cell JB1-5,7-11 are corresponding, all store 2 bit stream files, shown in table 2 specific as follows:
Table 2
S305: complete reconstruct according to control signal;
The control module of each elementary cell according to the signal in the external world, as the reconstruction signal etc. that user is sent by the button of developing instrument, control reconfiguration opportunity;
After the test completing objective circuit 1 function, user needs the function of test target circuit 2, press the reconstruction buttons of developing instrument, now be reconstructed, the bit stream data being particularly 2 by sequential in storage unit by control module imports in elementary cell, to replace the bit stream data that sequential is 1, realize new circuit function, the electronic circuit structural representation before and after reconstruct as shown in Figure 5;
As shown in Figure 5, before reconstitution, the bit stream file in elementary cell to be sequential be 1 bit stream data, now, elementary cell JB1 and JB7 realizes the function of electronic circuit c; Elementary cell JB2, JB8 and JB9 realize the function of electronic circuit d; Elementary cell JB3, JB4, JB5, JB10 and JB11 realize the function of electronic circuit e; After reconstitution, the bit stream file in elementary cell to be sequential be 2 bit stream data, now, elementary cell JB1 and JB7 realizes the function of first electronic circuit c; Elementary cell JB2 and JB8 realizes the function of second electronic circuit c; Elementary cell JB3, JB9 and JB10 realize the function of first electronic circuit d; Elementary cell JB4, JB5 and JB11 realize the function of second electronic circuit d.
In summary, by enforcement of the present invention, at least there is following beneficial effect:
Determine that treating in programmable logic device (PLD) reconstructs resource-area as required, and it is divided into elementary cell, elementary cell comprises at least one reconfigurable device, these reconfigurable devices just can realize basic logic function after write bit stream data, namely each elementary cell can some functions of realize target circuit, on this basis, respectively each elementary cell is reconstructed, achieving with elementary cell is the reconfiguration technique of minimal reconstruction unit, with existing with compared with the basic device reconfiguration technique that is minimal reconstruction unit, minimal reconstruction scope increases, control signal required during reconstruct and number of data streams all will reduce, reduce the numerous and diverse degree of device and the reconfiguration cost of programmable logic device (PLD),
Further, only waiting to reconstruct resource-area by needing the reconstruct electronic circuit reconstructed to be tied in objective circuit, reducing the waste of restructural resource.
Below be only the specific embodiment of the present invention; not any pro forma restriction is done to the present invention; every above embodiment is done according to technical spirit of the present invention any simple modification, equivalent variations, combination or modification, all still belong to the protection domain of technical solution of the present invention.
Claims (12)
1. a programmable logic device (PLD) reconstructing method, is characterized in that, comprising:
That determines programmable logic device (PLD) treats reconstruct resource-area;
Treat that reconstruct resource dividing is divided at least one elementary cell by described, described elementary cell comprises at least one reconfigurable device;
Respectively each elementary cell is reconstructed.
2. programmable logic device (PLD) reconstructing method as claimed in claim 1, it is characterized in that, described elementary cell also comprises reconfigurable connection between described reconfigurable device and other devices.
3. programmable logic device (PLD) reconstructing method as claimed in claim 1, it is characterized in that, described reconfigurable device comprises configurable logic blocks CLB.
4. the programmable logic device (PLD) reconstructing method as described in any one of claims 1 to 3, it is characterized in that, treat that reconstruct resource dividing is divided at least one elementary cell to comprise by described: treat that reconstruct resource-area is divided at least one elementary cell according to physical region by described; Or, treat that reconstruct resource-area is divided at least one elementary cell according to physical region and objective function by described.
5. programmable logic device (PLD) reconstructing method as claimed in claim 4, it is characterized in that, described objective function comprises: the function that described elementary cell needs realize, or described in wait to reconstruct the function that resource-area needs realization.
6. the programmable logic device (PLD) reconstructing method as described in any one of claims 1 to 3, is characterized in that, is reconstructed respectively and comprises: the new bit stream file generating each elementary cell according to objective function respectively to each elementary cell; The new bit stream file of each elementary cell is configured to corresponding elementary cell.
7. a programmable logic device (PLD) reconfiguration device, is characterized in that, comprising:
Determination module, for determine programmable logic device (PLD) wait reconstruct resource-area;
Divide module, for treating that reconstruct resource dividing is divided at least one elementary cell by described, described elementary cell comprises at least one reconfigurable device;
Reconstructed module, for being reconstructed each elementary cell respectively.
8. programmable logic device (PLD) reconfiguration device as claimed in claim 7, it is characterized in that, described elementary cell also comprises reconfigurable connection between described reconfigurable device and other devices.
9. programmable logic device (PLD) reconfiguration device as claimed in claim 7, it is characterized in that, described reconfigurable device comprises configurable logic blocks CLB.
10. the programmable logic device (PLD) reconfiguration device as described in any one of claim 7 to 9, is characterized in that, described division module specifically for: by described treat reconstruct resource-area be divided at least one elementary cell according to physical region; Or, treat that reconstruct resource-area is divided at least one elementary cell according to physical region and objective function by described.
11. programmable logic device (PLD) reconfiguration devices as claimed in claim 10, it is characterized in that, described objective function comprises: the function that described elementary cell needs realize, or described in wait to reconstruct the function that resource-area needs to realize.
12. programmable logic device (PLD) reconfiguration devices as described in any one of claim 7 to 9, it is characterized in that, described reconstructed module is specifically for generating the new bit stream file of each elementary cell respectively according to objective function; The new bit stream file of each elementary cell is configured to corresponding elementary cell.
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| CN201410835994.9A CN104536755B (en) | 2014-12-29 | 2014-12-29 | Programmable logic device reconstructing method and device |
| PCT/CN2015/097730 WO2016107421A1 (en) | 2014-12-29 | 2015-12-17 | Reconstruction method and apparatus for programmable logic device |
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| CN201410835994.9A Active CN104536755B (en) | 2014-12-29 | 2014-12-29 | Programmable logic device reconstructing method and device |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105260545A (en) * | 2015-10-19 | 2016-01-20 | 深圳市同创国芯电子有限公司 | Verification method for programmable circuit systems |
| WO2016107421A1 (en) * | 2014-12-29 | 2016-07-07 | 深圳市国微电子有限公司 | Reconstruction method and apparatus for programmable logic device |
| CN106487395A (en) * | 2016-10-18 | 2017-03-08 | 哈尔滨工业大学 | Multi-mode demodulating system based on FPGA |
| CN107491342A (en) * | 2017-09-01 | 2017-12-19 | 郑州云海信息技术有限公司 | A kind of more virtual card application methods and system based on FPGA |
| WO2018001329A1 (en) * | 2016-06-29 | 2018-01-04 | 中兴通讯股份有限公司 | Service implementation method and apparatus for programmable device, and communication terminal |
| CN108255778A (en) * | 2015-08-27 | 2018-07-06 | 阿尔特拉公司 | effective integrated circuit configuration data management |
| CN109491949A (en) * | 2018-11-27 | 2019-03-19 | 哈尔滨工业大学 | Dynamic reconfigurable frame and method based on Zynq |
| CN113971022A (en) * | 2021-12-22 | 2022-01-25 | 成都航天通信设备有限责任公司 | Wireless signal processing method and system applying system on fully programmable chip |
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| CN110602107B (en) * | 2019-09-18 | 2021-12-28 | 山东浪潮科学研究院有限公司 | Zynq-based network cipher machine and network data encryption and decryption method |
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| WO2016107421A1 (en) * | 2014-12-29 | 2016-07-07 | 深圳市国微电子有限公司 | Reconstruction method and apparatus for programmable logic device |
| CN108255778A (en) * | 2015-08-27 | 2018-07-06 | 阿尔特拉公司 | effective integrated circuit configuration data management |
| CN105260545A (en) * | 2015-10-19 | 2016-01-20 | 深圳市同创国芯电子有限公司 | Verification method for programmable circuit systems |
| CN105260545B (en) * | 2015-10-19 | 2018-09-14 | 深圳市紫光同创电子有限公司 | A kind of verification method of programmable circuit system |
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| CN107544819B (en) * | 2016-06-29 | 2022-04-19 | 中兴通讯股份有限公司 | Service implementation method and device for programmable device and communication terminal |
| CN106487395A (en) * | 2016-10-18 | 2017-03-08 | 哈尔滨工业大学 | Multi-mode demodulating system based on FPGA |
| CN107491342A (en) * | 2017-09-01 | 2017-12-19 | 郑州云海信息技术有限公司 | A kind of more virtual card application methods and system based on FPGA |
| CN109491949A (en) * | 2018-11-27 | 2019-03-19 | 哈尔滨工业大学 | Dynamic reconfigurable frame and method based on Zynq |
| CN109491949B (en) * | 2018-11-27 | 2022-06-07 | 哈尔滨工业大学 | Zynq-based dynamic reconfigurable framework and method |
| CN113971022A (en) * | 2021-12-22 | 2022-01-25 | 成都航天通信设备有限责任公司 | Wireless signal processing method and system applying system on fully programmable chip |
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| CN104536755B (en) | 2019-05-10 |
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