The downstream synchronic PN code capturing method that is used for CDMA20001x EV-DO system
Technical field
The present invention relates to the implementation method of a kind of CDMA20001x of being used for EV-DO (hereafter EV-DO) system descending synchronic PN code capturing.
Background technology
CDMA20001x obtains one of extensively commercial 3G cellular wireless mobile communication system at present, but along with the continuous growth of wireless data service demand, CDMA20001x can not satisfy the demand of future development to the tenability of high-speed packet data service.For this reason, 3GPP2 has proposed EV-DO (Evolution Data Optimized) technology, at sudden, the preceding/reverse link loading asymmetry of data service and the characteristics of big channel capacity,, provide higher data transmission capabilities specially in the mode of smooth evolution.
Compare the CDMA20001x system, EV-DO can provide higher air interface rate.Forward link has adopted technology such as time-derived channel scheduling, dynamic rate control and high order modulation, and simultaneously, reverse link has used technology such as reverse pilot, power control and rate controlled, makes network can more reasonably arrange various wireless data services.
The time-derived channel structure of EV-DO system forward link as shown in Figure 1, the forward link baseband signal that the base station sends has all been passed through the scrambling of pseudo noise (PN) sequence, different PN sequence phases is used to distinguish different base stations.Each base station all will send special pilot channel so that the travelling carriage in this sub-district carries out synchronously, travelling carriage must be caught the PN sequence phase of sub-district, place the very first time, and with local PN sequence (error must in the magnitude of part chip) accurate descrambling with it synchronously.
The frame period of EV-DO is 26.667ms (32768 chip period), and spreading rate is 1.2288Mchip/s, is divided into 16 time slots (slot), and each time slot is divided into 2 half cracks (half-slot) again, and structure of time slot as shown in Figure 2.
The PN sequence signature multinomial of I, Q two-way is respectively:
P
I(x)=x
15+x
10+x
8+x
7+x
6+x
2+1
P
Q(x)=x
15+x
12+x
11+x
10+x
9+x
5+x
4+x
3+1
Corresponding generator polynomial is respectively:
Wherein,
symbol
Expression mould 2 adds computing.The generation of PN sequence generally uses linear feedback shift register (LFSR) to realize that the PN sequence LFSR structure chart on I road and Q road as shown in Figure 3.
The m sequence period length of 15 grades of shift registers is 2
15-1, insert one 0 in continuous 14 0 backs, carry out then unipolarity to ambipolar mapping (bit 0 is mapped as+1; Bit 1 is mapped as-1) cycle of obtaining is 2
15The PN sequence of (32768 chips) joins end to end and periodically repeats.
The initial moment of system zero bias reference PN sequence is defined as: first 0 the delivery time in continuous 15 0.Between the frequency base station, utilize PN sequence biased exponent (PN offset index) to distinguish, biased exponent (value from 0 to 511, totally 512 kinds of value possibilities) multiply by the hysteresis number of chips that 64 chips are exactly this base station PN sequence Relative Zero bias reference PN sequence.
At receiving terminal, utilize PN sequence descrambling flow process as shown in Figure 4.Suppose that receiver is the received signal of an initial store M half crack (a corresponding 1024M chip) length with a certain moment s, the real part and the imaginary part of establishing this signal are respectively r
I(s+k), r
Q(s+k), k=0 wherein, 1,2 ... 1024M-1 utilizes the local multiple PN sequence P that generates
I(k), P
Q(k) descrambling to received signal, the I behind the descrambling, Q road signal are:
y
I(s+k)=r
I(s+k)P
I(k)+r
Q(s+k)P
Q(k);
y
Q(s+k)=r
Q(s+k)P
I(k)-r
I(s+k)P
Q(k);k=0,1,2…1024·M-1。
The catching method of existing PN sequence generally is that received signal starting point s is slided on whole PN sequence period, for each possible Phase synchronization moment s, with the scrambling sequence y of correspondence
I(s+k), y
Q(s+k) (k=0,1,2 ... 1024M-1) data that extract pilot frequency burst position add up again, and the accumulation result in m half crack is designated as θ
m(s):
Again with M result (θ
0(s), θ
1(s) ..., θ
M-1(s)) ask for mould value square after adding up, be designated as | θ (s) |
2:
Then in a PN sequence period, make | θ (s) |
2Maximum moment s is received signal PN sequence phase synchronization point
Pilot channel is a time division multiplexing among the EV-DO, the scrambling sequence of pilot frequency locations in each half crack of only adding up during search.When realizing, in order to simplify correlation computations, only the data of pilot frequency locations are carried out descrambling to received signal.Receiving terminal needs intercept local PN sequence before work is relevant at this moment, and method is: after the PN sequence that obtains a certain biased exponent correspondence, intercept 96 middle chip data of per 1024 chips.But the sequence that obtains after the PN sequence intercepting of different biased exponents is different (the present invention claims that the sequence that obtains after the intercepting of PN sequence is the PN pattern).Because the PN biased exponent of sub-district, unknown place, travelling carriage need be searched for all possible PN pattern when carrying out initial acquisition.
The relation of PN biased exponent and PN pattern as shown in Figure 5, the position (being called for short the PN intercept among the present invention) of the pilot burst in each half crack of schematically having drawn among the figure is numbered Pi (i=0,1,, 511) the PN intercept represent that biased exponent is first segment data after the PN sequence intercepting of i.Because PN sequence hysteresis number of chips is unit with 64chip, the then every increase 16 of PN biased exponent, PN sequence hysteresis number of chips increases by 1024 chips, just equals the length in a half crack, has marked the situation of the PN intercept appearance of numbering P0 among Fig. 5.Analyze as can be known, local PN sequence has 16 kinds of different patterns, PN sequence after all the other 496 kinds of interceptings can be that unit sequence skew obtains with the PN intercept by these 16 kinds of patterns: when the biased exponent of any two kinds of PN sequences differs 16 or 16 integral multiple, have identical PN pattern, and on sequence leading or several PN intercepts that lag behind.Therefore, when catching, be that 0 to 15 PN pattern detects the base station pilot signals that can guarantee to find any PN biased exponent to biased exponent.
In the real system, the E of received signal
c/ N
0(E
cBe the average chip energy of received signal, N
0Be noise power spectral density) may be very low, and the pilot channel that is used for the PN sequence capturing has only accounted for the part transmission time slot; In addition, may there be bigger radio frequency crystal oscillator frequency deviation in travelling carriage or be in the vehicle-mounted high-speed mobile environment.These all will increase the difficulty of PN sequence capturing.
For traditional catching method, at low E
c/ N
0Situation under, need to increase correlation length (promptly increasing half timeslot number M above) in the hope of improving acquisition performance, but exist at receiving terminal under the situation of frequency shift (FS), the long more frequency shift (FS) of correlation length is also big more to the influence of catching the result.The tradition catching method can't be taken into account the performance of two aspects simultaneously.
Summary of the invention
In order to overcome the existing in prior technology shortcomings and deficiencies, purpose of the present invention is exactly the downstream synchronic PN code capturing method of a kind of CDMA20001xEV-DO of being used for of proposition system.This method is applicable to programming device (including but not limited to FPGA, DSP etc.) realization, to 16 kinds of PN pattern parallel searches, for conventional method, can have bigger frequency shift (FS) and E in received signal
c/ N
0When low, realize that reliable down is synchronous; And can be according to the channel circumstance of reality, configuration parameter flexibly, better utilization hardware resource.
Above-mentioned purpose of the present invention is achieved through the following technical solutions: be used for the downstream synchronic PN code capturing method of CDMA20001x EV-DO system, may further comprise the steps:
Step 1, be the data in initial M half crack of received signal buffer memory, extract the data of each half crack pilot frequency burst position respectively current time s;
Step 2, make n=0, i=0 number is n relevant the adding up of PN intercept data of i with the data of n half crack of received signal pilot frequency burst position and local PN pattern, obtains 1 accumulation result;
Step 3, make n=n+1, repeating step 2 until n=M-1, obtains M-1 point accumulation result;
Step 4, the M point accumulation result of step 2 and step 3 gained is asked for mould value square respectively, obtain M point mould value square;
Step 5, the M point mould value of step 4 gained square is added up, obtain mould value square accumulation result;
Step 6, with mould value square accumulation result and default thresholding relatively if surpass default thresholding, is then successfully caught the PN sequence phase; Otherwise i=i+1, n=0 returns step 2, until i=15;
Step 7, if the mould value square accumulation result of 16 kinds of PN pattern correspondences all not have to surpass default thresholding, s=s+1 then, the received signal original position chip of delaying time returns step 1, until successfully catching the PN sequence phase.
Acquisition procedure of the present invention is: storage is the received signal of an initial 1024M chip lengths (corresponding M half crack) constantly with s, extracts the data of pilot frequency burst position in each half crack respectively; (data of the individual half of 0≤n≤M-1) crack pilot frequency burst position and local PN pattern number are n the intercept data pn of i (0≤i≤15) to n
i n(k) (k=0,1,2 ... 95) relevant adding up; And then with M relevant accumulation result (θ
i 0(s), θ
i 1(s) ..., θ
i M-1(s)) ask for mould value square respectively, adding up obtains mould value square accumulation result Metric again
i(s).If current s received signal PN sequence and local PN pattern when number being the sequence basic synchronization of i constantly, Metric
i(s) will surpass default thresholding, realize the PN sequence phase capturing.Otherwise, calculate the mould value square accumulation result of other 15 kinds of PN pattern correspondences, and judge whether to surpass default thresholding; If the correlated results of all the other 15 kinds of PN pattern correspondences all surpasses thresholding, s=s+1 then, 1 chip of received signal original position time-delay repeats above-mentioned steps, can successfully catch the PN sequence.
From above technical scheme and acquisition procedure as can be known, compare with existing traditional catching method, advantage of the present invention and beneficial effect are:
1) is initial received signal with phase place s, only, reduced amount of calculation, in programming device, use the matched filter realization the pilot frequency locations data accumulating operation of be correlated with.
2) ask the mould value square to add up again earlier to every section correlated results, frequency shift (FS) is not accumulated with the increase of the hop count that adds up the influence of correlated results.During frequency shift (FS) in there is certain limit in received signal, owing to mould value square operation makes the adverse effect of frequency shift (FS) can not accumulate along with the increase of the hop count that adds up; Frequency shift (FS) is less to the correlated results influence of 96 chip lengths of each section, so the correlation length of this method no longer is subjected to the restriction of frequency shift (FS).Through actual verification, frequency shift (FS) and E in received signal existence ± 3kHz scope
c/ N
0During 〉=-20dB, this method can realize the reliable down synchronic PN sequence capturing.In addition, this method is adapted at realizing on the programming device.
3) 16 kinds of PN patterns of parallel search, effectively shortened mean acquisition time: when the present invention carries out parallel search to 16 kinds of PN patterns, to each search window or phase point, detected 16 kinds of PN patterns simultaneously after, a search window or phase point again slide; Rather than as serial search of the prior art, only search for a PN pattern at every turn, a PN pattern has been searched for a frame after, the following a kind of PN pattern of search again.Parallel search of the present invention remains come calculating one by one of branchs to 16 kinds of PN patterns in concrete calculating.
Description of drawings
Fig. 1 is the schematic diagram of CDMA20001xEV-DO system forward link time-derived channel;
Fig. 2 is the schematic diagram of CDMA20001xEV-DO system forward chain time gap structure;
Fig. 3 generates the schematic diagram of I, Q two-way PN sequence for the CDMA20001xEV-DO system utilizes LFSR;
Fig. 4 carries out the schematic diagram of descrambling to baseband signal for the multiple PN sequence of receiving terminal utilization;
Fig. 5 is the schematic diagram of the PN of CDMA20001xEV-DO system biased exponent and PN pattern;
Fig. 6 carries out the schematic diagram of related operation to received signal for the present invention;
Fig. 7 is the flow chart of catching of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with embodiment and accompanying drawing, but embodiments of the present invention are not limited thereto.
Embodiment
The present invention can realize on programming device, the process of carrying out related operation to received signal as shown in Figure 6, detailed process is as shown in Figure 7; Specifically may further comprise the steps:
Step 1, with the data that current time s is initial M half crack of received signal buffer memory (1024M chip lengths), be designated as r (s+k) (r (s+k)=r
I(s+k)+jr
Q(s+k), k=0,1,2 ... 1024M-1), extract the data of each half crack pilot frequency burst position respectively.
Step 2, make n=0, i=0 number is n the PN intercept data pn of i with the data of n half crack of received signal pilot frequency burst position and local PN pattern
i n(k) relevant adding up obtains 1 accumulation result.
The length of each PN intercept data is 96 chips in the above-mentioned steps.Preferably, the described relevant matched filter that uses 96 complex tap in the programming device that is accumulated in realizes that n correlator exported as accumulation result:
Wherein, k=0,1,2 ... 95; Symbol * represents the complex conjugate computing.
Step 3, make n=n+1, repeating step 2 until n=M-1, obtains M-1 point accumulation result.
Step 4, with the M point accumulation result (θ of step 2 and step 3 gained
i 0(s), θ
i 1(s) ..., θ
i M-1(s)) ask for mould value square respectively, obtain M point mould value square.The mould value square is designated as | θ
i n(s) |
2Wherein, asking for of mould value square used 2M real multipliers and M real add musical instruments used in a Buddhist or Taoist mass realization in programming device.
Step 5, the M point mould value of step 4 gained square is added up, obtains mould value square accumulation result:
Above-mentioned mould value square is accumulated in and uses M-1 real add musical instruments used in a Buddhist or Taoist mass realization in the programming device.
Step 6, with mould value square accumulation result Metric
i(s) compare with default thresholding,, then successfully catch the PN sequence phase if surpass default thresholding; Otherwise i=i+1, n=0 returns step 2, until i=15.
Mould value square accumulation result Metric
i(s) realize with 1 comparator that relatively passes through of default thresholding.
Step 7, if the mould value square accumulation result Metric of 16 kinds of PN pattern correspondences
i(s) (i=0,1,2 ..., 15) all there is not to surpass a default thresholding, s=s+1 then, chip of received signal original position time-delay returns step 1, until successfully catching the PN sequence phase.
The foregoing description is an example with the single-time sampling, is preferred implementation of the present invention, but embodiments of the present invention are not restricted to the described embodiments, for example the principle of multiple sampling with realize and can on the described basis of present embodiment, simple extension obtain; Other any do not deviate from change, the modification done under spirit of the present invention and the principle, substitutes, combination, simplify, and all should be the substitute mode of equivalence, is included within protection scope of the present invention.