CN101699776B - Down link synchronization method applied to CDMA20001x system - Google Patents

Abstract

The invention discloses a down link synchronization method applied to a CDMA20001x system, comprising the following steps: buffering receiving signals rI (s+k) and rQ (s+k) with the s moment as a start and the total length being M chips and dividing the receiving signals into P segments, each of which has length of X chips; carrying out accumulation after multiplying the data on the first segment of the receiving signals by the conjugate point by point on the first segment of a corresponding local PN sequence, and obtaining a P point accumulation result; padding zeros at the end of the P point accumulation result until N point and then carrying out FFT to obtain an N point transformation result; computing the squares of the moduli of the N point transformation result and searching the maximum of the squares of the moduli of the N point; and comparing the maximum of the squares of the moduli with a preset threshold, if the maximum exceeds the threshold, successfully capturing the PN phase, or enabling s to be equal to s+1 and returning to the initial step. The method can realize reliable down link synchronization when the receiving signals have larger frequency offsets and Ec/N0 of the pilot channel is lower.

Description

A kind of down link synchronisation method that is applied to CDMA2000 1x system

Technical field

The present invention relates to the method for synchronous of spread spectrum communication system, be specifically related to the down-going synchronous implementation method of a kind of CDMA2000 of being applied to 1x system.

Background technology

In the cellular wireless mobile communication field, cdma system has many exclusive technical advantages, and it can better resist channel disturbance and increase the confidentiality of information, becomes the key technology of 3G physical layer.For Resistant DS Spread Spectrum System, for obtaining spreading code phase place that the ideal system performance just requires receiving-transmitting sides (error must in the magnitude of part chip) fully synchronously, receiver must be known the instantaneous phase of transmitter spreading code accurately and rapidly and the spreading code that this locality generates is aimed at it, just can carry out demodulation accurately.

In CDMA2000 1x system, each base station will send special pilot channel so that the travelling carriage in this residential quarter carries out synchronously, pilot channel is directly repeated to constitute by pseudo noise (PN) sequence period of I, Q two-way, travelling carriage utilizes this pilot channel, carry out the PN sequence phase capturing, it is synchronous to obtain descending timing.Downlink pilot frequency channel transmitting terminal baseband model as shown in Figure 1.

The proper polynomial that CDMA2000 1x system is used for the PN sequence on I road and Q road is respectively:

P _I(x)＝x ¹⁵+x ¹³+x ⁹+x ⁸+x ⁷+x ⁵+1

P _Q(x)＝x ¹⁵+x ¹²+x ¹¹+x ¹⁰+x ⁶+x ⁵+x ⁴+x ³+1

Corresponding generator polynomial is:

$i\left(n\right)=i(n-15)\⊕i(n-10)\⊕i(n-8)\⊕i(n-7)\⊕i(n-6)\⊕i(n-2)$

$q\left(n\right)=q(n-15)\⊕q(n-12)\⊕q(n-11)\⊕q(n-10)\⊕q(n-9)$

$\⊕q(n-5)\⊕q(n-4)\⊕q(n-3)$

Symbol

Expression mould 2 adds computing.The generation of PN sequence generally uses linear feedback shift register (LFSR) to realize that the PN sequence LFSR structure chart on I road and Q road as shown in Figure 2.

The m sequence period length of 15 grades of shift register generations is 2 ¹⁵-1, insert one 0 in continuous 14 0 backs, as the PN sequence start position, carry out then unipolarity to ambipolar mapping (bit 0 is mapped as+1; Bit 1 is mapped as-1) cycle of obtaining is 2 ¹⁵The PN sequence of (32768 chips), the periodicity emphasis that joins end to end recurrence is sent.

The descrambling flow process of receiver as shown in Figure 3.Suppose that receiver is the reception signal of an initial buffer memory M chip lengths with a certain moment s, real part and the imaginary part of establishing this signal are respectively r _I(s+k), r _Q(s+k), k=0 wherein, 1,2...M-1 utilizes the local plural PN sequence P that generates _I(k), P _Q(k) descrambling to received signal, the I behind the descrambling, Q road signal are:

y _I(s+k)＝r _I(s+k)·P _I(k)+r _Q(s+k)·P _Q(k)；

y _Q(s+k)＝r _Q(s+k)·P _I(k)-r _I(s+k)·P _Q(k)；k＝0，1，2...M-1

Existing method for synchronous generally is that reception signal starting point s is slided at whole PN sequence period, to each possible synchronization point s, with the M point scrambling sequence y of correspondence _I(s+k), y _Q(s+k) (k=0,1,2...M-1) add up, be designated as θ (s):

$\mathrm{\θ}\left(s\right)=\underset{k=0}{\overset{M-1}{\mathrm{\Σ}}}{y}_I(s+k)+j\·\underset{k=0}{\overset{M-1}{\mathrm{\Σ}}}{y}_Q(s+k).$

Again accumulation result is asked for mould value square, then in a PN sequence period, is made | θ (s) | ²Maximum moment s is and receives signal PN sequence phase synchronization point

$\hat{s}=\arg \underset{s}{\max }{\left|\mathrm{\θ}\left(s\right)\right|}^2.$

In the real system, receive the E of signal _c/ N ₀(E _cFor receiving signal averaging chip energy, N ₀Be noise power spectral density) may be very low, and the pilot channel that is used for the PN sequence capturing has only accounted for the part of total transmit signal power; In addition, may there be bigger radio frequency crystal oscillator frequency deviation in travelling carriage or be in the vehicle-mounted high-speed mobile environment.These all will increase the difficulty of PN sequence capturing.

For the conventional synchronization method, at low E _c/ N ₀Situation under, need to increase correlation length (namely increasing M above) in the hope of improving acquisition performance; But exist at receiving terminal under the situation of frequency shift (FS), the more long frequency shift (FS) of correlation length is also more big to the influence of catching the result.Therefore, the conventional synchronization method can't be taken into account the performance of two aspects simultaneously.

Summary of the invention

In order to overcome the existing in prior technology defective, purpose of the present invention is exactly the down link synchronisation method of a kind of CDMA2000 of being applied to 1x of proposition system.For conventional method, the present invention can receive the bigger frequency shift (FS) of signal existence and the E of pilot channel _c/ N ₀When low, realize reliable down-going synchronous; And can be according to the channel circumstance of reality, configuration parameter flexibly, better utilization hardware resource.

Purpose of the present invention is achieved through the following technical solutions: the down link synchronisation method of a kind of CDMA2000 of being applied to 1x system may further comprise the steps:

Step 1, buffer memory are the reception signal r of M chip for initial total length with s constantly _I(s+k), r _Q(s+k), and with it be divided into the P section, every segment length X chip, M=PX;

Step 2, make l=0, add up after receiving signal l segment data and the conjugation pointwise of corresponding local PN sequence l section being multiplied each other, obtain 1 accumulation result;

Step 3, l=l+1, repeating step 2 until l=P-1, obtains P-1 point accumulation result;

Step 4, with the P point accumulation result end zero padding of step 2, step 3 gained to the N point, carry out the FFT conversion, obtain N point transformation result, N is 2 integral number power;

Step 5, N point transformation result is asked for mould value square respectively;

The maximum of step 6, search N point mould value square;

Step 7, with mould value square maximum and default thresholding relatively if surpass thresholding, is then successfully caught the PN phase place; Otherwise s=s+1 receives chip of signal original position time-delay, returns step 1.

In above-mentioned method for synchronous, step 6 also records the position that mould value square maximum occurs in N point mould value square After described step 7 is successfully caught the PN phase place, also carry out:

Step 8, according to mould value square maximum position

To received signal and the frequency offseting value that exists between the local PN sequence Carry out following estimation:

When $\hat{k}<\frac{N}{2}$ The time, ${\hat{f}}_0=\frac{\hat{k}}{N\&CenterDot;X\&CenterDot;T_c};$ When $\frac{N}{2}\&le;\hat{k}\&le;N-1$ The time, ${\hat{f}}_0=-\frac{N-\hat{k}}{N\&CenterDot;X\&CenterDot;T_c};$ T wherein _cChip period for single-time sampling.

Compare with existing traditional catching method, advantage of the present invention and beneficial effect are:

1) the segmentation correlated results is carried out the FFT conversion, and square maximizing as a result of search N point mould value, compare with default thresholding, can judge whether this phase place is the locking phase of PN sequence; Thereby the total correlation length M no longer is subjected to the restriction of frequency shift (FS).Through actual verification, the frequency shift (FS) that this method can be in receiving signal existence ± 10kHz scope and the E of pilot channel _c/ N ₀During 〉=-27dB, realize reliable down-going synchronous.

2) the present invention is adapted at realizing on the programming device.In programming device, use matched filter to realize receiving the relevant accumulating operation of segmentation of signal and local PN sequence.

3) if the N value is too little, the peak value during the PN Phase synchronization has bigger shake (being called the grid effect), influences acquisition performance; The present invention will be to P accumulation result (θ before the FFT conversion ₀(s), θ ₁(s) ..., θ _P-1(s)) the end zero padding increases the FFT points N to N point (N 〉=P, and be 2 integral number power), further improves acquisition performance and frequency offset estimation accuracy.

4) when successfully catching the PN phase place, can carry out the estimation of frequency offseting value.

Description of drawings

Fig. 1 is the schematic diagram of CDMA2000 1x system transmitting terminal baseband pilot signal;

Fig. 2 is the schematic diagram that CDMA2000 1x system generates I, Q two-way PN sequence;

Fig. 3 carries out the schematic diagram of descrambling to baseband signal for the multiple PN sequence of receiving terminal utilization;

Fig. 4 carries out the schematic diagram of related operation to received signal for the present invention;

Fig. 5 is the schematic diagram of realization flow of the present invention.

Embodiment

The present invention is described in further detail below in conjunction with embodiment and accompanying drawing, but embodiments of the present invention are not limited thereto.

Embodiment

The present invention can realize at programming device, carries out the process of related operation to received signal as shown in Figure 4, and detailed process as shown in Figure 5; Specifically may further comprise the steps:

Step 1, buffer memory are the reception signal r of M chip for initial total length with s constantly _I(s+k), r _Q(s+k) (k=0,1,2... M-1), and are divided into the P section, every segment length X chip, M=PX with it.

Step 2, make l=0, add up after receiving signal l segment data and the conjugation pointwise of corresponding local PN sequence l section being multiplied each other, obtain 1 accumulation result:

${\mathrm{\&theta;}}_l\left(s\right)=\underset{k=0}{\overset{X-1}{\mathrm{\&Sigma;}}}[r_I(s+X\&CenterDot;l+k)\&CenterDot;P_I(X\&CenterDot;l+k)+r_Q(s+X\&CenterDot;l+k)\&CenterDot;P_Q(X\&CenterDot;l+k)]$

$+j\&CenterDot;\underset{k=0}{\overset{X-1}{\mathrm{\&Sigma;}}}[r_Q(s+X\&CenterDot;l+k)\&CenterDot;P_I(X\&CenterDot;l+k)-r_I(s+X\&CenterDot;l+k)\&CenterDot;P_Q(X\&CenterDot;l+k)];$

Above-mentioned adding up can be realized by matched filter in programming device.

Step 3, l=l+1, repeating step 2 until l=P-1, obtains P-1 point accumulation result.

Step 4, with the P point accumulation result (θ of step 2, step 3 gained ₀(s), θ ₁(s) ..., θ _P-1(s)) the end zero padding is carried out the FFT conversion to N point (P＜N, N are 2 integral number power), obtains N point transformation Z as a result _FFT(k) | _s(k=0,1 ..., N-1).

Wherein, the FFT conversion can be used special-purpose FFT chip or use Nlog in programming device ₂N complex multiplier and 2Nlog ₂N complex adder realizes.

Step 5, with N point transformation Z as a result _FFT(k) | _sAsk for mould value square respectively, the mould value of asking for square is designated as | Z _FFT(k) | _s| ²(k=0,1 ..., N-1).Wherein, asking for of mould value square can be by 2N real multipliers and N real add musical instruments used in a Buddhist or Taoist mass realization.

Step 6, search N point mould value square | Z _FFT| _s| ²Maximum, be designated as metric (s), and the position of record mould value square maximum appearance in N point mould value square

$\mathrm{metric}\left(s\right)={\left|{Z_{\mathrm{DFT}}\left(\hat{k}\right)|}_s\right|}^2;$ $\hat{k}=\arg \underset{k}{\max }\left({\left|Z_{\mathrm{DFT}}{\left(k\right)|}_s\right|}^2\right),k=\mathrm{0,1}\&CenterDot;\&CenterDot;\&CenterDot;N-1;$

Wherein square peaked search of mould value adopts N-1 comparator to realize.

Step 7, with mould value square maximum metric (s) and default thresholding relatively if surpass thresholding, is then successfully caught the PN phase place, forwards step 8 to; Otherwise s=s+1 receives chip of signal original position time-delay, returns step 1.Wherein mould value square maximum and default thresholding relatively realizes by 1 comparator.

Step 8, according to mould value square maximum position $\hat{k}(0\&le;\hat{k}<N-1),$ To received signal and the frequency offseting value that exists between the local PN sequence Carry out following estimation:

When $\hat{k}<\frac{N}{2}$ The time, ${\hat{f}}_0=\frac{\hat{k}}{N\&CenterDot;X\&CenterDot;T_c};$ When $\frac{N}{2}\&le;\hat{k}\&le;N-1$ The time, ${\hat{f}}_0=-\frac{N-\hat{k}}{N\&CenterDot;X\&CenterDot;T_c}.$

T wherein _cBeing the chip period of single-time sampling, is 1/1228800 second in the system;

Be invariant.The estimation of frequency offseting value adopts 1 comparator, 1 multiplier to realize.

Above-described embodiment is example with the single-time sampling, is preferred implementation of the present invention, but embodiments of the present invention are not restricted to the described embodiments, for example the principle of multiple sampling with realize and can on the described basis of present embodiment, simple extension obtain; Other any do not deviate from change, the modification done under spiritual essence of the present invention and the principle, substitutes, combination, simplify, and all should be the substitute mode of equivalence, is included within protection scope of the present invention.

Claims (6)

1. down link synchronisation method that is applied to the CDMA20001x system is characterized in that may further comprise the steps:

Step 1, buffer memory are the reception signal r of M chip for initial total length with s constantly _I(s+k), r _Q(s+k), and with it be divided into the P section, every segment length X chip, M=PX;

Step 2, make l=0, add up after receiving signal l segment data and the conjugation pointwise of corresponding local PN sequence l section being multiplied each other, obtain 1 accumulation result;

Step 3, l=l+1, repeating step 2 until l=P-1, obtains P-1 point accumulation result;

Step 4, with the P point accumulation result end zero padding of step 2, step 3 gained to the N point, carry out the FFT conversion, obtain N point transformation result, N is 2 integral number power;

Step 5, N point transformation result is asked for mould value square respectively;

The maximum of step 6, search N point mould value square;

Step 7, with mould value square maximum and default thresholding relatively if surpass thresholding, is then successfully caught the PN phase place; Otherwise s=s+1 receives chip of signal original position time-delay, returns step 1;

Described reception signal r _I(s+k), r _Q(s+k) represent real part and the imaginary part of receiver received signal respectively, k=0 wherein, 1,2...M-1.

2. the down link synchronisation method that is applied to the CDMA20001x system according to claim 1, it is characterized in that: described being accumulated in the programming device of step 2 realized by matched filter.

3. the down link synchronisation method that is applied to the CDMA20001x system according to claim 1, it is characterized in that: the described FFT conversion of step 4 is used special-purpose FFT chip or use Nlog in programming device ₂N complex multiplier and 2Nlog ₂N complex adder realizes.

4. the down link synchronisation method that is applied to the CDMA20001x system according to claim 1 is characterized in that: asking for by 2N real multipliers and N real add musical instruments used in a Buddhist or Taoist mass of the described mould value of step 5 square realizes.

5. the down link synchronisation method that is applied to the CDMA20001x system according to claim 1 is characterized in that: square N-1 the comparator realization of peaked search employing of the described mould value of step 6.

6. according to each described down link synchronisation method that is applied to the CDMA20001x system among the claim 1-5, it is characterized in that step 6 also records the position that mould value square maximum occurs in N point mould value square

After described step 7 is successfully caught the PN phase place, also carry out:

Step 8, according to mould value square maximum position

To received signal and the frequency offseting value that exists between the local PN sequence

Carry out following estimation:

When $\hat{k}<\frac{N}{2}$ The time, ${\hat{f}}_0=\frac{\hat{k}}{N\&CenterDot;X\&CenterDot;T_c};$ When $\frac{N}{2}\&le;\hat{k}\&le;N-1$ The time, ${\hat{f}}_0=-\frac{N-\hat{k}}{N\&CenterDot;X\&CenterDot;T_c};$ T wherein _cChip period for single-time sampling.

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