CN101699773B - Downstream synchronic PN code capturing method for CDMA 2000 1x EV-DO system - Google Patents

Abstract

The invention discloses a downstream synchronic PN code capturing method for a CDMA 2000 1x EV-DO system, comprising the following steps: caching M half time slot data for a receipt signal taking the current time as the starting; respectively extracting the data at each half time slot pilot frequency burst position; relatively accumulating the data at nth half time slot pilot frequency burst position with the nth intercepted data of which the local PN figure number is i; respectively calculating the module square values of m relative accumulating results; accumulating to obtain the module square value accumulating result; if the module square value accumulating result exceeds the preset threshold, successively capturing, otherwise, calculating module square value accumulating results corresponding to the other 15 kinds of PN figures; if the result still can not exceed the preset threshold, delaying by a chip from the initial position of the receipt signal; and calculating again until the code is captured successively. The invention can realize the reliable downstream synchronization when the receipt signal has large frequency shift and low Ec/N0.

Description

The downstream synchronic PN code capturing method that is used for CDMA2000 1x EV-DO system

Technical field

The present invention relates to the implementation method of a kind of CDMA2000 of being used for 1x EV-DO (hereafter EV-DO) system descending synchronic PN code capturing.

Background technology

CDMA2000 1x obtains one of extensively commercial 3G cellular wireless mobile communication system at present, but along with the continuous growth of wireless data service demand, CDMA2000 1x can not satisfy the demand of future development to the tenability of high-speed packet data service.For this reason; 3GPP2 has proposed EV-DO (Evolution Data Optimized) technology; Special in sudden, the preceding/reverse link loading asymmetry of data service and the characteristics of big channel capacity, with the mode of smooth evolution, higher data transmission capabilities is provided.

Compare CDMA2000 1x system, EV-DO can provide higher air interface rate.Forward link has adopted technology such as time-derived channel scheduling, dynamic rate control and high order modulation, and simultaneously, reverse link has used technology such as reverse pilot, power control and rate controlled, makes network can more reasonably arrange various wireless data services.

The time-derived channel structure of EV-D0 system forward link is as shown in Figure 1, and the forward link baseband signal that send the base station has all been passed through the scrambling of pseudo noise (PN) sequence, and different PN sequence phases are used to distinguish different base stations.Special pilot channel all will be sent so that the travelling carriage in this sub-district carries out synchronously in each base station; Travelling carriage must be caught the PN sequence phase of sub-district, place the very first time, and with local PN sequence (error must in the magnitude of part chip) accurate descrambling with it synchronously.

The frame period of EV-DO is 26.667ms (32768 chip period), and spreading rate is 1.2288Mchip/s, is divided into 16 time slots (slot), and each time slot is divided into 2 half cracks (half-slot) again, and structure of time slot is as shown in Figure 2.

The PN sequence signature multinomial of I, Q two-way is respectively:

P _I(x)＝x ¹⁵+x ¹⁰+x ⁸+x ⁷+x ⁶+x ²+1

P _Q(x)＝x ¹⁵+x ¹²+x ¹¹+x ¹⁰+x ⁹+x ⁵+x ⁴+x ³+1

Corresponding generator polynomial is respectively:

$i\left(n\right)=i(n-15)\⊕i(n-13)\⊕i(n-9)\⊕i(n-8)\⊕i(n-7)\⊕i(n-5)$

$q\left(n\right)=q(n-15)\⊕q(n-12)\⊕q(n-11)\⊕q(n-10)\⊕q(n-6)\⊕q(n-5)$

$\⊕q(n-4)\⊕q(n-3)$

Wherein, symbol

expression mould 2 adds computing.The generation of PN sequence generally uses linear feedback shift register (LFSR) to realize that the PN sequence LFSR structure chart on I road and Q road is as shown in Figure 3.

The m sequence period length of 15 grades of shift registers is 2 ¹⁵-1, insert one 0 in continuous 14 0 backs, carry out then unipolarity to ambipolar mapping (bit 0 is mapped as+1; Bit 1 is mapped as-1) cycle of obtaining is 2 ¹⁵The PN sequence of (32768 chips) joins end to end and periodically repeats.

The initial moment of system zero bias reference PN sequence is defined as: first 0 the delivery time in continuous 15 0.Between the frequency base station, utilize PN sequence biased exponent (PN offset index) to distinguish, biased exponent (value from 0 to 511, totally 512 kinds of value possibilities) multiply by the hysteresis number of chips that 64 chips are exactly this base station PN sequence Relative Zero bias reference PN sequence.

At receiving terminal, utilize PN sequence descrambling flow process as shown in Figure 4.Suppose that receiver is the reception signal of an initial store M half crack (a corresponding 1024M chip) length with a certain moment s, the real part and the imaginary part of establishing this signal are respectively r _I(s+k), r _Q(s+k), k=0 wherein, 1,2...1024M-1 utilizes the local multiple PN sequence P that generates _I(k), P _Q(k) descrambling to received signal, the I behind the descrambling, Q road signal are:

y _I(s+k)＝r _I(s+k)P _I(k)+r _Q(s+k)P _Q(k)；

y _Q(s+k)＝r _Q(s+k)P _I(k)-r _I(s+k)P _Q(k)；k＝0，1，2...1024·M-1。

The catching method of existing PN sequence generally is that reception signal starting point s is slided on whole PN sequence period, as far as each possible Phase synchronization moment s, with the scrambling sequence y of correspondence _I(s+k), y _Q(s+k) (k=0,1, the data that 2...1024M-1) extract pilot frequency burst position add up again, and the accumulation result in m half crack is designated as θ _m(s):

${\mathrm{\θ}}_m\left(s\right)=\underset{k=464}{\overset{559}{\mathrm{\Σ}}}{y}_I(s+1024\·m+k)+j\·\underset{k=464}{\overset{559}{\mathrm{\Σ}}}{y}_Q(s+1024\·m+k);m=\mathrm{0,1},\·\·\·M-1;$

Again with M result (θ ₀(s), θ ₁(s) ..., θ _M-1(s)) ask for mould value square after adding up, be designated as | θ (s) | ²:

${\left|\mathrm{\θ}\left(s\right)\right|}^2={\left|\underset{m=0}{\overset{M-1}{\mathrm{\Σ}}}{\mathrm{\θ}}_m\left(s\right)\right|}^2$

Then in a PN sequence period, make | θ (s) | ²Maximum moment s is and receives signal PN sequence phase synchronization point

$\hat{s}=\arg \underset{s}{\max }{\left|\mathrm{\θ}\left(s\right)\right|}^2.$

Pilot channel is a time division multiplexing among the EV-DO, the scrambling sequence of pilot frequency locations in each half crack of only adding up during search.When realizing, in order to simplify correlation computations, only the data of pilot frequency locations are carried out descrambling to received signal.This moment, receiving terminal needed carry out intercepting to local PN sequence before work is relevant, and method is: after obtaining the corresponding PN sequence of a certain biased exponent, and 96 middle chip data of per 1024 chips of intercepting.But the sequence that obtains after the PN sequence intercepting of different biased exponents is different (the present invention claims that the sequence that obtains after the intercepting of PN sequence is the PN pattern).Because the PN biased exponent of sub-district, unknown place, travelling carriage need be searched for all possible PN pattern when carrying out initial acquisition.

The relation of PN biased exponent and PN pattern is as shown in Figure 5; The position (being called for short the PN intercept among the present invention) of the pilot burst in each half crack of schematically having drawn among the figure is numbered Pi (i=0,1; ..., 511) the PN intercept represent that biased exponent is first segment data after the PN sequence intercepting of i.Because PN sequence hysteresis number of chips is unit with 64chip, the then every increase 16 of PN biased exponent, PN sequence hysteresis number of chips increases by 1024 chips, just equals the length in a half crack, has marked the situation of the PN intercept appearance of numbering P0 among Fig. 5.Analysis can be known; Local PN sequence has 16 kinds of different patterns; PN sequence after all the other 496 kinds of interceptings can be that unit sequence skew obtains with the PN intercept by these 16 kinds of patterns: when the biased exponent of any two kinds of PN sequences differs 16 or 16 integral multiple; Have identical PN pattern, and on sequence leading or several PN intercepts that lag behind.Therefore, when catching, be that 0 to 15 PN pattern detects the base station pilot signals that can guarantee to find any PN biased exponent to biased exponent.

In the real system, receive the E of signal _c/ N ₀(E _cFor receiving signal averaging chip energy, N ₀Be noise power spectral density) may be very low, and the pilot channel that is used for the PN sequence capturing has only accounted for the part transmission time slot; In addition, possibly there is bigger radio frequency crystal oscillator frequency deviation in travelling carriage or is in the vehicle-mounted high-speed mobile environment.These all will increase the difficulty of PN sequence capturing.

For traditional catching method, at low E _c/ N ₀Situation under, need to increase correlation lengths (promptly increasing half timeslot number M in the preceding text) in the hope of improving acquisition performance, but exist under the situation of frequency shift (FS) at receiving terminal, the long more frequency shift (FS) of correlation length is also big more to the influence of catching the result.The tradition catching method can't be taken into account the performance of two aspects simultaneously.

Summary of the invention

In order to overcome the existing in prior technology shortcomings and deficiencies, the object of the invention is exactly the downstream synchronic PN code capturing method of a kind of CDMA2000 of being used for 1xEV-DO of proposition system.This method is applicable to that programming device (comprise but be not limited to FPGA, DSP etc.) realizes, to 16 kinds of PN pattern parallel searches, for conventional method, can have bigger frequency shift (FS) and E receiving signal _c/ N ₀When low, realize that reliable down is synchronous; And can be according to the channel circumstance of reality, configuration parameter flexibly, better utilization hardware resource.

Above-mentioned purpose of the present invention realizes through following technical scheme: be used for the downstream synchronic PN code capturing method of CDMA2000 1x EV-DO system, may further comprise the steps:

Step 1, be the data in initial M half crack of reception signal buffer memory, extract the data of each half crack pilot frequency burst position respectively current time s;

Step 2, make n=0, i=0 number is n relevant the adding up of PN intercept data of i with the data that receive n half crack of signal pilot frequency burst position and local PN pattern, obtains 1 accumulation result;

Step 3, make n=n+1, repeating step 2 until n=M-1, obtains M-1 point accumulation result;

Step 4, the M point accumulation result of step 2 and step 3 gained is asked for mould value square respectively, obtain M point mould value square;

Step 5, the M point mould value of step 4 gained square is added up, obtain mould value square accumulation result;

Step 6, with mould value square accumulation result and preset thresholding relatively if surpass preset thresholding, is then successfully caught the PN sequence phase; Otherwise i=i+1, n=0 returns step 2, until i=15;

Step 7, if the corresponding mould value square accumulation results of 16 kinds of PN patterns all have to surpass preset thresholding, s=s+1 then receives the signal original position chip of delaying time, and returns step 1, until successfully catching the PN sequence phase.

Acquisition procedure of the present invention is: storage is the reception signal of an initial 1024M chip lengths (corresponding M half crack) constantly with s, extracts the data of pilot frequency burst position in each half crack respectively; (data of the individual half of 0≤n≤M-1) crack pilot frequency burst position and local PN pattern number are n the intercept data pn of i (0≤i≤15) to n _i ⁿ(k) (k=0,1,2...95) relevant adding up; And then with M relevant accumulation result (θ _i ⁰(s), θ _i ¹(s) ..., θ _i ^M-1(s)) ask for mould value square respectively, adding up obtains mould value square accumulation result Metric again _i(s).When if current s reception signal PN sequence and local PN pattern constantly number is the sequence basic synchronization of i, Metric _i(s) will surpass preset thresholding, realize the PN sequence phase capturing.Otherwise, calculate the corresponding mould value square accumulation result of other 15 kinds of PN patterns, and judge whether to surpass preset thresholding; If the correlated results that all the other 15 kinds of PN patterns are corresponding does not all surpass thresholding, then s=s+1 receives 1 chip of signal original position time-delay, repeats above-mentioned steps, can successfully catch the PN sequence.

Can know that from above technical scheme and acquisition procedure compare with existing traditional catching method, advantage of the present invention and beneficial effect are:

1) is initial reception signal with phase place s, only, reduced amount of calculation, in programming device, use the matched filter realization the pilot frequency locations data accumulating operation of be correlated with.

2) ask the mould value square to add up again earlier to every section correlated results, frequency shift (FS) is not accumulated with the increase of the hop count that adds up the influence of correlated results.When there is the frequency shift (FS) in the certain limit in the reception signal, owing to mould value square operation makes the adverse effect of frequency shift (FS) can not accumulate along with the increase of the hop count that adds up; Frequency shift (FS) is less to the correlated results influence of 96 chip lengths of each section, so the correlation length of this method no longer receives the restriction of frequency shift (FS).Through actual verification, frequency shift (FS) and E in receiving signal existence ± 3kHz scope _c/ N ₀During>=-20dB, this method can realize the reliable down synchronic PN sequence capturing.In addition, this method is adapted at realizing on the programming device.

3) 16 kinds of PN patterns of parallel search, effectively shortened mean acquisition time: when the present invention carries out parallel search to 16 kinds of PN patterns, to each search window or phase point, detected 16 kinds of PN patterns simultaneously after, a search window or phase point again slide; Rather than as serial search of the prior art, only search for a PN pattern at every turn, a PN pattern has been searched for a frame after, the following a kind of PN pattern of search again.Parallel search of the present invention remains come calculating one by one of branchs to 16 kinds of PN patterns in concrete calculating.

Description of drawings

Fig. 1 is the sketch map of CDMA2000 1xEV-DO system forward link time-derived channel;

Fig. 2 is the sketch map of CDMA2000 1xEV-DO system forward chain time gap structure;

Fig. 3 generates the sketch map of I, Q two-way PN sequence for CDMA2000 1xEV-DO system utilizes LFSR;

Fig. 4 carries out the sketch map of descrambling to baseband signal for the multiple PN sequence of receiving terminal utilization;

Fig. 5 is the sketch map of the CDMA2000 1xEV-DO PN of system biased exponent and PN pattern;

Fig. 6 carries out the sketch map of related operation to received signal for the present invention;

Fig. 7 is the flow chart of catching of the present invention.

Embodiment

Below in conjunction with embodiment and accompanying drawing the present invention is described in further detail, but execution mode of the present invention is not limited thereto.

Embodiment

The present invention can realize on programming device that the process of carrying out related operation to received signal is as shown in Figure 6, and detailed process is as shown in Figure 7; Specifically may further comprise the steps:

Step 1, with the data that current time s is initial M half crack of reception signal buffer memory (1024M chip lengths), be designated as r (s+k) (r (s+k)=r _I(s+k)+jr _Q(s+k), k=0,1,2...1024M-1), extract the data of each half crack pilot frequency burst position respectively.

Step 2, make n=0, i=0 number is n the PN intercept data pn of i with the data that receive n half crack of signal pilot frequency burst position and local PN pattern _i ⁿ(k) relevant adding up obtains 1 accumulation result.

The length of each PN intercept data is 96 chips in the above-mentioned steps.Preferably, the said relevant matched filter that uses 96 complex tap in the programming device that is accumulated in realizes that n correlator exported as accumulation result:

${\mathrm{\θ}}_i^n\left(s\right)=\underset{k=0}{\overset{95}{\mathrm{\Σ}}}[r(s+1024\·n+464+k)\·{\mathrm{pn}}_i^n{\left(k\right)}^{*}];$

Wherein, k=0,1,2...95; Symbol * representes the complex conjugate computing.

Step 3, make n=n+1, repeating step 2 until n=M-1, obtains M-1 point accumulation result.

Step 4, with the M point accumulation result (θ of step 2 and step 3 gained _i ⁰(s), θ _i ¹(s) ..., θ _i ^M-1(s)) ask for mould value square respectively, obtain M point mould value square.The mould value square is designated as | θ _i ⁿ(s) | ²Wherein, asking for of mould value square used 2M real multipliers and M real add musical instruments used in a Buddhist or Taoist mass realization in programming device.

Step 5, the M point mould value of step 4 gained square is added up, obtains mould value square accumulation result:

${\mathrm{Metric}}_i\left(s\right)=\underset{n=0}{\overset{M-1}{\mathrm{\Σ}}}{\left|{\mathrm{\θ}}_i^n\left(s\right)\right|}^2;$

Above-mentioned mould value square is accumulated in and uses M-1 real add musical instruments used in a Buddhist or Taoist mass realization in the programming device.

Step 6, with mould value square accumulation result Metric _i(s) compare with preset thresholding,, then successfully catch the PN sequence phase if surpass preset thresholding; Otherwise i=i+1, n=0 returns step 2, until i=15.

Mould value square accumulation result Metric _i(s) realize with 1 comparator that relatively passes through of preset thresholding.

Step 7, if the corresponding mould value square accumulation result Metric of 16 kinds of PN patterns _i(s) (i=0,1,2 ..., 15) all there is not to surpass preset thresholding, then s=s+1 receives chip of signal original position time-delay, returns step 1, until successfully catching the PN sequence phase.

The foregoing description is an example with the single-time sampling, is preferred implementation of the present invention, but execution mode of the present invention is not restricted to the described embodiments, for example the principle of multiple sampling with realize and can on the said basis of present embodiment, simple extension obtain; Other any do not deviate from change, the modification done under spirit of the present invention and the principle, substitutes, combination, simplify, and all should be the substitute mode of equivalence, is included within protection scope of the present invention.

Claims (5)

1. be used for the downstream synchronic PN code capturing method of CDMA2000 1x EV-DO system, it is characterized in that may further comprise the steps:

Step 1, will be the data in initial M half crack of reception signal buffer memory, extract the data of each half crack pilot frequency burst position respectively with current time s;

Step 2, make n=0, i=0 number is n relevant the adding up of PN intercept data of i with the data that receive n half crack of signal pilot frequency burst position and local PN pattern, obtains 1 accumulation result;

Step 3, make n=n+1, repeating step 2 until n=M-1, obtains M-1 point accumulation result;

Step 4, the M point accumulation result of step 2 and step 3 gained is asked for mould value square respectively, obtain M point mould value square;

Step 5, the M point mould value of step 4 gained square is added up, obtain mould value square accumulation result;

Step 6, with mould value square accumulation result and preset thresholding relatively if surpass preset thresholding, is then successfully caught the PN sequence phase; Otherwise i=i+1, n=0 returns step 2, until i=15;

Step 7, if the corresponding mould value square accumulation results of 16 kinds of PN patterns all have to surpass preset thresholding, s=s+1 then receives the signal original position chip of delaying time, and returns step 1, until successfully catching the PN sequence phase.

2. the downstream synchronic PN code capturing method that is used for CDMA2000 1x EV-DO system according to claim 1; It is characterized in that: the length of each PN intercept data is 96 chips in the step 2, and the relevant matched filter that uses 96 complex tap in the programming device that is accumulated in is realized.

3. the downstream synchronic PN code capturing method that is used for CDMA2000 1x EV-DO system according to claim 1 is characterized in that: 2M real multipliers and M real add musical instruments used in a Buddhist or Taoist mass realization are used in asking for of the said mould value of step 4 square in programming device.

4. the downstream synchronic PN code capturing method that is used for CDMA2000 1x EV-DO system according to claim 1 is characterized in that: the said mould value of step 5 square is accumulated in and uses M-1 real add musical instruments used in a Buddhist or Taoist mass realization in the programming device.

5. the downstream synchronic PN code capturing method that is used for CDMA2000 1x EV-DO system according to claim 1 is characterized in that: 1 comparator that relatively passes through of said mould value square accumulation result of step 6 and preset thresholding is realized.

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