CN101675501A - 制造具有局部结合金属的半导体栅极的晶体管的方法 - Google Patents

制造具有局部结合金属的半导体栅极的晶体管的方法 Download PDF

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CN101675501A
CN101675501A CN200880002035A CN200880002035A CN101675501A CN 101675501 A CN101675501 A CN 101675501A CN 200880002035 A CN200880002035 A CN 200880002035A CN 200880002035 A CN200880002035 A CN 200880002035A CN 101675501 A CN101675501 A CN 101675501A
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马库斯·慕勒
格里高利·比达尔
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STMicroelectronics Crolles 2 SAS
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Abstract

本发明涉及一种形成场效应晶体管的方法，该场效应晶体包括形成在绝缘层上的栅极(G)，在与绝缘层接触的区域中该栅极具有在栅极(G)长度上的半导体中心区域(50)和横向区域(48)，该方法包括形成栅极(G)，该栅极包括绝缘层部分(32)、形成在绝缘层(32)上方的半导体层部分、和形成在半导体层上方的掩模层部分；执行掩模层部分的蚀刻以便在栅极(G)的中心只留下一部分；和使半导体栅极与沉积在栅极上方的金属起反应。

Description

制造具有局部结合金属的半导体栅极的晶体管的方法
技术领域
本发明通常涉及集成电路领域，尤其涉及制造具有隔离栅极的场效应晶体管的方法，该栅极由局部结合金属的半导体材料形成。本发明还涉及通过该方法得到的晶体管。
背景技术
通常，希望制造密度越来越高的集成电路，因此晶体管越来越小。然而，MOS晶体管的栅极尺寸的减小会产生多种寄生效应。在这些效应中，会提到短沟道效应(SCE)和漏极引致势垒降低(drain induced barrierlowering，DIBL)。短沟道效应是由栅极长度缩短时紧靠在一起的源区和漏区的静电感应引起的。当MOS晶体管截止时势垒降低效应会减小沟道中载流子(电子和空穴)的能垒，这会增加泄漏电流。这两个效应在具有N沟道的MOS晶体管的情况下会降低阈值电压(VT)或者在具有P沟道的MOS晶体管的情况下会增加阈值电压。为了在栅极长度减小时保持令人满意的阈值电压，因此需要改变MOS晶体管的结构以至少部分消除短沟道效应和势垒降低。
为了避免短沟道和势垒降低的寄生问题，2005年12月13日申请的非公开欧洲专利申请N°05/292650.8提出了一种MOS晶体管，其中栅极由多个区域形成，如图1所示。该MOS晶体管形成在衬底10上。它包括栅极G、源极S和漏极D。间隔物14形成在栅极G的每一侧上。栅极区G通过称为栅极氧化物的氧化硅层16与衬底10隔离。位于栅极氧化物层16上方的栅极G由两个区域组成。位于栅极长度的中心并靠近栅极氧化物16的第一区域18由多晶硅制成。在该多晶硅区域18的每一侧上，以及在它上方，使该栅极硅化。与栅极氧化物16接触的硅化区域20，允许得到在上方，使该栅极硅化。与栅极氧化物16接触的硅化区域20，允许得到在栅极长度方向上的栅极每一侧上高的阈值电压，而对应于位于栅极中心的多晶硅区域18的阈值电压低。栅极每一侧上的阈值电压的这种增加允许至少部分消除由上述寄生效应造成的阈值电压的减小。
在形成栅极的先前需求中提出的方法不容易控制，其中该栅极包括在位于栅极中心部分的多晶硅区域的上方和每一侧上的硅化区域。
发明内容
本发明涉及具有隔离栅极的场效应晶体管，即使它们的栅极不是由金属形成并且它们的栅极绝缘层也未必由氧化物形成，但在这里将称为MOS晶体管。
本发明的实施例的目的在于提供形成具有局部结合金属的半导体栅极的晶体管的新的和改良的方法。
根据本发明的第一方面，提供一种形成场效应晶体管的方法，该场效应晶体管包括形成在绝缘层上的栅极，在与绝缘层接触的区域中该栅极具有在栅极长度上的半导体中心区域和横向区域，该方法包括形成栅极，该栅极包括绝缘层部分、在绝缘层上方形成的半导体层部分、和在半导体层上方形成的掩模层部分；执行掩模层部分的蚀刻以便只留下栅极中心的部分；和使半导体栅极与沉积在栅极上方的金属起反应。
根据本发明的实施例，半导体层具有使金属与栅极之间的反应主要产生在高度方向的结构。
根据本发明的实施例，半导体层由多晶硅形成。
根据本发明的实施例，半导体层和金属层之间的反应是硅化反应。
根据本发明的实施例，掩模层部分的蚀刻在栅极的横向长度方向上移除的掩模层的距离小于栅极长度的一半，并且垂直移除部分掩模层。
根据本发明的实施例，在栅极的每侧上形成间隔物。
根据本发明的实施例，掩模层是由在金属和栅极的材料起反应期间不会起反应的材料制成，并且允许其被栅极的材料和例如由氧化硅制成的间隔物选择性蚀刻。
根据本发明的实施例，该金属选自从由镍、钴和钛组成的组。
根据本发明的第一方面，提供一种场效应晶体管，其包括形成在衬底上的隔离栅极，该栅极包括在栅极长度方向上的结合金属的第一半导体区、半导体中心区、和结合金属的第二半导体区。
根据本发明的实施例，第一和第二区的结合金属选自由钛、铒、镝、镱、铽、铂、铱、铪、铬、钼、钯、钨、铁、钴、钽、铑、锆和锰组成的组。
附图说明
参考附图，从以示例而非限制方式给出的实施例的以下详细描述，本发明的前述和其它目的、特征、方面和优势将变得明显，其中：
如上所述，图1是MOS晶体管的横截面图，其中该栅极包括硅化物部分；
图2A至2E是示例制造具有局部结合金属的半导体栅极的隔离栅(MOS)场效应晶体管的方法实例的连续步骤的横截面图；和
图3示例了通过根据本发明的实施例的方法得到的另一晶体管结构。
如在集成电路表示中常见的，各个图没有按比例绘制。
具体实施方式
图2A示例了对应于制造根据该发明实施例的MOS晶体管的方法实例的初始步骤结果的中间结构。
半导体衬底30具有形成在它上面的叠层，该叠层包括氧化物层32(栅极氧化物)、多晶硅层34和掩模层36。掩模层36可以由例如氧化硅(SiO2)形成。不同的层通过在衬底30上形成带的连续蚀刻步骤界定，包括氧化物层32部分、多晶硅层34部分和掩模层36部分。多晶硅带34形成MOS晶体管的栅极G。随后在栅极G的每侧上执行第一掺杂剂注入用于形成延伸的源区S和漏区D 41。随后在带32、34、36的每侧上形成间隔物38。这些间隔物38可以由例如氮化硅(SiN)形成。可以通过在整个器件的上方沉积氮化硅层并且对该层执行各向异性蚀刻来形成间隔物38，使得它仅留在栅极G的每侧上。随后执行第二掺杂剂注入以形成晶体管的源区S和漏区D 40。
在图2B的步骤中，对掩模层36执行各向同性蚀刻处理。各向同性蚀刻相对于间隔物38和多晶硅层34是选择性的。各向同性蚀刻水平并垂直地移除掩模层36。执行该蚀刻以横向移除所选择量的层36以便在多晶硅层34的上方仅有区域44留在栅极的中心。区域44例如为大致梯形形状。在下文中将区域44称为“掩模”。为了不完全蚀刻掩模层36并且使最终的掩模44具有所希望的长度，掩模层36的初始厚度优选大于所希望执行的蚀刻深度。各向同性蚀刻允许在栅极G的多晶硅层34的中心自动对准掩模44。
应该理解，该发明可以应用于具有极短栅极长度的晶体管，例如小于200nm。举例来说，对于具有栅极长度为140nm的栅极，如果希望得到具有长度为40nm的掩模44，掩模层36则将优选具有大于60nm的厚度。
在图2C的步骤中，在图2B的整个结构的上方沉积金属层46。层46的金属是允许与多晶硅层34硅化反应的金属，该反应优选包括金属在多晶硅层34中扩散。例如该金属为镍。
在图2D的步骤中，硅化反应发生在层46的金属和栅极34的多晶硅之间。硅化反应还发生在层46的金属和晶体管的源极S和漏极D之间。
在多晶硅层34中，硅化反应在栅极G的每侧上形成硅化区48。多晶硅层34的中心部分50由于受到掩模44的保护而没有被硅化。为了避免中心部分50的硅化，可以提供特定结构的多晶硅栅极，例如柱状结构。在多晶硅柱状结构中，硅粒在栅极G中在高度方向上延伸排列。该特定的多晶硅结构例如可以通过选择的具有适当的沉积温度和压力的LPCVD工艺(低压化学汽相沉积)获得。该颗粒在栅极的高度方向上拉长，相比栅极的长度方向和深度方向，该金属更易在栅极的高度方向上扩散。此外，同时，在层46的金属和源区S和漏区D之间会发生硅化反应，由此在源极和漏极的上方形成了硅化区52。与图2D中示例的相反，图2D没有按比例绘制，源区S和漏区D的硅化区域例如具有的深度约等于栅极G的硅化区域的深度。一旦发生了硅化反应，在整个器件的上方就会留下金属没有反应的金属层54。
在图2E的步骤中，通过连续选择性蚀刻移除了剩下的金属54和掩模44。接下来，以已知的方式，沉积绝缘层和互连导电层用于使该结构的栅极G、源区S和漏区D连接到其中形成了晶体管的集成电路的其它元件。
图3示例了通过根据该发明实施例的制造方法得到的结构的变形。图3和图2E之间的主要区别在于，在图3中，图2E的两个横向硅化区域48在栅极的顶部结合在一起。本领域的技术人员应该明白，为了得到图3的结构，改变图2A至2D的方法步骤的某些参数，例如扩散的持续时间、掩模的尺寸、和/或栅极多晶硅的特征。
如上所述，在这里描述的MOS晶体管结构不限制于金属氧化物半导体结构。可以有许多变形，例如涉及栅极G的材料、层46的金属、栅极隔离32的材料、掩模层36的材料和获得自动对准掩模44的方法。
栅极层34可以由在硅化或者锗化反应中能够结合金属的任何半导体材料形成。尤其是，层34可以由硅、锗或硅锗形成，并且半导体材料可以具有多种形式，例如单晶质、多晶质或者非晶质。
金属层46可以是允许与栅极层34的半导体材料硅化或者锗化反应的任何金属。金属层46优选由钛、铒、镝、镱、铽、铂、铱、铪、铬、钼、钯、钨、铁、钴、钽、铑、锆和锰组成的组中的金属形成。在硅化或锗化期间，层46的金属的主要反应是金属向栅极层34扩散，而不可颠倒。使形成硅化或锗化区域的方法适合于使用的金属(温度、反应时间......)。
栅极的绝缘层32可以由任何类型的绝缘体，例如氮化硅(Si3N4)、氧化物(HfO2...)、具有高介电常数(高-k)的任何材料(Al2O3、Y2O3、La2O3、Ta2O5、TiO2、HfO2、ZrO2、BaTiO3、BaZrO3、ZrSiO4、HfZrO2......)、或者在形成硅化物或者锗化物的反应期间不会发生反应的所有其它绝缘材料形成。
掩模层36可以由氧化硅(SiO2)、氮氧化物SiOxNy、氮化硅Si3N4制成或者油具有两层的结构、例如在氧化物上方的氮化物制成。掩模层也可以由在硅化期间不发生反应的并且被由组成层34和间隔38的材料选择性蚀刻的任何其它材料制成。
在所描述的实施例中，在图2A和2B的步骤之间执行的掩模层36的蚀刻是各向同性蚀刻。取决于用于形成掩模层或者层36的材料，和这些材料的特性(水平和垂直蚀刻速度)，可以结合各向异性和各向同性蚀刻步骤以得到所需要的形状和尺寸的掩模44。
因此描述了本发明的至少一个示例性实施例，对于本领域的技术人员将容易进行各种变更、变形和改进。这些变更、变形和改进意指在该发明的精神和范围内。因此，前面的描述仅是实例而不是用于起限制作用的。本发明仅限制为下面的权利要求中的限定和它的等价物。

Claims (10)

1.一种形成场效应晶体管的方法，该场效应晶体管包括形成在绝缘层上的栅极(G)，在与该绝缘层接触的区域中，该栅极具有在栅极(G)长度上的半导体中心区域(50)和横向区域(48)，该方法包括：
形成栅极(G)，该栅极包括绝缘层部分(32)、形成在绝缘层上方的半导体层部分(34)、和形成在半导体层上方的掩模层部分(36)；
执行掩模层部分(36)的蚀刻以便在栅极(G)的中心只留下一部分(44)；和
使半导体栅极(34)与沉积在栅极上方的金属(46)起反应。
2.如权利要求1所述的方法，其中半导体层(34)具有使金属和栅极之间的反应主要产生在高度方向(G)上的结构。
3.如权利要求2所述的方法，其中半导体层(34)由多晶硅形成。
4.如权利要求3所述的方法，其中半导体层(34)和金属层(36)之间的反应是硅化反应。
5.如权利要求1所述的方法，其中掩模层部分(36)的蚀刻在栅极的横向长度方向上移除的掩模层的距离小于栅极长度的一半，并且垂直移除掩模层(36)的部分。
6.如权利要求1所述的方法，其中在栅极(G)的每侧上形成间隔物。
7.如权利要求1所述的方法，其中掩模层(36)是由在金属和栅极材料之间起反应的期间不会起反应的材料制成，并且允许其被栅极的材料和例如由氧化硅制成的间隔物选择性蚀刻。
8.如权利要求1所述的方法，其中金属(46)选自由镍、钴和钛组成的组。
9.一种场效应晶体管，包括形成在衬底(30)上的隔离栅极(G)，该栅极包括在栅极的长度方向上的结合金属(46)的第一半导体区域(48)、半导体中心区域(50)、和结合金属(46)的第二半导体区域(48)。
10.如权利要求9所述的场效应晶体管，其中第一和第二区域的结合的金属选自由钛、铒、镝、镱、铽、铂、铱、铪、铬、钼、钯、钨、铁、钴、钽、铑、锆和锰组成的组。
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