CN101674085B - Sampling hold circuit applied to analogue-to-digital converter - Google Patents
Sampling hold circuit applied to analogue-to-digital converter Download PDFInfo
- Publication number
- CN101674085B CN101674085B CN200810119800XA CN200810119800A CN101674085B CN 101674085 B CN101674085 B CN 101674085B CN 200810119800X A CN200810119800X A CN 200810119800XA CN 200810119800 A CN200810119800 A CN 200810119800A CN 101674085 B CN101674085 B CN 101674085B
- Authority
- CN
- China
- Prior art keywords
- node
- pipe
- sampling
- pmos
- nmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Electronic Switches (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a sampling hold circuit applied to an analogue-to-digital converter, which comprises a sampling switch bootstrap circuit (10), a sampling network (20) and a source follower (30). The output end of the sampling switch bootstrap circuit (10) is connected with the input end of the sampling network (20); the output end of the sampling network (20) is connected with the input end of the source follower (30); and a thirteenth node (13) of the source follower (30) is the output Vout of the sampling hold circuit. Compared with the conventional sampling hold circuit, the sampling hold circuit applied to the analogue-to-digital converter eliminates the nonlinearity of a switch conducting resistance, reduces signal distortion and improves the accuracy of the circuit due to the adoption of the bootstrap circuit.
Description
Technical field
The present invention relates to sampling and keep (Track and Hold) circuit engineering field, particularly a kind of sampling that contains boostrap circuit that is applied to analog to digital converter keeps (Track and Hold) circuit.
Background technology
Sampling hold circuit (sampling/retainer) is called sample/hold amplifier again.General sampling hold circuit all adopts switched-capacitor circuit to realize.The circuit that switched-capacitor circuit is made up of the switch and the capacitor of subject clock signal control.It is to utilize the storage of electric charge and shift the various processing capacities that realize signal.In side circuit, the circuit that only constitutes with switch and capacitor does not often meet the demands sometimes, thus manyly combine with amplifier exclusive disjunction amplifier, comparator etc., with generation, conversion and the processing of the realization signal of telecommunication.
Fig. 1 is a basic switched capacitor amplifier circuit.The control action of three switches is among Fig. 1: S
1And S
3Make C respectively
1Left pole plate and V
InLink to each other S with ground
2The unit gain feedback is provided.At first, S
1, S
2Connect S
3Disconnect V
B=V
Out≈ 0, C
1Both end voltage is approximately equal to V
InAt t=t
0Constantly, S
1, S
2Disconnect S
3Connect A point ground connection.Because V
AFrom V
In0Output voltage changes to 0, so will change to V from 0
In0C
1/ C
2
The numerous characteristics of circuit shown in Figure 1 makes it be different from circuit continuous time, and it has the sampling function, reaches stable when output voltage has the sufficient time, so the open-loop gain that feedback capacity can step-down amplifier.
Discrete time action need switch is sampled, and needs high input impedance could obtain the charge stored amount reliably.CMOS technology has simple switch and high input impedance, so CMOS technology becomes the main selection in the data sampling application.
When analog signal being carried out the A/D conversion, need certain change-over time, in this change-over time, it is constant substantially that analog signal will keep, and could guarantee conversion accuracy like this.Sampling hold circuit is the circuit of realizing this function, is in " sampling " or " maintenance " two kinds of operating states under input logic level control.The output tracking of circuit input analog signal under " sampling " state, the instantaneous input analog signal that the output of circuit maintenance was last time sampled the finish time under " maintenances " state is till entering next time sample states.The most basic sampling hold circuit is made up of analog switch, memory element (maintenance electric capacity) and buffering amplifier.Its principle as shown in Figure 2.
Among Fig. 2, when Vc is sampled level, switch s conducting, analog signal Vi charges to CH by s, the variation of output voltage V o trace simulation signal; When Vc was the maintenance level, switch s disconnected, and output voltage V o remains on the input signal values that analog switch disconnects moment.Realize that sampling keeps function.
Along with the development of technology, high-speed high accuracy has become the design object of pipeline a/d converter, and sampling hold circuit is as the core of pipeline organization A/D converter, and its performance has determined the performance of whole A/D converter.Therefore, the sampling hold circuit of a high-speed, high precision of design just seems particularly important.The required precision of sampling hold circuit generally is subject to the finite gain of amplifier and the error that switching circuit causes.On the one hand, amplifier is not an ideal operational amplifier, exists gain error; On the other hand because sampling hold circuit is a kind of utilization of switched-capacitor circuit, switch-charge injection effect and clock feedthrough that itself exists, and switch conduction resistance is non-linear, all can influence the precision of sampling hold circuit.For electric charge injection effect and clock feedthrough, utilize the conducting sequential of switch, it is irrelevant that electric charge is injected with input signal, eliminates by the fully differential structure again.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is, a kind of sampling hold circuit that is applied to analog to digital converter is provided, and to eliminate the non-linear of switch conduction resistance, reduces distorted signals, improves the circuit precision.
(2) technical scheme
For achieving the above object, the invention provides a kind of sampling hold circuit that is applied to analog to digital converter, this sampling hold circuit comprises sampling switch boostrap circuit 10, sampling network 20 and source follower 30, the output of this sampling switch boostrap circuit 10 is connected with the input of sampling network 20, the output of this sampling network 20 is connected with the input of source follower 30, and the 13rd node 13 of source follower 30 is the output Vout of this sampling hold circuit; Wherein:
In this sampling switch boostrap circuit 10, meet sinusoidal input signal Vin as the 4th node 4 of input endpoint, the 22nd node 22 meets V1, and the 23rd node 23 meets V2; Adopt first inverter 40 that constitutes by device the 9th PMOS pipe M9 and the tenth NMOS pipe M10 to be connected between the 1st node 1 and the 2nd node 2, adopt between the 1st node 1 and the 3rd node 3 and manage M11 and the 12 NMOS by device the 11 PMOS and manage second inverter 50 that M12 constitutes and be connected; Source electrode, first capacitor C 1 of the drain electrode of the one PMOS pipe M1, the 5th PMOS pipe M5 are connected in the 5th node 5, drain electrode, first capacitor C 1 of the source electrode of the 2nd NMOS pipe M2, the 6th NMOS pipe M6 are connected in the 6th node 6, source electrode, second capacitor C 2 of the drain electrode of the 3rd PMOS pipe M3, the 7th PMOS pipe M7 is connected in the source electrode of the 7th node 7, the four NMOS pipe M4, drain electrode, second capacitor C 2 of the 8th NMOS pipe M8 is connected in the 8th node 8; The 9th node 9 is connected in power supply VCC, and the 10th node 10 is connected in ground GND;
In this sampling switch boostrap circuit 10, the source electrode of the drain electrode of the 13 NMOS pipe M13, the 14 NMOS pipe M14 is connected in the source electrode of Section 11 point 11, the 15 PMOS pipe M15, the drain electrode that the 16 PMOS manages M16 is connected in the 12nd node 12; Source electrode and the substrate of the 5th PMOS pipe M5 are connected in the 5th node 5, source electrode and the substrate of the 7th PMOS pipe M7 are connected in the 7th node 7, the source electrode of the 17 PMOS pipe (M17) and substrate are connected in the 13rd node (13) with the 4th electric capacity (C4), in order to elimination by bulk effect cause non-linear; Source electrode, the 15 PMOS that the source electrode of the drain electrode of the 5th PMOS pipe M5, the 13 NMOS pipe M13, the control end of the first nmos switch pipe Ms1 are connected in the 14th node 14, the four NMOS pipe M4 manages the drain electrode of M15, the control end of the 2nd PMOS switching tube Ms2 is connected in the 15th node 15; The 16th node the 16, the 17th node 17 links to each other with power supply VCC, and the 18th node the 18, the 25th node the 25, the 26th node the 26, the 27th node 27 links to each other with ground GND;
In this sampling switch boostrap circuit 10, the 19th node the 19, the 20th node 20 links to each other with power supply VCC, and the 21st node 21 links to each other with ground GND; The source electrode of the tenth NMOS pipe M10 links to each other with the 6th node 6; The 22nd node 22 meets voltage V1, and V1 is less than the value of supply voltage VCC: the 23rd node 23 meets voltage V2, and V2 is poor less than supply voltage VCC and Vin maximum.
In the such scheme, frequency, the phase place of the 2nd node the 2, the 3rd node 3 clocks are identical, and be identical with the 1st node 1 clock frequency, phase phasic difference 180 degree.
In the such scheme, in sampling network 20, the drain electrode of the source electrode of the source electrode of the first nmos switch pipe Ms1, the 2nd PMOS switching tube Ms2, the 7th PMOS pipe M7 is connected in the 4th node 4, control end, the 3rd capacitor C 3 of the drain electrode of the drain electrode of the first nmos switch pipe Ms1, the 2nd PMOS switching tube Ms2, the 17 PMOS pipe M17 are connected in the 24th node 24, the first nmos switch pipe Ms1 and the 2nd PMOS switching tube Ms2 form transmission gate, make the first nmos switch pipe and conducting simultaneously of the 2nd PMOS switching tube or disconnection by signal controlling.
(3) beneficial effect
This sampling hold circuit that is applied to analog to digital converter provided by the invention, keep (Track and Hold) circuit to compare with traditional sampling,, eliminated the non-linear of switch conduction resistance owing to adopt boostrap circuit, reduce distorted signals, improved the circuit precision.
Description of drawings
Fig. 1 is the switched capacitor amplifier schematic diagram;
Fig. 2 is basic sampling hold circuit schematic diagram;
Fig. 3 is the circuit diagram that is applied to the sampling hold circuit of analog to digital converter provided by the invention;
Fig. 4 is the block diagram that is applied to the sampling hold circuit of analog to digital converter provided by the invention;
Fig. 5 is the circuit diagram of sampling switch boostrap circuit;
Fig. 6 is the circuit diagram of sampling network circuit;
Fig. 7 is the circuit diagram of source follower circuit.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 3 and Figure 4, this sampling hold circuit that is applied to analog to digital converter provided by the invention comprises sampling switch boostrap circuit 10, sampling network 20 and source follower 30.The output of this sampling switch boostrap circuit 10 is connected with the input of sampling network 20, and the output of this sampling network 20 is connected with the input of source follower 30, and the 13rd node 13 of source follower 30 is the output Vout of this sampling hold circuit.
In this sampling switch boostrap circuit 10, meet sinusoidal input signal Vin as the 4th node 4 of input endpoint, the 22nd node 22 meets V1, and the 23rd node 23 meets V2.Adopt first inverter 40 that constitutes by device the 9th PMOS pipe M9 and the tenth NMOS pipe M10 to be connected between the 1st node 1 and the 2nd node 2, adopt between the 1st node 1 and the 3rd node 3 and manage M11 and the 12 NMOS by device the 11 PMOS and manage second inverter 50 that M12 constitutes and be connected.Source electrode, first capacitor C 1 of the drain electrode of the one PMOS pipe M1, the 5th PMOS pipe M5 are connected in the 5th node 5, drain electrode, first capacitor C 1 of the source electrode of the 2nd NMOS pipe M2, the 6th NMOS pipe M6 are connected in the 6th node 6, source electrode, second capacitor C 2 of the drain electrode of the 3rd PMOS pipe M3, the 7th PMOS pipe M7 is connected in the source electrode of the 7th node 7, the four NMOS pipe M4, drain electrode, second capacitor C 2 of the 8th NMOS pipe M8 is connected in the 8th node 8.The 9th node 9 is connected in power supply VCC, and the 10th node 10 is connected in ground GND.
In this sampling switch boostrap circuit 10, the source electrode of the drain electrode of the 13 NMOS pipe M13, the 14 NMOS pipe M14 is connected in the source electrode of Section 11 point 11, the 15 PMOS pipe M15, the drain electrode that the 16 PMOS manages M16 is connected in the 12nd node 12; Source electrode and the substrate of the 5th PMOS pipe M5 are connected in the 5th node 5, source electrode and the substrate of the 7th PMOS pipe M7 are connected in the 7th node 7, the source electrode of the 17 PMOS pipe (M17) and substrate are connected in the 13rd node (13) with the 4th electric capacity (C4), in order to elimination by bulk effect cause non-linear; The source electrode of the drain electrode of the 5th PMOS pipe M5, the 13 NMOS pipe M13, the control end of the first nmos switch pipe Ms1 are connected in the source electrode of the 14th node 14, the four NMOS pipes (M4), the drain electrode of the 15 PMOS pipe M15, the control end of the 2nd PMOS switching tube Ms2 and are connected in the 15th node 15; The 16th node the 16, the 17th node 17 links to each other with power supply VCC, and the 18th node the 18, the 25th node the 25, the 26th node the 26, the 27th node 27 links to each other with ground GND.
In this sampling switch boostrap circuit 10, the 19th node the 19, the 20th node 20 links to each other with power supply VCC, and the 21st node 21 links to each other with ground GND; The source electrode of the tenth NMOS pipe M10 links to each other with the 6th node 6; The 22nd node 22 meets voltage V1, and V1 is less than the value of supply voltage VCC: the 23rd node 23 meets voltage V2, and V2 is poor less than supply voltage VCC and Vin maximum, i.e. V2＜[VCC-(Vin maximum)].
Frequency, the phase place of the 2nd node the 2, the 3rd node 3 clocks are identical, and be identical with the 1st node 1 clock frequency, phase phasic difference 180 degree.At the 1st node 1 incoming clock Φ, the 2nd node the 2, the 3rd node 3 incoming clocks
, Φ with
Frequency is identical, and phase phasic difference 180 degree are controlled circuit.
In sampling network 20, the drain electrode of the source electrode of the source electrode of the first nmos switch pipe Ms1, the 2nd PMOS switching tube Ms2, the 7th PMOS pipe M7 is connected in the 4th node 4, control end, the 3rd capacitor C 3 of the drain electrode of the drain electrode of the first nmos switch pipe Ms1, the 2nd PMOS switching tube Ms2, the 17 PMOS pipe M17 are connected in the 24th node 24, the first nmos switch pipe Ms1 and the 2nd PMOS switching tube Ms2 form transmission gate, make Ms1 and Ms2 conducting simultaneously or disconnection by signal controlling.
By above analysis, following specific design original shape circuit.
Operation principle:
Control end points (i.e. the 9th node) 9 of the 13 NMOS pipe M13 links to each other with power supply (VCC), and control end points (i.e. the 10th node) 10 of the 15 PMOS pipe M15 links to each other with ground (GND), makes M13, M15 conducting all the time.
When the clock signal Phi when low, M1, M3, M6, M8, M14, M16 conducting, M2, M4, M5, M7 disconnect.First capacitor C, 1 two ends: the voltage of the 5th node 5 equates with the voltage of the 22nd node 22, is V1, and the voltage of the 6th node 6 equates with the voltage of the 18th node 18, is 0, and the voltage difference of the 5th node the 5, the 6th node 6 of C1 is V1.M
S1 control end points (i.e. the 14th node), 14 voltages equate with the voltage of the 10th node 10, are 0, M
S1 disconnects.Second capacitor C, 2 two ends: the voltage of the 7th node 7 equates with the voltage of the 16th node 16, is supply voltage (VCC), and the voltage of the 8th node 8 equates with the voltage of the 23rd node 23, is V2, and the voltage difference of the 7th node the 7, the 8th node 8 of C2 is (VCC-V2).M
SThe voltage of 2 control ends the 15th node 15 equates with the voltage of the 17th node 17, is supply voltage (VCC), M
S2 disconnect.This moment, 3 discharges of the 3rd capacitor C were hold mode.The 24th node 24 output voltage V o remain on the input signal values that analog switch disconnects moment.
When clock signal Phi when being high, M1, M3, M6, M8, M14, M16 disconnect M2, M4, M5, M7 conducting, first capacitor C, 1 two ends: the voltage of the 6th node 6 equates with the voltage of the 4th node 4, be Vin, the big V1 of voltage of voltage ratio the 6th node 6 of the 5th node 5 is V1+Vin.M
SThe voltage of 1 control end the 14th node 14 equates with the voltage of the 5th node 5, is V1+Vin, M
SThe voltage of 1 input the 4th node 4 is Vin, M
S1 control end and input difference are stable, M
S1 conducting, working stability.Second capacitor C, 2 two ends: the voltage of the 7th node 7 equates with the voltage of the 4th node 4, is Vin, and the voltage little (VCC-V2) of voltage ratio the 7th node 7 of the 8th node 8 is V2+Vin-VCC.M
SThe voltage of 2 control ends the 15th node 15 equates with the voltage of the 8th node 8, is V2+Vin-VCC, M
SThe voltage of 2 inputs the 4th node 4 is Vin, M
S2 control ends and input difference are stable, M
S2 conductings, working stability.Be sample states this moment.The variation of the 24th node 24 output voltage V o trace simulation signals.
The 24th node 24 output voltage V o are by source follower circuit (30), and the 13rd node 13 is exported Vout frequencies, phase invariant, and is more stable.
Realize that boostrap circuit and sampling keep function.
Because the PMOS pipe is good to the transmission performance of input signal Vin high level, and the NMOS pipe is good to the low level transmission performance of input signal Vin.So use the first nmos switch pipe Ms1 and the 2nd PMOS switching tube Ms2 to form transmission gate, make two pipe conducting simultaneously or disconnections by signal controlling, when sampling, can make signal Vin can obtain the transmission of whole range and do not have level breakdown.
Wherein the substrate of device the 5th PMOS pipe M5 is connected at the 5th node 5 with source electrode, the substrate of device the 7th PMOS pipe M7 is connected at the 7th node 7 with source electrode, the source electrode of device the 17 PMOS pipe (M17) and substrate are connected in the 13rd node (13) with the 4th electric capacity (C4), in order to elimination by bulk effect cause non-linear.
When clock signal Φ is high, device the tenth NMOS pipe M10 conducting, the voltage of the 2nd node 2 equates with the voltage of the 6th node 6, be Vin, the voltage of device the 5th PMOS pipe M5 input the 5th node 5 is V1+Vin, stable with the voltage difference of control end the 2nd node 2, guarantee device the 5th PMOS pipe M5 conducting, working stability.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. sampling hold circuit that is applied to analog to digital converter, it is characterized in that, this sampling hold circuit comprises sampling switch boostrap circuit (10), sampling network (20) and source follower (30), the output of this sampling switch boostrap circuit (10) is connected with the input of sampling network (20), the output of this sampling network (20) is connected with the input of source follower (30), and the 13rd node (13) of source follower (30) is the output Vout of this sampling hold circuit; Wherein:
In this sampling switch boostrap circuit (10), meet sinusoidal input signal Vin as the 4th node (4) of input endpoint, the 22nd node (22) meets V1, and the 23rd node (23) meets V2;
Adopt first inverter (40) that constitutes by device the 9th PMOS pipe (M9) and the tenth NMOS pipe (M10) to be connected between the 1st node (1) and the 2nd node (2), adopt between the 1st node (1) and the 3rd node (3) and manage second inverter (50) that (M11) and the tenth NMOS manage (M12) formation by device the 11 PMOS and be connected;
Source electrode, first capacitor C 1 of the drain electrode of the one PMOS pipe (M1), the 5th PMOS pipe (M5) are connected in the 5th node (5), drain electrode, first capacitor C 1 of the source electrode of NMOS pipe (M2), the 6th NMOS pipe (M6) are connected in the 6th node (6), source electrode, second capacitor C 2 of the drain electrode of the 3rd PMOS pipe (M3), the 7th PMOS pipe (M7) are connected in the 7th node (7), and drain electrode, second capacitor C 2 of the source electrode of the 4th NMOS pipe (M4), the 8th NMOS pipe (M8) are connected in the 8th node (8);
The 9th node (9) is connected in power supply VCC, and the 10th node (10) is connected in ground GND;
In this sampling switch boostrap circuit (10), the source electrode of the drain electrode of the 13 NMOS pipe (M13), the 14 NMOS pipe (M14) is connected in Section 11 point (11), and the drain electrode of the source electrode of the tenth PMOS pipe (M15), the 16 PMOS pipe (M16) is connected in the 12nd node (12);
The source electrode and the substrate of PMOS pipe (M5) are connected in the 5th node (5), the source electrode and the substrate of the 7th PMOS pipe (M7) are connected in the 7th node (7), the source electrode of the 17 PMOS pipe (M17) and substrate are connected in the 13rd node (13) with the 4th electric capacity (C4), in order to elimination by bulk effect cause non-linear;
The source electrode of the drain electrode of the 5th PMOS pipe (M5), the 13 NMOS pipe (M13), the control end of the first nmos switch pipe (Ms1) are connected in the 14th node (14), and the source electrode of the 4th NMOS pipe (M4), the drain electrode of the 15 PMOS pipe (M15), the control end of the 2nd PMOS switching tube (Ms2) are connected in the 15th node (15);
The 16th node (16), the 17th node (17) link to each other with power supply VCC, and the 18th node (18), the 25th node (25), the 26th node (26), the 27th node (27) link to each other with ground GND;
In this sampling switch boostrap circuit (10), the 19th node (19), the 20th node (20) link to each other with power supply VCC, and the 21st node (21) links to each other with ground GND; The source electrode of the tenth NMOS pipe (M10) links to each other with the 6th node (6); The 22nd node (22) meets voltage V1, and V1 is less than the value of supply voltage VCC: the 23rd node (23) meets voltage V2, and V2 is poor less than supply voltage VCC and Vin maximum.
2. the sampling hold circuit that is applied to analog to digital converter according to claim 1 is characterized in that, frequency, the phase place of the 2nd node (2), the 3rd node (3) clock are identical, and be identical with the 1st node (1) clock frequency, phase phasic difference 180 degree.
3. the sampling hold circuit that is applied to analog to digital converter according to claim 1, it is characterized in that, in sampling network (20), the source electrode of the first nmos switch pipe (Ms1), the source electrode of the 2nd PMOS switching tube (Ms2), the drain electrode of the 7th PMOS pipe (M7) is connected in the 4th node (4), the drain electrode of the first nmos switch pipe (Ms1), the drain electrode of the 2nd PMOS switching tube (Ms2), the control end of the 17 PMOS pipe (M17), the 3rd electric capacity (C3) is connected in the 24th node (24), the first nmos switch pipe (Ms1) and the 2nd PMOS switching tube (Ms2) are formed transmission gate, make the first nmos switch pipe and conducting simultaneously of the 2nd PMOS switching tube or disconnection by signal controlling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810119800XA CN101674085B (en) | 2008-09-10 | 2008-09-10 | Sampling hold circuit applied to analogue-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810119800XA CN101674085B (en) | 2008-09-10 | 2008-09-10 | Sampling hold circuit applied to analogue-to-digital converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101674085A CN101674085A (en) | 2010-03-17 |
| CN101674085B true CN101674085B (en) | 2011-12-21 |
Family
ID=42021115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810119800XA Expired - Fee Related CN101674085B (en) | 2008-09-10 | 2008-09-10 | Sampling hold circuit applied to analogue-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101674085B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8816887B2 (en) * | 2012-09-21 | 2014-08-26 | Analog Devices, Inc. | Sampling circuit, a method of reducing distortion in a sampling circuit, and an analog to digital converter including such a sampling circuit |
| CN103475352B (en) * | 2013-09-06 | 2017-07-25 | 深圳市芯海科技有限公司 | The detection circuit of capacitance touch button |
| US9224499B2 (en) * | 2014-02-07 | 2015-12-29 | Infineon Technologies Ag | Pre-charge sample-and-hold circuit and method for pre-charging a sample-and-hold circuit |
| CN110022064B (en) * | 2019-03-29 | 2020-07-14 | 成都市易冲半导体有限公司 | Slope compensation circuit capable of eliminating influence on loading capacity of current step-down transformer |
| CN111900986B (en) * | 2020-08-10 | 2022-08-16 | 中国电子科技集团公司第二十四研究所 | Follow-up hold switch circuit |
| CN113014259A (en) * | 2021-02-25 | 2021-06-22 | 中国科学院微电子研究所 | Sampling switch circuit and analog-to-digital converter |
| CN114172518A (en) * | 2022-02-14 | 2022-03-11 | 山东兆通微电子有限公司 | Sampling hold circuit and analog-to-digital converter |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6072355A (en) * | 1998-01-22 | 2000-06-06 | Burr-Brown Corporation | Bootstrapped CMOS sample and hold circuitry and method |
| US6384758B1 (en) * | 2000-11-27 | 2002-05-07 | Analog Devices, Inc. | High-speed sampler structures and methods |
| CN2586314Y (en) * | 2002-12-31 | 2003-11-12 | 重庆大学 | Relative double-sampling hold circuit with new structure |
| CN1697980A (en) * | 2003-08-25 | 2005-11-16 | 爱知制钢株式会社 | Magnetic sensor |
-
2008
- 2008-09-10 CN CN200810119800XA patent/CN101674085B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6072355A (en) * | 1998-01-22 | 2000-06-06 | Burr-Brown Corporation | Bootstrapped CMOS sample and hold circuitry and method |
| US6384758B1 (en) * | 2000-11-27 | 2002-05-07 | Analog Devices, Inc. | High-speed sampler structures and methods |
| CN2586314Y (en) * | 2002-12-31 | 2003-11-12 | 重庆大学 | Relative double-sampling hold circuit with new structure |
| CN1697980A (en) * | 2003-08-25 | 2005-11-16 | 爱知制钢株式会社 | Magnetic sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101674085A (en) | 2010-03-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101674085B (en) | Sampling hold circuit applied to analogue-to-digital converter | |
| CN101277112B (en) | Low-power consumption assembly line a/d converter by sharing operation amplifier | |
| CN101777916B (en) | Charge coupling assembly line A/D converter | |
| CN101692603B (en) | Gain bootstrap type C class reverser and application circuit thereof | |
| CN103178813B (en) | Low-offset full-motion comparator | |
| CN103346765A (en) | Gate-source following sampling switch | |
| CN101517898A (en) | A/D converter | |
| CN103703685A (en) | Distributed bootstrap switch | |
| CN101577545A (en) | Dual bootstrap and voltage compensation technology-based A/D converter sampling switch | |
| CN101587753A (en) | A kind of simulating signal sample circuit and a kind of switched-capacitor circuit | |
| CN105119604A (en) | Bootstrap switch circuit suitable for sampling of an analog-to-digital converter in a low power and voltage condition | |
| CN111900986B (en) | Follow-up hold switch circuit | |
| CN103944571A (en) | High-speed configurable assembly line analog-to-digital converter | |
| CN216625715U (en) | Floating type dynamic latch comparator and successive approximation type analog-to-digital converter | |
| CN116978429A (en) | Equivalent circuit of linear memristor | |
| CN103944570B (en) | Programmable gain digital-analog unit and analog-to-digital converter | |
| CN1877999A (en) | Analog-to-digital converter for sampling input flow line | |
| CN104868916A (en) | Analog to digital converter and control method thereof | |
| CN1561000B (en) | Pipeline structure analogue/digital converter of controlling input common-mode drift | |
| CN104375546A (en) | Chopped wave band-gap reference device with switched-capacitor filter | |
| CN204559546U (en) | Analog to digital converter | |
| CN101546998B (en) | High-precision sampling switch adopting grate source tracking technology | |
| CN201766574U (en) | High-speed common mode insensitive charge comparator circuit | |
| US8576106B2 (en) | Analog-digital converter | |
| CN106160459A (en) | The charge pump circuit system of fast transient response |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111221 Termination date: 20140910 |
|
| EXPY | Termination of patent right or utility model |