CN110022064B - Slope compensation circuit capable of eliminating influence on loading capacity of current step-down transformer - Google Patents

Slope compensation circuit capable of eliminating influence on loading capacity of current step-down transformer Download PDF

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Publication number
CN110022064B
CN110022064B CN201910247031.XA CN201910247031A CN110022064B CN 110022064 B CN110022064 B CN 110022064B CN 201910247031 A CN201910247031 A CN 201910247031A CN 110022064 B CN110022064 B CN 110022064B
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current
nmos tube
ramp
circuit
slope
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CN110022064A (en
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金学成
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Chengdu Yichong Wireless Power Technology Co ltd
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Chengdu Yichong Wireless Power Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Abstract

The invention relates to the technical field of integrated circuits, and discloses a slope compensation circuit capable of eliminating influence on the loading capacity of a current step-down transformer. The device comprises a ramp voltage generating circuit, a ramp current generating circuit, a mirror current circuit and a sampling circuit; the ramp current generating circuit is connected with a voltage point A which is in ramp rising in the ramp voltage generating circuit to generate a first ramp rising current; the mirror current circuit is matched with the ramp current generating circuit to generate a second ramp rising current of a mirror image; the sampling circuit samples and converts the direct current component of the ramp voltage generating circuit into a current using a sample/hold circuit (including a transmission gate and a capacitor). By adopting the technical scheme of the invention, the direct current component of the slope voltage is sampled, and the influence of the direct current component is eliminated in the final slope compensation current, so that the maximum load capacity of the buck converter is not influenced while the circuit is ensured not to generate subharmonic oscillation, and the load capacity of the converter is optimized.

Description

Slope compensation circuit capable of eliminating influence on loading capacity of current step-down transformer
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a slope compensation circuit capable of eliminating the influence on the loading capacity of a current step-down transformer.
Background
In a peak current mode buck converter, slope compensation is required to prevent the circuit from stability problems of sub-harmonic oscillation.
In subsequent circuits, the switching point of a Pulse Width Modulation (PWM) comparator is typically set to:
Ieao＝Islope+Isense
wherein, IeaoIs the output current of the error amplifier ea, IsenseSampling current, I, for inductor currentslopeThe current is compensated for the ramp. Since the maximum output current of EA has an upper limit, the slope compensation current IslopeThe larger the peak value sampled by the inductor current, the smaller the corresponding load current. The slope compensation of the circuit needs to compensate a slope, and the traditional slope compensation circuit introduces a large direct current component. Therefore, in the conventional slope compensation technology (whether adopting the segmented compensation or the nonlinear compensation), the maximum loading capacity of the current step-down transformer is affected as long as the slope compensation is introduced.
The prior art improves the traditional slope compensation circuit, and the slope compensation quantity can be dynamically adjusted according to different duty ratios. However, such an improvement mainly aims at improving stability, and still introduces a dc component to a different extent in the slope compensation, and does not eliminate the influence of the slope compensation on the load carrying capacity.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: in view of the above existing problems, a slope compensation circuit is provided which can eliminate the influence on the load capacity of a current step-down transformer.
The technical scheme adopted by the invention is as follows: a slope compensation circuit capable of eliminating the influence on the loading capacity of a current step-down transformer comprises a slope voltage generating circuit, a slope current generating circuit, a mirror current circuit and a sampling circuit;
the ramp current generating circuit comprises a second NMOS tube and a first resistor, the grid electrode of the second NMOS tube is connected with a voltage point A which is in ramp rising in the ramp voltage generating circuit, the source electrode of the second NMOS tube is connected with the first resistor, and the source electrode and the drain electrode of the second NMOS tube have first ramp rising current; the mirror current circuit is matched with the ramp current generating circuit to generate a second ramp rising current of a mirror image;
the sampling circuit comprises a transmission gate, a second capacitor, a third NMOS tube and a second resistor, wherein a voltage point A which is in slope rising is connected with the transmission gate and then connected with the second capacitor, the transmission gate is controlled by a control signal and a reverse signal, the control signal and the reverse signal sample/store the voltage point A through the transmission gate and the second capacitor, a node between the transmission gate and the second capacitor is connected with a grid electrode of the third NMOS tube, the second slope rising current and the slope compensation current are connected together and then connected to a drain electrode of the third NMOS tube, a source electrode of the third NMOS tube is connected with the second resistor, and the second resistor is matched with the first resistor, so that the current flowing through the third NMOS tube is a direct current component of the slope compensation current when a PWM comparator in a voltage reducer overturns.
Further, the ramp voltage generating circuit comprises a first NMOS tube, a fourth NMOS tube, a charging current and a first capacitor, wherein a source electrode of the first NMOS tube is grounded, a drain electrode of the first NMOS tube is connected with a source electrode of the fourth NMOS tube, the charging current is connected with the first capacitor and then grounded, a grid electrode of the first NMOS tube is connected to a voltage point A between the charging current and the first capacitor, the fourth NMOS tube is a switch tube, a grid electrode connection control signal Singal _2 of the fourth NMOS tube is used for switching off the fourth NMOS tube when the upper tube is opened every time, and the first capacitor is charged through the charging current.
Furthermore, the first NMOS tube, the second NMOS tube and the third NMOS tube have the same size, and the layouts are matched.
Furthermore, the mirror current circuit comprises a first PMOS tube and a second PMOS tube, wherein the source electrode of the first PMOS tube is connected with the charging current, the drain electrode and the grid electrode of the first PMOS tube are in short circuit and are respectively connected with the drain electrode of the second NMOS tube and the grid electrode of the second PMOS tube, the source electrode of the second PMOS tube is connected with the charging current, and the drain electrode of the second PMOS tube is connected with the drain electrode of the third NMOS tube.
Compared with the prior art, the beneficial effects of adopting the technical scheme are as follows: by adopting the technical scheme of the invention, the direct current component of the slope voltage is sampled, and the influence of the direct current component is eliminated in the final slope compensation current, so that the maximum load capacity of the buck converter is not influenced while the circuit is ensured not to generate subharmonic oscillation, and the load capacity of the converter is optimized.
Drawings
Fig. 1 is a schematic structural diagram of a slope compensation circuit capable of eliminating the influence on the loading capacity of a current step-down transformer according to the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
The slope compensation circuit capable of eliminating the influence on the loading capacity of the current step-down transformer, as shown in fig. 1, comprises a slope voltage generating circuit 1, a slope current generating circuit, a mirror current circuit 2 and a sampling circuit;
the ramp current generating circuit comprises a second NMOS transistor MN2 anda first resistor R1, the gate MN2 of the second NMOS transistor is connected to a voltage point A which is ramp-up in the ramp voltage generation circuit, the source MN2 of the second NMOS transistor is connected to the first resistor R1, and the source and the drain of the second NMOS transistor MN2 have a first ramp-up current I1(ii) a Because the voltage at the point B of the source of the second NMOS transistor MN2 rises along with the point A, the current I1＝VBthe/R1 also has a ramp-up, the mirror current circuit 2 cooperates with the ramp current generating circuit to generate a mirror current I2Also rises in a slope;
the sampling circuit comprises a transmission gate TG, a second capacitor C2, a third NMOS tube MN3 and a second resistor R2, a voltage point A which rises in a slope is connected with the transmission gate TG and then connected with the second capacitor C2, the transmission gate TG is controlled by a control Signal _1 and a reverse Signal _1 ', the control Signal _1 and the reverse Signal _ 1' sample/store the voltage point A through the transmission gate TG and the second capacitor C2, a node between the transmission gate TG and the second capacitor C2 is connected with a gate of the third NMOS tube MN3, and the second slope rising current I2And a slope compensation current IslopeThe NMOS transistors are connected together and then connected to the drain electrode of a third NMOS transistor MN3, the source electrode of the third NMOS transistor MN3 is connected with a second resistor R2, and the second resistor R2 is matched with the first resistor R1, so that the current I flowing through the third NMOS transistor MN33The DC component of the slope compensation current when the PWM comparator in the voltage reducer overturns. Slope compensation current IslopeThe current that eventually enters the PWM.
Because of Islope＝I3-I2，I2The current is a current rising in a slope, I3To fix the current, so the final generated slope compensation current IslopeAnd the current which is in ramp reduction is superposed with the output current of the error amplifier EA to complete the ramp compensation of the circuit. Meanwhile, because the gate terminal of the third NMOS transistor MN3 samples the dc component of the ramp voltage, I is sampled when the PWM comparator flipsslopeCurrent does not sample the inductor current IsenseThe maximum value of (a) has an effect and thus does not affect the load capacity of the converter. The above-described embodiment uses a structure in which a sample/hold is usedThe circuit (transmission gate TG and second capacitor C2) basically eliminates the influence on the maximum load capacity in the conventional slope compensation by sampling the dc component of the slope voltage and converting it into current.
As an embodiment of the invention, the ramp voltage generating circuit 1 comprises a first NMOS transistor MN1, a fourth NMOS transistor MN4, and a charging current I0And a first capacitor C1, the source of the first NMOS transistor MN1 is grounded, the drain of the first NMOS transistor MN1 is connected with the source of the fourth NMOS transistor MN4, and the charging current I0A first capacitor C1 is connected to ground, and the gate of the first NMOS transistor MN1 is connected to the charging current I0And a voltage point A of C1 between the first capacitor, the fourth NMOS tube MN4 is a switch tube, a gate connection control signal Singal _2 of the fourth NMOS tube MN4 is to turn off the fourth NMOS tube MN4 when the upper tube is turned on every time, and the charging current I is passed0To charge the first capacitor C1, the control signal single _2 delays the turn on of the fourth NMOS transistor MN4 for a short time after each turn off of the upper transistor, so that the first capacitor C1 is fully discharged until the next turn on of the upper transistor, and the next cycle starts.
As an embodiment of the present invention, the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor have the same size, and are layout-matched.
As an embodiment of the invention, the mirror current circuit 2 comprises a first PMOS transistor MP1 and a second PMOS transistor MP2, and the source of the first PMOS transistor MP1 is connected with the charging current I0The drain and the gate of the first PMOS transistor MP1 are shorted and connected to the drain of the second NMOS transistor MN2 and the gate of the second PMOS transistor MP2, respectively, and the source of the second PMOS transistor MP2 is connected to the charging current I0The drain of the second PMOS transistor MP2 is connected to the drain of the third NMOS transistor MN 3.
The invention is not limited to the foregoing embodiments. The invention extends to any novel feature or any novel combination of features disclosed in this specification and any novel method or process steps or any novel combination of features disclosed. Those skilled in the art to which the invention pertains will appreciate that insubstantial changes or modifications can be made without departing from the spirit of the invention as defined by the appended claims.

Claims (3)

1. A slope compensation circuit capable of eliminating the influence on the loading capacity of a current step-down transformer is characterized by comprising a slope voltage generating circuit, a slope current generating circuit, a mirror current circuit and a sampling circuit;
the ramp current generating circuit comprises a second NMOS tube and a first resistor, the grid electrode of the second NMOS tube is connected with a voltage point A which is in ramp rising in the ramp voltage generating circuit, the source electrode of the second NMOS tube is connected with the first resistor, and the source electrode and the drain electrode of the second NMOS tube have first ramp rising current; the mirror current circuit is matched with the ramp current generating circuit to generate a second ramp rising current of a mirror image;
the sampling circuit comprises a transmission gate, a second capacitor, a third NMOS tube and a second resistor, wherein a voltage point A which is in a slope rising state is connected with the transmission gate and then connected with the second capacitor, the transmission gate is controlled by a control signal and a reverse signal, the control signal and the reverse signal carry out sampling/storage operation on the voltage point A through the transmission gate and the second capacitor, a junction between the transmission gate and the second capacitor is connected with a grid electrode of the third NMOS tube, the second slope rising current and the slope compensation current are connected together and then connected to a drain electrode of the third NMOS tube, a source electrode of the third NMOS tube is connected with the second resistor, and the second resistor is matched with the first resistor, so that the current flowing through the third NMOS tube is a direct-current component of the slope compensation current when a PWM comparator in the voltage reducer is turned over;
the ramp voltage generating circuit comprises a first NMOS tube, a fourth NMOS tube, a charging current and a first capacitor, wherein a source electrode of the first NMOS tube is grounded, a drain electrode of the first NMOS tube is connected with a source electrode of the fourth NMOS tube, the charging current is connected with the first capacitor and then grounded, a grid electrode of the first NMOS tube is connected to a voltage point A between the charging current and the first capacitor, the fourth NMOS tube is a switching tube, a grid electrode connection control signal Singal _2 of the fourth NMOS tube is used for turning off the fourth NMOS tube when the upper tube is opened at every time, and the first capacitor is charged through the charging current.
2. The slope compensation circuit capable of eliminating the influence on the loading capacity of the current step-down transformer as claimed in claim 1, wherein the first NMOS transistor, the second NMOS transistor and the third NMOS transistor have the same size and are layout-matched.
3. The slope compensation circuit capable of eliminating the influence on the load capacity of the current step-down transformer as claimed in claim 2, wherein the mirror current circuit comprises a first PMOS transistor and a second PMOS transistor, the source electrode of the first PMOS transistor is connected with the charging current, the drain electrode and the gate electrode of the first PMOS transistor are shorted and respectively connected with the drain electrode of the second NMOS transistor and the gate electrode of the second PMOS transistor, the source electrode of the second PMOS transistor is connected with the charging current, and the drain electrode of the second PMOS transistor is connected with the drain electrode of the third NMOS transistor.
CN201910247031.XA 2019-03-29 2019-03-29 Slope compensation circuit capable of eliminating influence on loading capacity of current step-down transformer Active CN110022064B (en)

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CN114285251A (en) * 2021-12-24 2022-04-05 西安理工大学 Circuit for improving carrying capacity of switching power supply

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101674069A (en) * 2009-10-14 2010-03-17 美芯晟科技（北京）有限公司 Slope generating circuit
CN101674085A (en) * 2008-09-10 2010-03-17 中国科学院半导体研究所 Sampling hold circuit applied to analogue-to-digital converter
CN202435271U (en) * 2012-01-20 2012-09-12 彩优微电子(昆山)有限公司 Slope compensation circuit

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JP4902390B2 (en) * 2007-02-17 2012-03-21 セイコーインスツル株式会社 Current detection circuit and current mode switching regulator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101674085A (en) * 2008-09-10 2010-03-17 中国科学院半导体研究所 Sampling hold circuit applied to analogue-to-digital converter
CN101674069A (en) * 2009-10-14 2010-03-17 美芯晟科技（北京）有限公司 Slope generating circuit
CN202435271U (en) * 2012-01-20 2012-09-12 彩优微电子(昆山)有限公司 Slope compensation circuit

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