CN114726208B - PWM control circuit of peak current mode buck converter - Google Patents

PWM control circuit of peak current mode buck converter Download PDF

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Publication number
CN114726208B
CN114726208B CN202210489727.5A CN202210489727A CN114726208B CN 114726208 B CN114726208 B CN 114726208B CN 202210489727 A CN202210489727 A CN 202210489727A CN 114726208 B CN114726208 B CN 114726208B
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China
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power nmos
circuit
current
power
voltage
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CN114726208A (en
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周泽坤
吴徽
张志坚
彭栎郴
王卓
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a PWM control circuit of a peak current mode buck converter. Aiming at the problems that a traditional peak current mode circuit PWM control method needs a complex sampling circuit, a signal superposition circuit and an additional pin, the invention provides a PWM control method without a load sampling circuit and an additional pin.

Description

PWM control circuit of peak current mode buck converter
Technical Field
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a PWM control circuit of a peak current mode buck converter.
Background
In a general peak current mode DC-DC buck converter, inductance current information needs to be sampled, the obtained sampled voltage is used as an input signal of a PWM comparator in the system, and since the inductance of the converter is generally out of the chip, voltage information at two ends of the inductance needs to be obtained in the traditional sampling process, one end of the inductance is a switch node SW and can be directly cited in the chip, and the other end of the inductance is out of the chip, therefore, an additional pin is inevitably needed to transmit the voltage information at the other end of the inductance into the chip; in addition, for the peak current mode converter, in order to prevent the problem of subharmonic oscillation, the output signal of the operational voltage amplifier needs to be superimposed with the ramp compensation voltage and then compared with the sampling voltage, so as to generate signals of switching off the upper tube and switching on the lower tube, and therefore, a relatively complex voltage signal superimposing circuit is inevitably needed. Therefore, the conventional peak current mode PWM control method is not suitable for low power consumption and miniaturized applications.
Disclosure of Invention
Aiming at the problems that a complex sampling circuit, a signal superposition circuit and an additional pin are needed in the traditional peak current mode circuit PWM control method, the invention provides a PWM control circuit without a load sampling circuit and an additional pin.
The technical scheme of the invention is as follows:
a PWM control circuit of a peak current mode buck converter comprises a first power NMOS, a second power NMOS, a third power NMOS, an off-chip inductor, an off-chip capacitor, a load resistor, a first feedback resistor, a second feedback resistor, an operational amplifier, a voltage-to-current circuit, a current scaling circuit, a comparator, a logic control and driving circuit and a ramp compensation current source; the drain electrode of the first power NMOS is connected with a power supply voltage, the source electrode of the first power NMOS is connected with the drain electrode of the second power NMOS and one end of an off-chip inductor, and the grid electrode of the first power NMOS is connected with a high-side driving signal output by a logic control and driving circuit; the source electrode of the second power NMOS is grounded, and the grid electrode of the second power NMOS is connected with a low-side driving signal output by a logic control and driving circuit; the other end of the off-chip inductor is connected with one end of the off-chip capacitor and one end of the load resistor to serve as output ends, and the other end of the off-chip capacitor and the other end of the load resistor are grounded; the output end is grounded through the first feedback resistor and the second feedback resistor in sequence, and the joint of the first feedback resistor and the second feedback resistor is connected with one input end of the operational amplifier; the other input end of the operational amplifier is connected with a reference voltage, and the output end of the operational amplifier is connected with the input end of the voltage-to-current circuit; the output end of the voltage-to-current converter is connected with the input ends of the ramp compensation current source and the current scaling circuit; the output end of the current scaling circuit is connected with the source electrode of the third power NMOS tube and the negative input end of the comparator; the drain electrode of the third power NMOS tube is connected with a power supply, and the grid electrode of the third power NMOS tube is connected with the grid electrode of the first power NMOS tube; the positive input end of the comparator is connected with the connection point of the first power NMOS and the second power NMOS, and the output end of the comparator is connected with the input end of the logic control and driving circuit.
The beneficial effects of the invention are as follows: the output voltage of the operational amplifier is converted into current, and then the current is overlapped with the oblique wave compensation current, and the overlapped current passes through a sampling power tube which is proportional to the high-side power tube, and the source voltage of the sampling power tube is compared with the source voltage of the high-side power tube to generate a signal for controlling the high-side power tube to be closed.
Drawings
Fig. 1 is a schematic diagram of a PWM control circuit of a peak current mode buck converter according to the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings;
as shown in fig. 1, the first feedback resistor and the second feedback resistor divide the output voltage of the circuit to obtain feedback signals, and the feedback signals and the reference voltage are respectively used as two input ends of the operational voltage amplifier and generate output signals, and the output signals are equivalent to the peak value of the inductor current sampling voltage in the common peak current mode application. The current obtained by subtracting the current generated by the voltage-to-current circuit from the ramp compensation current flows through the third power NMOS after passing through the current scaling circuit, and a certain voltage drop is generated on the current, and at the moment, the source voltage of the third power transistor can be expressed as:
V S,M3 ＝V IN -mIR on,M3 (1)
the current I is the current after the output voltage of the operational amplifier passes through the voltage-to-current circuit and then is subtracted from the ramp compensation current. During switching, when the first power NMOS is turned on, an inductor current flows therein, and thus a voltage drop occurs, so that the source voltage of the first NMOS transistor, that is, the voltage at the positive input terminal of the comparator, can be expressed as:
V S,M1 ＝V IN -I H R on,M1 (2)
the voltage represented by the formula (2) is equivalent to a sampled voltage obtained by sampling the inductor current by using the on-resistance of the first power NMOS, and when the comparator is turned over, the source voltage of the third power NMOS is the same as the source voltage of the first power NMOS, so that the on-resistances of the two power NMOS are in a certain proportion at the moment when the comparator is turned over. Comparing the two voltages of the formula (1) and the formula (2) through the comparator, and when the comparator is turned from high level to low level, the high-side power tube is required to be turned off at the moment, so that the logic and the driving circuit can control the first power NMOS to be turned off and the second power NMOS to be turned on; the logic and driving circuit controls the first power NMOS to be turned on and the second power NMOS to be turned off until the clock signal CLK is turned from low level to high level, thereby realizing the control of the peak current mode. In addition, compared with a common sampling circuit for current passing through the replica power tube, the structure can omit a voltage clamping operational amplifier for clamping the drain terminal potential of the replica tube and the drain terminal potential of the power tube to the same potential, so that the chip area can be reduced.
Through the analysis of the PWM control method of the peak current mode buck converter, the invention has the advantages of no need of additional sampling pins, simple structure, no need of complex sampling circuits and voltage superposition circuits, and suitability for miniaturized and low-power consumption application.

Claims (1)

1. The PWM control circuit of the peak current mode buck converter is characterized by comprising a first power NMOS, a second power NMOS, a third power NMOS, an off-chip inductor, an off-chip capacitor, a load resistor, a first feedback resistor, a second feedback resistor, an operational amplifier, a voltage-to-current circuit, a current scaling circuit, a comparator, a logic control and drive circuit and a ramp compensation current source; the drain electrode of the first power NMOS is connected with a power supply voltage, the source electrode of the first power NMOS is connected with the drain electrode of the second power NMOS and one end of an off-chip inductor, and the grid electrode of the first power NMOS is connected with a high-side driving signal output by a logic control and driving circuit; the source electrode of the second power NMOS is grounded, and the grid electrode of the second power NMOS is connected with a low-side driving signal output by a logic control and driving circuit; the other end of the off-chip inductor is connected with one end of the off-chip capacitor and one end of the load resistor to serve as output ends, and the other end of the off-chip capacitor and the other end of the load resistor are grounded; the output end is grounded through the first feedback resistor and the second feedback resistor in sequence, and the joint of the first feedback resistor and the second feedback resistor is connected with one input end of the operational amplifier; the other input end of the operational amplifier is connected with a reference voltage, and the output end of the operational amplifier is connected with the input end of the voltage-to-current circuit; the output end of the voltage-to-current converter is connected with the input ends of the ramp compensation current source and the current scaling circuit; the output end of the current scaling circuit is connected with the source electrode of the third power NMOS tube and the negative input end of the comparator; the drain electrode of the third power NMOS tube is connected with a power supply, and the grid electrode of the third power NMOS tube is connected with the grid electrode of the first power NMOS tube; the positive input end of the comparator is connected with the connection point of the first power NMOS and the second power NMOS, and the output end of the comparator is connected with the input end of the logic control and driving circuit.
CN202210489727.5A 2022-05-07 2022-05-07 PWM control circuit of peak current mode buck converter Active CN114726208B (en)

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CN115882700B (en) * 2023-03-08 2023-04-28 合肥乘翎微电子有限公司 Control circuit of direct current-direct current converter with wide conversion ratio

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