CN202435271U - Slope compensation circuit - Google Patents

Abstract

A slope compensation circuit is used for a DC-DC switching power supply consisting of a power tube, which comprises a voltage generating circuit, a voltage control circuit and a current output circuit, wherein the voltage generating circuit is used for generating gradually boosting voltage; the voltage control circuit is connected with the voltage generating circuit and used for periodically controlling voltage generated by the voltage generating circuit according to a clock signal, and periodically releasing the voltage; and the current output circuit is connected with the voltage control circuit and used for receiving output voltage of the voltage control circuit, and the waveform of slope compensation current is sawtooth-shaped. After the slope compensation current is stacked with inductance current and sampling current of the switching power supply, subharmonic oscillation is well restrained, and besides, an existent over-compensation problem of other slope compensation methods is effectively avoided, so as to enable a switching power supply circuit to be more stable.

Description

Slope compensation circuit

Technical field

The utility model relates to a kind of Switching Power Supply, more particularly, relates to the slope compensation circuit that is applied in the Switching Power Supply.

Background technology

The main circuit of Switching Power Supply generally is made up of input EMI FILTER (EMI), current rectifying and wave filtering circuit, power conversion circuit, PWM controller circuitry, output rectifier and filter.Auxiliary circuit has input over under-voltage protection circuit, output over under-voltage protection circuit, output overcurrent protective circuit, output short circuit protection circuit etc.

In the control of DC-DC switch power supply stream mode, a shortcoming is all arranged, need add a little slope on the comparator slope, be called slope compensation.Slope compensation is in order to prevent the subharmonic instability of Controlled in Current Mode and Based.Unstable unobstructed wide switch pulse and the narrow switching pulse that alternately occurs that show as of subharmonic, the transient state respective capabilities acutely descends simultaneously.

Subharmonic (under the current-mode of DC-DC Switching Power Supply) is unsettled to have two conditions to satisfy simultaneously, one be the DC-DC Switching Power Supply duty ratio must near or greater than 50%, another is that converter is operated in CCM (continuous mode).Under current control mode control, when electric current reached a certain size, switch turn-offed.If duty ratio surpasses 50%, the rise time of inductive current, the time of electric current decline was just less than 50% of one-period so just greater than 50% of the whole cycle.In the short period of time, the electric current static initial value that also do not have enough time to get back to, next cycle and having begun.It is big that the initial current of next cycle becomes, and in ensuing one-period, inductive current rises to reference point soon; Be that ON time shortens; Duty ratio narrows down, and compares with last one-period, and the duty ratio in this cycle is reduced to below 50%; But so just cause the turn-off time oversize, the initial value of next cycle electric current is too little.Like this, just can cause the duty ratio of ensuing one-period to surpass 50% once more again.So circulation, electric current vibration occurs with the excessive and too small mode of interval one-period, i.e. and subharmonic oscillation frequency is 1/2 of a switching frequency.When duty ratio raises, just more need slope compensation.Usually when minimum input voltage, get rid of the unsettled possibility of subharmonic as possible.

In order to suppress the subharmonic oscillation problem in the DC-DC switch power supply stream mode, need carry out slope compensation.Commonly used is single slope compensation and segmentation slope compensation at present.Single slope compensation is in whole duty ratio interval, to compensate with a fixed slope, the overcompensation problem when there is little duty ratio in this mode.The segmentation slope compensation is that whole duty ratio interval is divided into several sections, and every section duty ratio compensates with a fixed ramp, the same overcompensation problem that has little duty ratio in the section.

The utility model content

The purpose of the utility model is to provide a kind of slope slope continually varying slope compensation mode that in whole duty ratio interval, compensates, and in the good restraining subharmonic oscillation, can effectively solve the overcompensation problem that other slope compensation modes exist.

For realizing above-mentioned purpose, the technical scheme of the utility model is following:

A kind of slope compensation circuit is used for the DC-DC Switching Power Supply, and this DC-DC Switching Power Supply comprises a power tube, and this slope compensation circuit comprises: voltage generation circuit is used to produce a voltage that rises gradually; Voltage control circuit is connected with voltage generation circuit, is used for the voltage according to the said voltage generation circuit generation of a clock signal period property ground gating, and periodically discharges this voltage; Current output circuit is connected with voltage control circuit, is used to accept the output voltage of said voltage control circuit and exports the slope compensation electric current, said slope compensation current waveform indention.

As a kind of preferred version of the above-mentioned slope compensation circuit of the utility model, voltage generation circuit comprises a current source and an electric capacity, and current source is used for electric capacity charging, with a hot end of this electric capacity output as this voltage generation circuit.

First execution mode as above-mentioned preferred version; Voltage control circuit comprises the second nmos fet N12; Its source electrode, drain electrode connect the two ends of this electric capacity respectively and as two outputs of this voltage control circuit; Its grid is accepted this clock signal, is used for the voltage signal that the gate voltage generative circuit produces.

Further improvement as above-mentioned first execution mode; Current output circuit comprises the first nmos fet N11; Its source electrode is connected with the source electrode of the second nmos fet N12 and ground connection; Its grid is connected with this second nmos fet N12 drain electrode, and its drain electrode is as output output slope compensation electric current.

Second execution mode as above-mentioned preferred version; Voltage control circuit comprises the second pmos fet P22; Its source electrode, drain electrode connect the two ends of this electric capacity respectively and as two outputs of this voltage control circuit; Its grid is accepted this clock signal, is used for the voltage signal that the gate voltage generative circuit produces.

Further improvement as above-mentioned second execution mode; Current output circuit comprises the first pmos fet P21; Its source electrode is connected with the source electrode of the second pmos fet P22 and is connected to an external voltage source; Its grid is connected with the drain electrode of this second pmos fet P22, and its drain electrode is as output output slope compensation electric current.

According to an aspect of the above-mentioned slope compensation circuit of the utility model, the clock signal that clock signal is obtained by the grid of the power tube of DC-DC Switching Power Supply connects an inverter and produces.

According to an aspect of the above-mentioned slope compensation circuit of the utility model, it also comprises a current mirroring circuit, and its control end connects the output of current output circuit, is used to duplicate the slope compensation electric current.

An aspect according to the above-mentioned slope compensation circuit of the utility model also is connected with a switch between the output of current mirroring circuit control end and current output circuit.

The slope compensation circuit that the utility model provides is exported a kind of slope compensation electric current, after the stack of the inductive current sample rate current of Switching Power Supply, has suppressed subharmonic oscillation well, has effectively avoided other slope compensation mode problem, the problem includes: the overcompensation problem simultaneously; Make switching power circuit more stable.

Description of drawings

Fig. 1 is the circuit diagram of first embodiment of the utility model;

Fig. 2 is the circuit diagram after first embodiment of the utility model further improves;

Fig. 3 is the circuit diagram of second embodiment of the utility model.

Embodiment

Below in conjunction with accompanying drawing, the embodiment of the utility model is done further to specify.

In order to suppress the subharmonic oscillation problem in the DC-DC switch power supply stream mode, need carry out slope compensation.Can know by the Ridley model,, must satisfy following relational expression in order to suppress the subharmonic oscillation problem in the current-mode:

$m_c=1+\frac{\mathrm{Se}}{\mathrm{Sn}}\≥\frac{0.82}{D^{\′}}$

In the following formula, Se is compensation slope slope, and Mc is the slope current penalty coefficient;

Wherein Sn is the inductive current rate of rise; In the boost framework,

In the following formula, V _iBe the input voltage of DC-DC Switching Power Supply, Vo is the output voltage of DC-DC Switching Power Supply; D '=1-D, wherein D is the duty ratio of clock signal clk, L is the inductance value in the boost framework.

Can draw by above-mentioned various derivation:

$\mathrm{Se}\≥\frac{\mathrm{Vo}}{L}\·(D-0.18)$

Minimum compensation slope current changes with DC-DC switch power supply power tube opening time t in the one-period, t=DTs wherein, and Ts is DC-DC Switching Power Supply time work period, minimum compensation slope current varying type is:

$\mathrm{Islope}=\frac{1}{2}\·\frac{\mathrm{Vo}\·\mathrm{Ts}}{L}\·{(D-0.18)}^2---\left(1.1\right)$

Fig. 1 illustrates a kind of slope slope continually varying slope compensation circuit that in whole duty ratio interval, compensates according to first embodiment of the utility model, is used for the DC-DC Switching Power Supply.Particularly, this slope compensation circuit comprises 4 parts: voltage generation circuit, voltage control circuit, slope compensation circuit, current mirroring circuit.According to the common practise of this area, the DC-DC Switching Power Supply must include a power tube.Need to prove that current mirroring circuit is not the necessary component of slope compensation circuit, its only be for replica current to be used for other circuit.In the embodiment of the utility model, introducing current mirroring circuit is not the scope in order to restriction the utility model yet.

Voltage generation circuit is used to produce a voltage that rises gradually, and preferably, voltage generation circuit can be that a current source I is connected with a capacitor C, the circuit that capacitor C is charged; Less preferred ground; It also can be a triangle wave generating circuit; According to the common practise of this area, triangle wave generating circuit can specifically be made up of hysteresis loop comparator and integrating circuit, and the output of hysteresis loop comparator and integrating circuit is the input of another circuit each other; Hysteresis loop comparator is output as square wave, behind the integral operation circuit, is transformed to triangular wave.

Voltage control circuit is used to control the voltage that voltage generation circuit produces, and said voltage is put in the subsequent conditioning circuit with the form of expection, promptly plays the function of a screening voltage.Voltage control circuit comprises a clock signal clk and the second nmos fet N12, and the CLK signal is input to the grid of the second nmos fet N12.Preferably, slope compensation circuit also comprises an inverter, and the clock signal that clock signal clk is obtained by the grid of the power tube of DC-DC Switching Power Supply inputs to this inverter and produces; The voltage that the gate voltage generative circuit was produced when CLK was high level ends during low level, and its duty ratio is D; Be that pulse voltage is that to account for the ratio of pulse period the low level duration be D; 0＜D＜1, in the utility model, D can change in span continuously.

In the current output circuit, input be the output voltage of voltage control circuit, output be the electric current of waveform indentation, this moment electric current in eliminated subharmonic oscillation, do not have problems such as overcompensation yet.Current output circuit specifically is made up of the first nmos fet N11.Obviously, the grid source of the first nmos fet N11 asks that voltage is voltage between the drain-source of the second nmos fet N12, also equals the voltage at capacitor C two ends.

Current mirroring circuit is input as the electric current of above-mentioned current output circuit output, and output current can be used as the current source of other circuit, and preferably, this circuit can be that the form with current mirror is amplified to required multiple to electric current, to supply with circuit; Current mirroring circuit can be made up of the 3rd, the 4th pmos fet P11, P12; Particularly; Three, the 4th pmos fet P11, P12 grid link together and are connected to the drain electrode of the 3rd pmos fet P11; Their source electrode is connected with external voltage source U respectively; The drain electrode of the 3rd pmos fet P11 is connected with the current output circuit output, the electric current after the drain electrode output of the 4th pmos fet P12 is duplicated.External voltage source U can be two, and the source electrode of the 3rd, the 4th pmos fet P11, P12 connects one separately; External voltage source U also can be one, and the source electrode of the 3rd, the 4th pmos fet P11, P12 connects jointly.

Wherein the first nmos fet N11 is long raceway groove nmos fet, is operated in the saturation region; Three, the 4th pmos fet P11 and P12 constitute the 1:1 current mirror; The electric current that duplicates among the first nmos fet N11 forms slope compensation electric current I slope1; Islope1 is the electric current between the source-drain electrode of the 4th pmos fet P12; Proportionate relationship by said current mirror can be known Islope1=In.Wherein In is the electric current that first nmos fet N11 drain electrode flows to source electrode; I is a current source; C is an electric capacity.

Above-mentioned first embodiment according to the utility model; The second nmos fet N12 is as nmos switch; Its Gate end (grid) is applied with a clock signal clk; The clock signal that the grid of the power tube that this signal CLK and this DC-DC Switching Power Supply comprise obtains is just in time opposite, makes this circuit can Cycle by Cycle work.When clock signal clk is low level, 0V for example, the grid source of the first nmos fet N11 asks that voltage is less than turn-on threshold voltage V _TSo the second nmos fet N12 is in cut-off state, current source I begins to charge for said capacitor C then, and the voltage at capacitor C two ends begins to raise; Because the voltage between the grid source of the first nmos fet N11 is the voltage at capacitor C two ends; When gate source voltage is elevated to when just equaling cut-in voltage VT, 0.7V for example, the first nmos fet N11 promptly gets into conducting state; When said clock signal clk is high level, 5V for example, voltage is greater than turn-on threshold voltage V between the grid source of the second nmos fet N12 _T, the second nmos fet N12 is in saturation condition immediately, and the voltage between the drain-source is almost nil, and said capacitor C is discharged rapidly, and the first nmos fet N11 also ends simultaneously.

In effective time in a work period, the electric current of the first nmos fet N11 (flowing to source electrode by drain electrode) is expressed as:

$\mathrm{In}=\frac{1}{2}\·u\·\mathrm{Cox}\·\frac{W}{\mathrm{Le}}\·{(V_{\mathrm{GS}}-V_T)}^2$

$=\frac{1}{2}\·u\·\mathrm{Cox}\·\frac{W}{\mathrm{Le}}\·{(\frac{I\·D\·\mathrm{Ts}}{C}-V_T)}^2$

$=\frac{1}{2}\·u\·\mathrm{Cox}\·\frac{W}{\mathrm{Le}}\·{\left(\frac{I\·\mathrm{Ts}}{C}\right)}^2\·{(D-\frac{V_T\·C}{I\·\mathrm{Ts}})}^2$

In the following formula, u is the carrier mobility of the first nmos fet N11, and Cox is the grid oxygen electric capacity of the first nmos fet N11 unit are, V _TBe the first nmos fet N11 turn-on threshold voltage, W/Le is the breadth length ratio of the first nmos fet N11;

Particularly, through fine setting V _T, parameter such as C and Ts, following relational expression is met:

That is: $\frac{I\·\mathrm{Ts}}{C}=\frac{V_T}{0.18}---\left(1.2\right)$

Order: $\frac{1}{2}\·u\·\mathrm{Cox}\·\frac{W}{\mathrm{Le}}\·{\left(\frac{I\·\mathrm{Ts}}{C}\right)}^2=\frac{1}{2}\·\frac{\mathrm{Vo}\·\mathrm{Ts}}{L},$ Then obtain the breadth length ratio of N1:

$\frac{W}{\mathrm{Le}}=\frac{\mathrm{Vo}\·\mathrm{Ts}}{L}\·{\left(\frac{C}{I\·\mathrm{Ts}}\right)}^2\·\frac{1}{u\·\mathrm{Cox}}=\frac{\mathrm{Vo}\·\mathrm{Ts}}{L}\·{\left(\frac{0.18}{V_T}\right)}^2\·\frac{1}{u\·\mathrm{Cox}}---\left(1.3\right)$

Can confirm the ratio of I and C among Fig. 1 by formula 1.2, after selected one of them value, then another value also can be confirmed.

Can confirm the breadth length ratio of the first nmos fet N11 among the figure one by formula 1.3.

The electric current I n that satisfies the field-effect transistor N11 of 1.2 formulas and 1.3 formulas can well realize the slope compensation electric current that formula 1.1 is confirmed.The slope of electric current I n changes with clock signal clk duty ratio D continuously, when suppressing subharmonic oscillation, also avoided other compensation way problem the problem includes: little duty ratio the time the overcompensation problem.

Fig. 2 is the circuit after the further improvement of Fig. 1, on the basis of Fig. 1, increases switch S 1, can control the slope compensation electric current and begin acting time point, the same Fig. 1 of other operation principles.

Fig. 3 is the employing pmos fet generation slope compensation electric current according to second embodiment of the utility model, the circuit diagram that nmos fet amplifies the slope compensation electric current as current mirror.This slope compensation circuit comprises 4 parts: voltage generation circuit, voltage control circuit, slope compensation circuit, current mirroring circuit.

Particularly, voltage generation circuit can be that a current source I is connected with a capacitor C, the circuit that capacitor C is charged; Less preferred ground also can be a triangle wave generating circuit.Voltage control circuit comprises the second pmos fet P22; Its source electrode, drain electrode connect the two ends of capacitor C respectively and as two outputs of this voltage control circuit; Its grid is accepted a clock signal clk, is used for the voltage signal that the gate voltage generative circuit produces.Current output circuit is the first pmos fet P21; Its source electrode is connected with the source electrode of the second pmos fet P22 and is connected to an external voltage source U; Its grid is connected with the drain electrode of this second pmos fet P22, and the electric current of having eliminated subharmonic oscillation is exported in its drain electrode as output.Current mirroring circuit is made up of the 3rd, the 4th nmos fet N21, N22; Three, the grid of the 4th nmos fet N21, N22 links together and is connected to the drain electrode of the 3rd nmos fet N21; Three, the 4th nmos fet N21, N22 source grounding; The drain electrode of the 3rd nmos fet N21 is connected with the current output circuit output, the electric current after the drain electrode output of the 4th nmos fet N22 is duplicated.

The above-described preferred embodiment that is merely the utility model; Said embodiment is not the scope of patent protection in order to restriction the utility model; Therefore specification of every utilization the utility model and equivalent structure that the accompanying drawing content is done change, and in like manner all should be included in the protection range of the utility model.

Claims (12)

1. a slope compensation circuit is used for the DC-DC Switching Power Supply, and this DC-DC Switching Power Supply comprises a power tube, and said slope compensation circuit comprises:

Voltage generation circuit is used to produce a voltage that rises gradually;

Voltage control circuit is connected with said voltage generation circuit, is used for the voltage according to the said voltage generation circuit generation of a clock signal period property ground gating, and periodically discharges this voltage;

Current output circuit is connected with said voltage control circuit, is used to accept the output voltage of said voltage control circuit and exports the slope compensation electric current, said slope compensation current waveform indention.

2. slope compensation circuit as claimed in claim 1 is characterized in that, said voltage generation circuit comprises a current source and an electric capacity, and said current source is used for electric capacity charging, with a hot end of this electric capacity output as this voltage generation circuit.

3. slope compensation circuit as claimed in claim 1 is characterized in that, said voltage generation circuit is a triangle wave generating circuit.

4. slope compensation circuit as claimed in claim 2; It is characterized in that; Said voltage control circuit comprises second nmos fet (N12); Its source electrode, drain electrode connect the two ends of said electric capacity respectively and as two outputs of this voltage control circuit, its grid is accepted said clock signal, is used for the voltage signal that the said voltage generation circuit of gating produces.

5. slope compensation circuit as claimed in claim 2; It is characterized in that; Said voltage control circuit comprises second pmos fet (P22); Its source electrode, drain electrode connect the two ends of said electric capacity respectively and as two outputs of this voltage control circuit, its grid is accepted said clock signal, is used for the voltage signal that the said voltage generation circuit of gating produces.

6. slope compensation circuit as claimed in claim 4; It is characterized in that; Said current output circuit comprises first nmos fet (N11); Its source electrode is connected with the source electrode of said second nmos fet (N12) and ground connection, and its grid is connected with this second nmos fet (N12) drain electrode, and its drain electrode is exported said slope compensation electric current as output.

7. slope compensation circuit as claimed in claim 5; It is characterized in that; Said current output circuit comprises first pmos fet (P21); Its source electrode is connected with the source electrode of said second pmos fet (P22) and is connected to an external voltage source, and its grid is connected with the drain electrode of this second pmos fet (P22), and its drain electrode is exported said slope compensation electric current as output.

8. like each described slope compensation circuit in the claim 4 to 7; It is characterized in that; Said slope compensation circuit also comprises an inverter, and the clock signal that said clock signal is obtained by the grid of the power tube of said DC-DC Switching Power Supply inputs to this inverter and produces.

9. like each described slope compensation circuit in the claim 1 to 7, it is characterized in that it also comprises a current mirroring circuit, its control end connects the output of said current output circuit, is used to duplicate said slope compensation electric current.

10. slope compensation circuit as claimed in claim 9 is characterized in that, between the output of said current mirroring circuit control end and said current output circuit, also is connected with a switch.

11. slope compensation circuit as claimed in claim 9; It is characterized in that; Said current mirroring circuit is made up of the 3rd, the 4th pmos fet (P11, P12); Three, the grid of the 4th pmos fet (P11, P12) links together and is connected to the drain electrode of the 3rd pmos fet (P11); Three, the 4th pmos fet (P11, P12) source electrode is connected with the external voltage source respectively, and the drain electrode of the 3rd pmos fet (P11) is connected with said current output circuit output, the electric current after the drain electrode output of the 4th pmos fet (P12) is duplicated.

12. slope compensation circuit as claimed in claim 9; It is characterized in that; Said current mirroring circuit is made up of the 3rd, the 4th nmos fet (N21, N22); Three, the grid of the 4th nmos fet (N21, N22) links together and is connected to the drain electrode of the 3rd nmos fet (N21); Three, the 4th nmos fet (N21, N22) source grounding, the drain electrode of the 3rd nmos fet (N21) is connected with said current output circuit output, the electric current after the drain electrode output of the 4th nmos fet (N22) is duplicated.

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