CN101667535A - Glass passivating method of silicon planar semiconductor device - Google Patents
Glass passivating method of silicon planar semiconductor device Download PDFInfo
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- CN101667535A CN101667535A CN200910182406A CN200910182406A CN101667535A CN 101667535 A CN101667535 A CN 101667535A CN 200910182406 A CN200910182406 A CN 200910182406A CN 200910182406 A CN200910182406 A CN 200910182406A CN 101667535 A CN101667535 A CN 101667535A
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Abstract
The invention discloses a glass passivating method of silicon planar semiconductor device, relating to a glass passivating process of silicon planar semiconductor device, in particular to a surface PNjunction glass passivating process of silicon planar semiconductor device. The method comprises the following steps: mixing glass powder and photoresist, and the coating the mixture to the surface ofeach chip of a silicon slice, utilizing a photoetching method to remove the unnecessary glass powder and photoresist, removing the photoresist left on the surface of the silicon slice by degumming, leaving the glass powder at the position of PN junction, and sintering at the high temperature so as to form a glass passivating protective film. Common production equipment of a table-board semiconductor device can be completely adopted as equipment used in the production process procedure, thereby saving the investment of expensive CVD special equipment and reducing the production cost; the process is simple to operate, is easy to implement and realizes the surface PN junction protection of the planar semiconductor device.
Description
Technical field
The present invention relates to a kind of surperficial PN junction glassivation technology of glassivation technology, particularly silicon planar semiconductor device of semiconductor device.
Background technology
The surface passivation technology of current silicon planar semiconductor device is to adopt at silicon chip surface chemical vapor deposition polysilicon SIPOS film or mix the silicon dioxide-PSG film of phosphorus.Its technological principle is: utilize chemically inactive gas (H
2, N
2, Ar etc.) carry reaction source gas (phosphine, silane) and enter reative cell in the mode of laminar flow, arrive the substrate that is heated to reaction temperature in advance.In the laminar flow layer above substrate, the reaction source molecule in the carrier gas passes retention layer, decomposes and diffuses to plane of crystal, through physics and chemical process, controllably is deposited on the substrate, forms the illuvium that needs.This technology depends on expensive chemical vapor deposition consersion unit, so the production cost height.For a long time, in field of manufacturing semiconductor devices, people constantly carry out technology and create into, make every effort to reduce production costs, and improve cost performance of product.
Summary of the invention
The purpose of this invention is to provide a kind of process that replaces traditional SIPOS or psg film that planar semiconductor device is carried out surperficial PN junction protection with the glassivation film, to reduce production costs.
Technical solution of the present invention is: the mixed liquor of photoresist and glass dust evenly is coated in has finished the surface that diffusing procedure is treated the silicon chip of surface passivation, place and carry out preceding baking in the baking oven; Send into exposure in the exposure machine then, develop again, remove unnecessary photoresist and glass dust; With the slide glass boat of packing into of the silicon chip after developing, push diffusion furnace and remove photoresist; Again silicon chip is loaded onto the slide glass boat, pushed diffusion furnace, be warming up to 820 ℃, at O
2Sintering after 20 minutes is pulled out the slide glass boat in the atmosphere, takes off silicon chip.
After mixing glass dust and photoresist, the present invention is coated in each chip surface of silicon chip; utilize the method for photoetching to remove unnecessary glass dust and photoresist; again through removing photoresist; the photoresist of staying silicon chip surface is removed; stay glass dust at the PN junction position, and at high temperature sintering to form the glass passivation protection film.
The used equipment of production process of the present invention can adopt the production equipment of common mesa semiconductor devices fully; saved the investment of expensive CVD special equipment, reduced production cost, technological operation is simple; easy to implement, realized surperficial PN junction protection to planar semiconductor device.The invention of this technology has broken through traditional theory, has realized also producing without chemical gas-phase deposition method the dream of planar semiconductor device.
Photoresist and glass dust mass percent are respectively 40%～60%, 40%～60% in the mixed liquor of the present invention.The proper mixture ratio purpose is to guarantee that the mixed liquor that is coated in silicon chip surface has certain viscosity, so that operation, and guarantee to apply evenly, reach the purpose of passivation protection.
In order to improve the quality of products, the present invention also before described coating, carries out chemical cleaning and drying with described silicon chip.
Description of drawings
Fig. 1 is capped chip structure schematic diagram after the mixed liquor for diffusion sheet of the present invention.
Fig. 2 is the chip structure signal of the present invention after finishing.
In the accompanying drawing, 1 is the glass passivation protection film, and 2 are the SiO of diffusion back in silicon chip surface formation
2, 3 is the overlay of photoresist and glass dust mixed liquor.
Embodiment
Photoresist and glass dust is even according to the mixed with 4: 6 or 6: 4, make mixed liquor, stand-by.
Get and finished the silicon chip that diffusing procedure is treated surface passivation, carry out strict chemical cleaning and drying, the mixed liquor of the photoresist of preparation and glass dust evenly is coated in the surface (as Fig. 1) of silicon chip 2, and the horse of packing into, put into baking oven, under 150 ± 5 ℃ of temperature conditions, carry out preceding baking, send into exposure in the exposure machine then, develop again to remove unnecessary photoresist and glass dust.With the silicon chip that the showed shadow slide glass boat of packing into, push diffusion furnace, remove photoresist, again silicon chip is loaded onto the slide glass boat, push diffusion furnace, be warming up to 820 ℃, at O
2Sintering is 20 minutes in the atmosphere, after the end slide glass boat is pulled out, and takes off silicon chip, has just covered one deck glass passivation protection film 1 (see figure 2) like this at the PN junction place of silicon chip surface.
Claims (3)
1, the glass passivating method of silicon planar semiconductor device is characterized in that mixed liquor with photoresist and glass dust evenly is coated in to have finished the surface that diffusing procedure is treated the silicon chip of surface passivation, places and carries out preceding baking in the baking oven; Send into exposure in the exposure machine then, develop again, remove unnecessary photoresist and glass dust; With the slide glass boat of packing into of the silicon chip after developing, push diffusion furnace and remove photoresist; Again silicon chip is loaded onto the slide glass boat, pushed diffusion furnace, be warming up to 820 ℃, at O
2Sintering after 20 minutes is pulled out the slide glass boat in the atmosphere, takes off silicon chip.
2,, it is characterized in that photoresist and glass dust mass percent are respectively 40%～60%, 40%～60% in the described mixed liquor according to the glass passivating method of the described silicon planar semiconductor device of claim 1.
3, according to the glass passivating method of the described silicon planar semiconductor device of claim 1, it is characterized in that before described coating, described silicon chip is carried out chemical cleaning and drying.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101824065A CN101667535B (en) | 2009-09-14 | 2009-09-14 | Glass passivating method of silicon planar semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101824065A CN101667535B (en) | 2009-09-14 | 2009-09-14 | Glass passivating method of silicon planar semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101667535A true CN101667535A (en) | 2010-03-10 |
| CN101667535B CN101667535B (en) | 2011-06-08 |
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ID=41804093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101824065A Active CN101667535B (en) | 2009-09-14 | 2009-09-14 | Glass passivating method of silicon planar semiconductor device |
Country Status (1)
| Country | Link |
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| CN (1) | CN101667535B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465330A (en) * | 2014-12-25 | 2015-03-25 | 安徽安芯电子科技有限公司 | Rectifier diode, chip and manufacturing method thereof |
| CN110544659A (en) * | 2019-10-08 | 2019-12-06 | 江苏晟驰微电子有限公司 | novel quartz boat of glass passivation |
-
2009
- 2009-09-14 CN CN2009101824065A patent/CN101667535B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465330A (en) * | 2014-12-25 | 2015-03-25 | 安徽安芯电子科技有限公司 | Rectifier diode, chip and manufacturing method thereof |
| CN104465330B (en) * | 2014-12-25 | 2018-09-28 | 安徽安芯电子科技股份有限公司 | Rectifier diode, chip and preparation method thereof |
| CN110544659A (en) * | 2019-10-08 | 2019-12-06 | 江苏晟驰微电子有限公司 | novel quartz boat of glass passivation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101667535B (en) | 2011-06-08 |
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Address after: 226600, Jiangsu province Nantong city Haian county old dam Town Industrial Park Patentee after: Jiangsu Ming core microelectronic Limited by Share Ltd Address before: 226600 Jiangsu province Haian county old dam Port Industrial Park Patentee before: Nantong Mingxin Microelectronics Co., Ltd. |
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