CN101656096B - 已注册dimm存储器系统 - Google Patents
已注册dimm存储器系统 Download PDFInfo
- Publication number
- CN101656096B CN101656096B CN200910161562.3A CN200910161562A CN101656096B CN 101656096 B CN101656096 B CN 101656096B CN 200910161562 A CN200910161562 A CN 200910161562A CN 101656096 B CN101656096 B CN 101656096B
- Authority
- CN
- China
- Prior art keywords
- data bus
- control signal
- buffer
- switch
- memory chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000872 buffer Substances 0.000 claims description 156
- 230000003139 buffering effect Effects 0.000 claims description 17
- 238000003491 array Methods 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims description 6
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- 230000009977 dual effect Effects 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 230000006835 compression Effects 0.000 claims description 3
- 238000007906 compression Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 4
- 230000005039 memory span Effects 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
Abstract
Description
Claims (14)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US4122308P | 2008-03-31 | 2008-03-31 | |
US12/185,239 US8654556B2 (en) | 2008-03-31 | 2008-08-04 | Registered DIMM memory system |
US12/185,239 | 2008-08-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101656096A CN101656096A (zh) | 2010-02-24 |
CN101656096B true CN101656096B (zh) | 2014-10-29 |
Family
ID=41118870
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200910161562.3A Active CN101656096B (zh) | 2008-03-31 | 2009-08-04 | 已注册dimm存储器系统 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8654556B2 (zh) |
CN (1) | CN101656096B (zh) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8516185B2 (en) | 2009-07-16 | 2013-08-20 | Netlist, Inc. | System and method utilizing distributed byte-wise buffers on a memory module |
US8154901B1 (en) | 2008-04-14 | 2012-04-10 | Netlist, Inc. | Circuit providing load isolation and noise reduction |
JP2010218641A (ja) * | 2009-03-18 | 2010-09-30 | Elpida Memory Inc | メモリモジュール |
JP2010282510A (ja) * | 2009-06-05 | 2010-12-16 | Elpida Memory Inc | メモリモジュール |
US9128632B2 (en) | 2009-07-16 | 2015-09-08 | Netlist, Inc. | Memory module with distributed data buffers and method of operation |
JP5314612B2 (ja) * | 2010-02-04 | 2013-10-16 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
WO2012061633A2 (en) | 2010-11-03 | 2012-05-10 | Netlist, Inc. | Method and apparatus for optimizing driver load in a memory package |
US10324841B2 (en) | 2013-07-27 | 2019-06-18 | Netlist, Inc. | Memory module with local synchronization |
US10521387B2 (en) * | 2014-02-07 | 2019-12-31 | Toshiba Memory Corporation | NAND switch |
US9892770B2 (en) * | 2015-04-22 | 2018-02-13 | Micron Technology, Inc. | Methods and apparatuses for command shifter reduction |
US20160350002A1 (en) * | 2015-05-29 | 2016-12-01 | Intel Corporation | Memory device specific self refresh entry and exit |
WO2017018991A1 (en) * | 2015-07-24 | 2017-02-02 | Hewlett Packard Enterprise Development Lp | Modification of a bus channel |
US20170083461A1 (en) * | 2015-09-22 | 2017-03-23 | Qualcomm Incorporated | Integrated circuit with low latency and high density routing between a memory controller digital core and i/os |
US9811266B1 (en) | 2016-09-22 | 2017-11-07 | Cisco Technology, Inc. | Data buffer for multiple DIMM topology |
CN113767435A (zh) * | 2019-02-22 | 2021-12-07 | 美光科技公司 | 存储器装置接口及方法 |
CN111045955B (zh) * | 2019-12-16 | 2023-09-22 | 瓴盛科技有限公司 | 架构动态配置的存储装置及其操作方法及电子设备 |
KR20220119697A (ko) | 2019-12-27 | 2022-08-30 | 마이크론 테크놀로지, 인크. | 뉴로모픽 메모리 장치 및 방법 |
WO2021138329A1 (en) | 2019-12-30 | 2021-07-08 | Micron Technology, Inc. | Memory device interface and method |
US11538508B2 (en) | 2019-12-31 | 2022-12-27 | Micron Technology, Inc. | Memory module multiple port buffer techniques |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6502161B1 (en) * | 2000-01-05 | 2002-12-31 | Rambus Inc. | Memory system including a point-to-point linked memory subsystem |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030090879A1 (en) * | 2001-06-14 | 2003-05-15 | Doblar Drew G. | Dual inline memory module |
US7174495B2 (en) | 2003-12-19 | 2007-02-06 | Emmanuel Boutillon | LDPC decoder, corresponding method, system and computer program |
US7464225B2 (en) * | 2005-09-26 | 2008-12-09 | Rambus Inc. | Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology |
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2008
- 2008-08-04 US US12/185,239 patent/US8654556B2/en active Active
-
2009
- 2009-08-04 CN CN200910161562.3A patent/CN101656096B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6502161B1 (en) * | 2000-01-05 | 2002-12-31 | Rambus Inc. | Memory system including a point-to-point linked memory subsystem |
Also Published As
Publication number | Publication date |
---|---|
US20090248969A1 (en) | 2009-10-01 |
CN101656096A (zh) | 2010-02-24 |
US8654556B2 (en) | 2014-02-18 |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: MONTAGE SEMICONDUCTOR (SHANGHAI) CO., LTD. Free format text: FORMER OWNER: MONTAGE TECHNOLOGY GROUP LTD. Effective date: 20110322 |
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C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 200233 ROOM 406, VENTURE CENTER BUILDING, NO. 680, GUIPING ROAD, SHANGHAI TO: 200233 ROOM 802 + 803 + 805 + 807 + 809, BUILDING 33, NO. 680, GUIPING ROAD, SHANGHAI, CHINA |
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TA01 | Transfer of patent application right |
Effective date of registration: 20110322 Address after: 200233, No. 680, Guiping Road, 33, 802, 803, 805, 807, 809, Shanghai, China Applicant after: Lanqi Semiconductor Shanghai Co.,Ltd. Address before: 200233, room 406, Pioneer Building, No. 680, Guiping Road, Shanghai Applicant before: Acrospeed, Inc. |
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Owner name: MONTAGE TECHNOLOGY GROUP LTD. Free format text: FORMER OWNER: MONTAGE SEMICONDUCTOR (SHANGHAI) CO., LTD. Effective date: 20130313 |
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C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20130313 Address after: 200233 room 406A, building 32, No. 680 Guiping Road, Shanghai, Xuhui District, China Applicant after: Acrospeed, Inc. Address before: 200233, No. 680, Guiping Road, 33, 802, 803, 805, 807, 809, Shanghai Applicant before: Lanqi Semiconductor Shanghai Co.,Ltd. |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP03 | Change of name, title or address |
Address after: A6, No. 900 Yishan Road, Xuhui District, Shanghai, 2003 Patentee after: Lanqi Technology Co., Ltd. Address before: Room 406A, 4th floor, 32 Guiping Road, Xuhui District, Shanghai Patentee before: Acrospeed, Inc. |
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CP03 | Change of name, title or address |