CN101645767A - K interface error code testing method and system thereof - Google Patents
K interface error code testing method and system thereof Download PDFInfo
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- CN101645767A CN101645767A CN200910184522A CN200910184522A CN101645767A CN 101645767 A CN101645767 A CN 101645767A CN 200910184522 A CN200910184522 A CN 200910184522A CN 200910184522 A CN200910184522 A CN 200910184522A CN 101645767 A CN101645767 A CN 101645767A
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Abstract
The invention discloses a K interface error code testing method and a system thereof; the system is composed of an interface unit, a transmitting unit, a receiving unit, a clock unit, a control unit and a human-computer interface; the human-computer interface is connected with the control unit which is respectively connected with the transmitting unit, the clock unit, the receiving unit and the interface unit; the transmitting unit is connected with the interface unit which is respectively connected with the receiving unit and the clock unit; a clock signal is output by the clock unit by parameter setting of the human-computer interface under the control of the control unit, the transmitting unit generates test data which is converted through the interface unit and is output in a driving way, the input tested data is input to the receiving unit to carry out error code counting after being received and converted by the interface unit, finally, the data is processed by the control unit for displaying, so as to carry out K interface error code testing. The invention does not need conversion equipment and can accurately and directly realize K interface error code testing; the method can be used as the standard of the K interface error code testing.
Description
Technical field
The invention belongs to K interface testing technology, particularly a kind of K interface error code testing method and system thereof.
Background technology
The K interface is the wired population of a kind of single channel, is user terminal interface in the communication network, uses extensively.The error code testing of K interface never has tester, can adopt indirect method of measurement at present, promptly utilizes interface conversion equipment, is the K interface conversion RS232 interface, measures with the data code error tester of band RS232 interface then.Interface conversion equipment is at the communication objective design that realizes the remote point-to-point in RS232 interface termination, therefore, adopt this method of testing to have very big defective, at first be to be used for communication objective equipment to use as test, a lot of unaccommodated aspects are arranged, system clock as test is not the clock of Error Detector, and the function of test is limited by the function of conversion equipment, and test interface can not truly reflect the performance of K mouth etc.; The 2nd, this method of testing is lack of standardization, can't be as examination criteria; The 3rd, this test operation is loaded down with trivial details, use is very inconvenient.
Summary of the invention
The object of the present invention is to provide a kind of method and system thereof that can accurately, directly carry out error code testing to the K interface.
The technical solution that realizes the object of the invention is: a kind of K interface error code test macro, by interface unit, transmitting element, receiving element, clock unit, control unit and man-machine interface are formed, man-machine interface connects control unit, control unit connects transmitting element respectively, clock unit, receiving element and interface unit, this transmitting element connecting interface unit, interface unit connects receiving element and clock unit respectively, parameter setting by man-machine interface, under the control of control unit, by the clock unit clock signal, transmitting element produces test data, through the interface unit conversion, drive output, the measured data of importing is received through interface unit, after the conversion, the input receiving element carries out the error code counting,, finish the measurement of error code of K interface after control unit send demonstration after handling.
A kind of method of testing that realizes by above-mentioned K interface error code test macro, step is as follows:
(1) by the setup menu and the keyboard to set up test parameter of man-machine interface, comprises mode of operation, transmission rate, resolution chart, the insertion error rate;
(2) control unit is controlled each unit according to the test parameter that is provided with, and links to each other with clock unit, transmitting element, receiving element by data/address bus, links to each other with interface unit by control circuit;
(3) according to the transmission rate that is provided with, control unit is provided with the clock frequency that clock unit produces by data/address bus, clock unit produces 2048kHz or 8192kHz clock signal, when transmission rate is set to 16kbit/s, 32kbit/s, clock unit produces the 2048kHz clock signal, and when transmission rate was set to 64kbit/s, 128kbit/s, clock unit produced the 8192kHz clock signal, the clock signal that produces is sent into interface unit, as the system clock of interface unit;
(4) according to the resolution chart that is provided with, insert the error rate, control unit is provided with the circuit of transmitting element by data/address bus, the clock of transmitting element is from interface unit, transmitting element produces pseudorandom figure PRBS or word figure, wherein the PRBS pattern class has 2
6-1,2
9-1,2
11-1,2
15-1,2
20-1,2
23-1, perhaps anti-phase, the word figure has 16 bit programmables, complete " 0 ", complete " 1 ", 1010,1000; Insert the various error rates simultaneously in the figure that sends, the generation data format is that the figure of NRZ is sent into interface unit;
(5) interface unit is to the figure signal from transmitting element, after biphase coding and circuit driving, export on the K opening connector, test signal as the test of K interface error code, the received signal that receives from the K interface, reception in interface unit is reduced to the NRZ formatted data after amplifying, decoding, and these reception data are sent into receiving element;
(6) receiving element pursues bit relatively to the data and the local data that produce that receive, detect bit inequality and be error code, count results is sent into control unit by data/address bus, control unit is made a gift to someone the error code count results, and display shows in the machine interface, finishes the measurement of error code of K interface.
The present invention compared with prior art, its remarkable advantage: (1) does not need conversion equipment, can accurately, directly realize K interface error code test; (2) can be used as the standard that the K interface error code is tested, fill up the K interface error code and survey the instrument blank; (3) have principal and subordinate's working method, multiple test rate, multiple resolution chart; (4) convenient test, quick.
Description of drawings
Fig. 1 is a systematic schematic diagram of the present invention.
Fig. 2 is a control unit circuit schematic diagram of the present invention.
Fig. 3 is a main program flow chart of the present invention.
Fig. 4 is code error detector circuit theory diagrams of the present invention.
Fig. 5 is the synchronous decision flow chart of figure of the present invention.
Embodiment
Below in conjunction with accompanying drawing the present invention is described in further detail.
The present invention is based on K interface error code test macro, comprise following testing procedure:
1, test connects: connect the test interface of native system and the K interface of equipment under test by test cable;
2, test parameter is set: by the setup menu and the keyboard to set up test parameter of man-machine interface, in have mode of operation, transmission rate, resolution chart, the insertion error rate.Mode of operation has master mode and from two kinds of selections of mode; Transmission rate has; 16kbit/s, 32kbit/s, four kinds of speed of 64kbit/s, 128kbit/s; Resolution chart has pseudorandom figure (PRBS) and word figure two classes, and the PRBS pattern class has 2
6-1,2
9-1,2
11-1,2
15-1,2
20-1,2
23-1, can be anti-phase; The word figure has 16 bit programmables, complete " 0 ", complete " 1 ", 1010,1000; Insert the error rate: single, 10
-3～10
-6Select.Be provided with parameter as: working method is a master mode, and test rate 16kb/s, resolution chart are PRBS:2
6-1, anti-phase, inserting ratio is 10
-3
3, start measurement: the measurement button that clicks man-machine interface starts to be measured, and this button clicks to start and measures, and clicks to stop measurement again;
4, check measurement result: the menu as a result by man-machine interface is checked measurement result, and the measurement result content has error code number, the error rate, error performance analysis (meeting ITU-T G.821).The error rate of measurement result with test parameter is set in the error rate inserted when identical, illustrate that equipment under test does not have error code; If when inconsistent, illustrate that then equipment under test has produced error code.
In conjunction with Fig. 1, the present invention is based on K interface error code test macro, comprise interface unit, transmitting element, receiving element, clock unit, control unit and man-machine interface, man-machine interface connects control unit, control unit connects transmitting element, control unit also connects clock unit, receiving element and interface unit respectively simultaneously, transmitting element connecting interface unit, and interface unit connects receiving element and clock unit.Workflow is as follows: (1) comprises mode of operation, transmission rate, resolution chart, the insertion error rate by the setup menu and the keyboard to set up test parameter of man-machine interface.Be provided with parameter as: working method is a master mode, and test rate 16kb/s, resolution chart are PRBS:2
6-1, anti-phase, inserting ratio is 10
-3(2) control unit is controlled each unit according to the test parameter that is provided with, and links to each other with clock unit, transmitting element, receiving element by data/address bus, links to each other with interface unit by control circuit; (3) according to the transmission rate that is provided with, control unit is provided with the clock frequency that clock unit produces by data/address bus, clock unit generation 2048kHz or 8192kHz clock signal are (when transmission rate is set to 16kbit/s, 32kbit/s, clock unit produces the 2048kHz clock signal, when transmission rate is set to 64kbit/s, 128kbit/s, clock unit produces the 8192kHz clock signal), the clock signal of generation is sent into interface unit, as the system clock of interface unit; (4) according to the resolution chart that is provided with, insert the error rate, control unit is provided with the circuit of transmitting element by data/address bus, the clock of transmitting element is from interface unit.Transmitting element produces pseudorandom figure (PRBS) or word figure, and the PRBS pattern class has 2
6-1,2
9-1,2
11-1,2
15-1,2
20-1,2
23-1, can be anti-phase; The word figure has 16 bit programmables, complete " 0 ", complete " 1 ", 1010,1000.In the figure that sends, can insert the various error rates simultaneously and (single, 10 be arranged
-3～10
-6Select).The figure (data format is NRZ) that produces is sent into interface unit; (5) interface unit, exports on the K opening connector, as the test signal of K interface error code test after biphase coding and circuit driving the figure signal from transmitting element.From the received signal that the K interface receives, the reception in interface unit is reduced to the NRZ formatted data after amplifying, decoding, and these reception data are sent into receiving element; (6) receiving element pursues bit relatively to the data and the local data that produce (with the data of transmitting element generation) that receive, detects bit inequality and is error code, and count results is sent into control unit by data/address bus.Control unit is made a gift to someone the error code count results, and display shows in the machine interface, finishes the measurement of error code of K interface.
The interface unit that the present invention is based on K interface error code test macro is made up of digital network interface circuit, drive circuit and protective circuit; digital network interface circuit (as the MT9172 chip) connects drive circuit and protective circuit respectively, and drive circuit connects the K interface connector.In addition, the digital network interface circuit also connects clock unit, transmitting element and control unit respectively.Workflow is as follows: interface unit mode of operation, transmission rate are controlled by control unit, when mode of operation is master mode, the clock that the digital network interface circuit produces and the clock synchronization of clock unit, mode of operation is during from mode, and the clock that the digital network interface circuit produces is with to receive the data clock recovered synchronous.(four kinds of 16kbit/s, 32kbit/s, 64kbit/s and the 128kbit/s) that the clock rate that the digital network interface circuit produces and the transmission rate of man-machine interface setting are consistent.From the transmission figure (data format is NRZ) of transmitting element, behind digital network interface circuit biphase coding, send into drive circuit, by drive circuit output, protective circuit is carried out overvoltage protection to the signal of input and output at last.Receive the reception data from the K interface connector, send into the digital network interface circuit through drive circuit, extract clock and data decode, decoded data are the NRZ form, and clock and data are sent into receiving element together.
The transmitting element that the present invention is based on K interface error code test macro produces and inserts circuit by clock selecting, pattern generator, error code and forms, clock selection circuit connects pattern generator, pattern generator connects error code and produces and insert circuit, error code produces and inserts circuit connecting interface unit, and control unit is controlled transmitting element by data/address bus.Workflow is as follows: select one tunnel output from the two-way clock signal of interface unit in clock selection circuit, under the effect of clock, pattern generator produces PRBS pseudorandom figure (according to ITU-T standard O.151) and word figure signal, and the PRBS pattern class has 2
6-1,2
9-1,2
11-1,2
15-1,2
20-1,2
23-1, can be anti-phase; The word figure has 16 bit programmables, complete " 0 ", complete " 1 ", 1010,1000.Error code produces and inserts circuit and produces single or 10
-3～10
-6The error rate is inserted in the figure signal of transmission by inserting circuit simultaneously.
The receiving element that the present invention is based on K interface error code test macro is made up of local pattern generator, code error detector, error code and clock counter.Interface unit output connects code error detector, error code and the clock counter of receiving element respectively, and local pattern generator connects code error detector, and code error detector connects error code and clock counter, and error code is connected control unit with clock counter.Workflow is as follows: it is identical that figure that local pattern generator produces and transmitting element produce figure, reception data from interface unit are sent into code error detector with the data that local pattern generator produces, in code error detector, the data that receive and the data of local pattern generator compare by turn by comparator, if anything is wrong is an error code, and send rolling counters forward.Counter is to be used for clock, error code are counted, and the result of counter sends into control unit by data/address bus.
In conjunction with Fig. 4, the code error detector that the present invention is based on K interface error code test macro is a part of circuit important in the receiving element, the reception data that are made of from interface unit locking/non-locking switch, synchronous detecting, comparator connect locking/non-locking switch, synchronous detecting and comparator respectively, locking/non-locking switch connects the local pattern generator loop end in the receiving element, local pattern generator output connects synchronous detecting and comparator respectively, synchronous detecting connects the control end of locking/non-locking switch, and comparator connects the counter in the receiving element.Workflow is as follows: local pattern generator produces according to the figure that layout setting is set and sends the identical figure of figure, the data that receive and the data of local pattern generator are sent into comparator and synchronizing indicator respectively, in comparator, this two paths of data is carried out relatively special by turn, if anything is wrong is an error code, and send rolling counters forward.The clock that receives directly send rolling counters forward.The value of counter is read by control unit by data/address bus, and calculates the error rate.Measurement of error code at first will guarantee the data of local pattern generator and the data sync of reception (promptly at synchronization, two paths of data is identical), when asynchronous, adjusts synchronously in code error detector.In conjunction with Fig. 5, the figure synchronizing process is as follows:
(1) synchronously, under the condition of locking, (native system is defined as the error rate 5 * 10 greater than setting when the error code that detects
-2), it is asynchronous at this moment to be judged as figure, and then locking/non-locking switch is in unlock state, has disconnected the feedback control loop of local pattern generator, and the data of reception directly insert local pattern generator.That the figure synchronizing process is in is asynchronous, lock-out state not;
(2) asynchronous, not under the locking condition, synchronizing indicator carries out Error detection to the data of reception and the data of local pattern generator, there is not error code when detecting continuous 32 bits, at this moment be judged as figure genlocing, control locking/non-locking switch is got back to lock-out state again, the feedback loop closure of local pattern generator.The figure synchronizing process is in asynchronous, lock-out state;
(3) under asynchronous, locking condition, if the error code that detects is less than or equal to setting, it is synchronous at this moment to be judged as figure.The figure synchronizing process is in synchronously, lock-out state;
(4) under asynchronous, locking condition, asynchronous if the error code that detects, at this moment is judged as figure greater than setting.That the figure synchronizing process is in is asynchronous, lock-out state not;
(5) the synchronous adjustment process of figure is carried out in real time.
The clock unit that the present invention is based on K interface error code test macro is made up of crystal oscillator, Direct Digital Frequency Synthesizers DDS and filter circuit, crystal oscillator connects DDS, DDS connects filter circuit, and DDS connects control unit by data/address bus, filter circuit connecting interface unit simultaneously.Workflow is as follows: according to the transmission rate that is provided with in the man-machine interface, control unit is provided with the frequency values of DDS by data/address bus.The clock that crystal oscillator produces is sent into DDS, and as the reference clock of DDS, the clock of DDS output control unit setpoint frequency is exported after low-pass filter circuit filtering.The transmission rate relation that the clock of output and man-machine interface are provided with: when transmission rate is set to 16kbit/s, 32kbit/s, clock unit produces the 2048kHz clock signal, when transmission rate was set to 64kbit/s, 128kbit/s, clock unit produced the 8192kHz clock signal.
In conjunction with Fig. 2, the control unit that the present invention is based on K interface error code test macro is made up of CPU (as the SC2410 controller), program storage FLASH (as AM291v800BB70), data storage SDRAM (as IS62wv51216), crystal oscillator, RS232 interface, keyboard drive, display interface and data, address bus drive circuit.CPU is connected with program storage FLASH, data storage SDRAM and data, address bus drive circuit respectively by data/address bus and address bus, data, address bus drive circuit connect clock unit, transmitting element and receiving element respectively, crystal oscillator connects CPU, the display interface of CPU connects the display of human and machine interface unit, the I/O interface of CPU connects keyboard drive, keyboard drive connects the keyboard of man-machine interface, the RS232 interface of CPU connects the RS232 circuit, and the I/O mouth of CPU is connected to interface unit.Workflow is as follows: CPU according to the program that writes FLASH in advance to system be provided with, control, data processing and measurement result show, realizes the test of K interface error code.CPU reads the keyboard value by I/O interface and keyboard drive, and the display interface by CPU send display to show content and result are set, and respectively each unit is carried out exchanges data by data, address bus.
The man-machine interface that the present invention is based on K interface error code test macro is made up of keyboard and display.Keyboard is used for system parameter is set, and display is used for the demonstration of system, and all are provided with and object information shows on display, comprise the page, results page, the interpretation of result page be set, measure the timing page, the time is provided with the page etc.The page is set comprises contents such as mode of operation, transmission rate, resolution chart, the insertion error rate, results page shows the error code result, mainly contain error code counting, second error rate etc., the interpretation of result content of pages is the analysis of G..821 error performance, measure regularly page setup metering system and Measuring Time, the time is provided with page setup and revises system time.
In conjunction with Fig. 3, the system works flow process is as follows:
(1) after system's each several part powered on, CPU at first carried out initialization according to the program that writes FLASH in advance, comprised that system's real-time clock reads, and transmitting element, each port of receiving element are provided with DDS frequency configuration, counter O reset etc.;
(2) by the display and the keyboard to set up test parameter of man-machine interface, mainly contain working method, transmission rate, resolution chart, and insert bit eror rate;
(3) according to the transmission rate that is provided with, CPU is provided with the frequency values of DDS in the clock unit by data/address bus; According to the working method that is provided with, CPU is by the working method of digital network interface circuit in the I/O mouth control interface unit; According to the resolution chart that is provided with, the insertion error rate, control unit is provided with the corresponding circuits of transmitting element and receiving element by data/address bus;
(4) be set the testing time, have manual measurement, single measurement and regularly measure three types, as selecting manual measurement;
(5) begin to measure by measuring key;
(6) receiving element carries out Error detection and counting, and count results reads in interrupt routine in real time, carries out accumulation process in main program, calculates parameters such as total number of bit errors, clock frequency, second error rate.CPU makes a gift to someone these results, and display shows in the machine interface;
(7) stop to measure by measuring key, finish the measurement of error code of K interface;
(8) check the result: in measuring process or measure finish after, all can check measurement result.
Below by an example system work process is described: adopt K interface error code test macro of the present invention to carry out the test of K interface error code, the working method that interface is set is a master mode, and test rate 16kb/s, resolution chart are PRBS:2
6-1, anti-phase, inserting bit eror rate during test is 10
-3
At the display and the above-mentioned test parameter of keyboard to set up of man-machine interface, control unit is provided with the frequency values of DDS in the clock unit by data/address bus, makes clock unit produce the 2048kHz clock signal; Control unit is by I/O mouth control interface unit, and the working method that makes interface unit is a master mode, and the output 16kb/s clock that transmits and receive data is sent into transmitting element; Control unit is provided with the circuit of transmitting element and receiving element by data/address bus, makes transmitting element produce 2
6-1, anti-phase PRBS figure inserts 10 simultaneously in figure
-3The error rate.The figure that the local pattern generator of receiving element produces is 2
6-1, anti-phase PRBS figure; The signal that interface unit is sent into transmitting element carries out biphase coding and circuit drives back output, as the test signal of K interface error code test.From the received signal that the K interface receives, after receiving amplification, decoding, send into receiving element; Receiving element to the received signal with local pattern generator produce 2
6-1, anti-phase PRBS figure carries out measurement of error code, and the error code result sends into control unit by data/address bus; Control unit calculates and handles test result, calculates parameters such as total number of bit errors, clock frequency, second error rate, and error rate result is 10
-3, clock frequency result is 16kHz, the error code result is made a gift to someone display shows in the machine interface, finishes the measurement of error code of K interface.
Claims (9)
1, a kind of K interface error code test macro, it is characterized in that: by interface unit, transmitting element, receiving element, clock unit, control unit and man-machine interface are formed, man-machine interface connects control unit, control unit connects transmitting element respectively, clock unit, receiving element and interface unit, this transmitting element connecting interface unit, interface unit connects receiving element and clock unit respectively, parameter setting by man-machine interface, under the control of control unit, by the clock unit clock signal, transmitting element produces test data, through the interface unit conversion, drive output, the measured data of importing is received through interface unit, after the conversion, the input receiving element carries out the error code counting,, finish the measurement of error code of K interface after control unit send demonstration after handling.
2, K interface error code test macro according to claim 1, it is characterized in that: interface unit is made up of digital network interface circuit, drive circuit and protective circuit, the digital network interface circuit connects drive circuit and protective circuit respectively, drive circuit connects the K interface connector, and the digital network interface circuit also connects clock unit, transmitting element and control unit respectively simultaneously; Interface unit mode of operation, transmission rate are controlled by control unit, when mode of operation is master mode, the clock that the digital network interface circuit produces and the clock synchronization of clock unit, mode of operation be during from mode, and clock that the digital network interface circuit produces and reception data clock recovered are synchronous; From the transmission figure of transmitting element, behind digital network interface circuit biphase coding, send into drive circuit, by drive circuit output, protective circuit is carried out overvoltage protection to the signal of input and output at last; Receive the reception data from the K interface connector, send into the digital network interface circuit through drive circuit, extract clock and data decode, decoded data are the NRZ form, and clock and data are sent into receiving element together.
3, K interface error code test macro according to claim 1, it is characterized in that: transmitting element is by clock selecting, pattern generator, error code produces and inserts circuit and forms, clock selection circuit connects pattern generator, pattern generator connects error code and produces and insert circuit, error code produces and inserts circuit connecting interface unit, control unit is controlled transmitting element by data/address bus, in clock selection circuit, select one tunnel output from the two-way clock signal of interface unit, under the effect of clock, pattern generator produces PRBS pseudorandom figure and word figure signal, and the PRBS pattern class has 2
6-1,2
9-1,2
11-1,2
15-1,2
20-1,2
23-1, perhaps anti-phase; The word figure has 16 bit programmables, complete " 0 ", complete " 1 ", 1010,1000, and error code produces and inserts circuit and produces single or 10
-3～10
-6The error rate is inserted in the figure signal of transmission by inserting circuit simultaneously.
4, K interface error code test macro according to claim 1, it is characterized in that: receiving element is by local pattern generator, code error detector, error code and clock counter are formed, interface unit output connects code error detector respectively, error code and clock counter, local pattern generator connects code error detector, code error detector connects error code and clock counter, error code is connected control unit with clock counter, it is identical that figure that local pattern generator produces and transmitting element produce figure, reception data from interface unit are sent into code error detector with the data that local pattern generator produces, in code error detector, the data that receive and the data of local pattern generator compare by turn by comparator, if anything is wrong is an error code, and send rolling counters forward, counter is to be used for to clock, error code is counted, and the result of counter sends into control unit by data/address bus.
5, K interface error code test macro according to claim 4, it is characterized in that: code error detector is by locking/non-locking switch, synchronous detecting and comparator constitute, reception data from interface unit connect locking/non-locking switch respectively, synchronous detecting and comparator, locking/non-locking switch connects the local pattern generator loop end in the receiving element, local pattern generator output connects synchronous detecting and comparator respectively, synchronous detecting connects the control end of locking/non-locking switch, comparator connects the counter in the receiving element, local pattern generator produces according to the figure that layout setting is set and sends the identical figure of figure, the data that receive and the data of local pattern generator are sent into comparator and synchronizing indicator respectively, in comparator, this two paths of data is carried out relatively special by turn, if anything is wrong is an error code, and send rolling counters forward; The clock that receives directly send rolling counters forward, and the value of counter is read by control unit by data/address bus, and calculates the error rate.
6, K interface error code test macro according to claim 5, it is characterized in that: measurement of error code at first will guarantee the data of local pattern generator and the data sync of reception, promptly at synchronization, two paths of data is identical, when asynchronous, in code error detector, adjust synchronously: when error code greater than setting, at this moment it is asynchronous to be judged as figure, then locking/non-locking switch is in unlock state, disconnected the feedback control loop of local pattern generator, the data of reception directly insert local pattern generator; In synchronizing indicator, the data of reception and the data of local pattern generator are carried out Error detection, do not have error code, at this moment be judged as figure genlocing when detecting continuous 32 bits, control locking/non-locking switch is got back to lock-out state again, the feedback loop closure of local pattern generator; When the error code that detects less than setting, it is synchronous at this moment to be judged as figure; If it is asynchronous that the error code that detects, at this moment is judged as figure greater than setting, the synchronous adjustment process of repetitive pattern.
7, K interface error code test macro according to claim 1, it is characterized in that: clock unit is made up of crystal oscillator, DDS and filter circuit, and crystal oscillator connects DDS, and DDS connects filter circuit, DDS connects control unit by data/address bus, filter circuit connecting interface unit simultaneously; According to the transmission rate that is provided with in the man-machine interface, control unit is provided with the frequency values of DDS by data/address bus, the clock that crystal oscillator produces is sent into DDS, reference clock as DDS, the clock of DDS output control unit setpoint frequency, after low-pass filter circuit filtering, export, the clock of output and the relation of transmission rate: when transmission rate is set to 16kbit/s, 32kbit/s, clock unit produces the 2048kHz clock signal, when transmission rate was set to 64kbit/s, 128kbit/s, clock unit produced the 8192kHz clock signal.
8, K interface error code test macro according to claim 1, it is characterized in that: control unit is by CPU, program storage FLASH, data storage SDRAM, crystal oscillator, the RS232 interface, keyboard drive, display interface and data, the address bus drive circuit is formed, CPU by data/address bus and address bus respectively with program storage FLASH, data storage SDRAM and data, the address bus drive circuit connects, data, the address bus drive circuit connects clock unit respectively, transmitting element and receiving element, crystal oscillator connects CPU, the display interface of CPU connects the display of human and machine interface unit, the I/O interface of CPU connects keyboard drive, keyboard drive connects the keyboard of man-machine interface, the RS232 interface of CPU connects the RS232 circuit, the I/O mouth of CPU is connected to interface unit, CPU reads the keyboard value by I/O interface and keyboard drive, display interface by CPU send display to show content and result are set, and passes through data, address bus carries out exchanges data to each unit respectively; CPU according to the program that writes FLASH in advance to system be provided with, control, data processing and measurement result show, realizes the test of K interface error code.
9, a kind of method of testing that realizes by the described K interface error code of claim 1 test macro is characterized in that:
(1) by the setup menu and the keyboard to set up test parameter of man-machine interface, comprises mode of operation, transmission rate, resolution chart, the insertion error rate;
(2) control unit is controlled each unit according to the test parameter that is provided with, and links to each other with clock unit, transmitting element, receiving element by data/address bus, links to each other with interface unit by control circuit;
(3) according to the transmission rate that is provided with, control unit is provided with the clock frequency that clock unit produces by data/address bus, clock unit produces 2048kHz or 8192kHz clock signal, when transmission rate is set to 16kbit/s, 32kbit/s, clock unit produces the 2048kHz clock signal, and when transmission rate was set to 64kbit/s, 128kbit/s, clock unit produced the 8192kHz clock signal, the clock signal that produces is sent into interface unit, as the system clock of interface unit;
(4) according to the resolution chart that is provided with, insert the error rate, control unit is provided with the circuit of transmitting element by data/address bus, the clock of transmitting element is from interface unit, transmitting element produces pseudorandom figure PRBS or word figure, wherein the PRBS pattern class has 2
6-1,2
9-1,2
11-1,2
15-1,2
20-1,2
23-1, perhaps anti-phase, the word figure has 16 bit programmables, complete " 0 ", complete " 1 ", 1010,1000; Insert the various error rates simultaneously in the figure that sends, the generation data format is that the figure of NRZ is sent into interface unit;
(5) interface unit is to the figure signal from transmitting element, after biphase coding and circuit driving, export on the K opening connector, test signal as the test of K interface error code, the received signal that receives from the K interface, reception in interface unit is reduced to the NRZ formatted data after amplifying, decoding, and these reception data are sent into receiving element;
(6) receiving element pursues bit relatively to the data and the local data that produce that receive, detect bit inequality and be error code, count results is sent into control unit by data/address bus, control unit is made a gift to someone the error code count results, and display shows in the machine interface, finishes the measurement of error code of K interface.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910184522 CN101645767B (en) | 2009-08-28 | 2009-08-28 | K interface error code testing method and system thereof |
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|---|---|---|---|
| CN 200910184522 CN101645767B (en) | 2009-08-28 | 2009-08-28 | K interface error code testing method and system thereof |
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| CN101645767A true CN101645767A (en) | 2010-02-10 |
| CN101645767B CN101645767B (en) | 2013-03-27 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101882986A (en) * | 2010-06-28 | 2010-11-10 | 深圳市国扬通信股份有限公司 | Error code tester |
| CN102183722A (en) * | 2011-02-28 | 2011-09-14 | 华为技术有限公司 | Chip |
| CN105634861A (en) * | 2015-12-23 | 2016-06-01 | 中国电子科技集团公司第四十一研究所 | New type serial error code tester |
| CN107331421A (en) * | 2017-06-09 | 2017-11-07 | 中国电子科技集团公司第四十研究所 | A kind of SD card test system and method based on FPGA |
| CN108242981A (en) * | 2016-12-27 | 2018-07-03 | 航天信息股份有限公司 | Device for detecting code error |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100349112C (en) * | 2002-09-05 | 2007-11-14 | 中兴通讯股份有限公司 | Method of multifunctional testing digital interface and its device |
| CN101141227B (en) * | 2007-01-31 | 2012-04-04 | 中兴通讯股份有限公司 | Error code testing device and system |
-
2009
- 2009-08-28 CN CN 200910184522 patent/CN101645767B/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101882986A (en) * | 2010-06-28 | 2010-11-10 | 深圳市国扬通信股份有限公司 | Error code tester |
| CN102183722A (en) * | 2011-02-28 | 2011-09-14 | 华为技术有限公司 | Chip |
| CN102183722B (en) * | 2011-02-28 | 2014-03-05 | 华为技术有限公司 | Chip |
| CN105634861A (en) * | 2015-12-23 | 2016-06-01 | 中国电子科技集团公司第四十一研究所 | New type serial error code tester |
| CN108242981A (en) * | 2016-12-27 | 2018-07-03 | 航天信息股份有限公司 | Device for detecting code error |
| CN107331421A (en) * | 2017-06-09 | 2017-11-07 | 中国电子科技集团公司第四十研究所 | A kind of SD card test system and method based on FPGA |
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| Publication number | Publication date |
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| CN101645767B (en) | 2013-03-27 |
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