CN101645484A

CN101645484A - Soft support bridge type silicon micro-piezoelectric ultrasonic transducer chip and prepration method thereof

Info

Publication number: CN101645484A
Application number: CN 200910078945
Authority: CN
Inventors: 李俊红; 汪承灏; 刘梦伟; 徐联
Original assignee: Institute of Acoustics CAS
Current assignee: Institute of Acoustics CAS
Priority date: 2009-03-02
Filing date: 2009-03-02
Publication date: 2010-02-10
Anticipated expiration: 2029-03-02
Also published as: CN101645484B

Abstract

The invention relates to a soft support bridge type silicon micro-piezoelectric ultrasonic transducer chip which comprises a silicon substrate with a square conical hole which is small at the top andbig at the bottom in the center; a silicon layer and a first oxidation layer are sequentially covered on the front surface of the silicon substrate, and a second oxidation layer is covered on the backsurface; the corresponding silicon layer and the first oxidation layer above the square hole of the front surface of the silicon substrate constitute a square vibration membrane, one pair of oppositesides of the square vibration membrane respectively etch a vertical narrow slot, and the vertical projection of each narrow slot is positioned on the inner side of the hole edge above the front surface of the silicon substrate; a lower electrode, a piezoelectric membrane and an upper electrode are sequentially deposited on the square vibration membrane; a polyimide membrane is deposited on various parts on the front surface of the silicon substrate; and the square vibration membrane which is etched with the vertical narrow slots and the polyimide membrane commonly constitute a soft support anti-sound leakage bridge type vibration membrane. The anti-sound leakage bridge type structure is used on the vibration membrane of the transducer; in order to avoid sound leakage through the narrow slots, the soft polyimide membrane is deposited on the narrow slots, which has little effect on vibration of the vibration membrane and can still keep high sensitivity.

Description

Soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip and preparation method thereof

Technical field

The present invention relates to silicon micro piezoelectric ultrasonic transducer field, particularly a kind of soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip and preparation method thereof.

Background technology

Silicon micro-ultrasonic transducer mainly by two kinds of piezoelectric type and condenser types, be made up of piezoelectric layer, vibrating membrane, metal electrode by the silicon micro piezoelectric ultrasonic transducer.For the silicon micro capacitor ultrasonic transducer, piezoelectric ultrasonic transducer has simple in structure, and preparation technology is simple; And impedance is low, and is suitable to transmitting transducer.At present the vibrating membrane of silicon micro piezoelectric ultrasonic transducer all is that prop up admittedly on four limits, thus ultrasonic transducer when vibration, piezoelectric layer causes the remolding sensitivity of ultrasonic transducer lower owing to diminishing.In order to increase the strain of the piezoelectric layer that transducer the time causes in vibration, the sensitivity that improves ultrasonic transducer just is necessary to design novel ultrasonic transducer structure.

Summary of the invention

The object of the present invention is to provide a kind of anti-sound leakage soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip and preparation method thereof, to improve the sensitivity of ultrasonic transducer.Should prevent sound leakage soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip, by two slits of a pair of opposite side etching at vibrating membrane, thereby the unfettered Stress Release in the both sides that make vibrating membrane, make vibrating membrane become the bridge-type vibrating membrane, with respect to piezoelectric ultrasonic transducer, because vibrating membrane has only the both sides fixed support, so transducer is when work with the solid Zhi Chuantong vibrating membrane in four limits, can cause the strain that piezoelectric layer is bigger, thereby obviously improve the sensitivity of ultrasonic transducer; But the slit on both sides can cause sound leakage, influences the smooth of sensitivity and frequency response.In order to prevent sound leakage, chip of the present invention is at two plastic films such as polyimide film that deposition above the slit is soft, because polyimide film quality softness, so limited to the vibration effect of vibrating membrane, and can waterproof.The formed ultrasonic transducer of this structure will have higher sensitivity.In addition, in ultrasonic field, particularly during ultrasonography, often transducer (array element) need be formed transducer array, for transducer array, this structure also has a very big advantage: because the polyimide plastic film is very soft, it can effectively suppress mutual vibration coupling harmful between the array element.Technical scheme of the present invention is as follows:

Soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip provided by the invention, it comprises:

One silicon chip 1; Described silicon chip 1 center is provided with the up-small and down-big square bellmouth that forms by the body etching; Be covered with one deck silicon layer 2 and first oxide layer 3 on described silicon chip 1 front successively, be covered with one deck second oxide layer 4 on described silicon chip 1 back side; Described second oxide layer 4 centers be provided with silicon chip 1 back side on the square hole of square hole same size; The silicon layer 2 and first oxide layer 3 corresponding on the described silicon chip 1 positive upper aperture are square vibrating membrane, the a pair of opposite side of this square vibrating membrane one of etching respectively runs through the vertical slit 31 of the silicon layer 2 and first oxide layer 3, and the vertical projection of described vertical slit 31 is positioned at the inboard, positive upper aperture edge of described silicon chip 1;

Be deposited on the described square vibrating membrane and the graphical bottom electrode 6 that forms; Described bottom electrode 6 is the aluminium bottom electrode with vacuum evaporation equipment or sputtering equipment preparation 0.01～1 μ m thickness, or the compound bottom electrode of Cr/Au for being made of Cr layer and Au layer, or the compound bottom electrode of Ti/Pt for being made of Ti layer and Pt layer; Described Cr layer and Ti layer thickness are 0.01～0.1 μ m; Described Au layer and Pt layer thickness are 0.05～0.5 μ m;

Be deposited on the bottom electrode 6 and the graphical piezoelectric film 7 that forms;

Be deposited on described piezoelectric film 7 lip-deep patterned top electrodes 9; With

Be deposited on the patterned polyimide film 5 on each parts on described silicon chip 1 upper surface;

Be etched with the square vibrating membrane and the anti-sound leakage bridge-type vibrating membrane of the soft support of polyimide film 5 common formations of vertical slit 31.

Soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip provided by the invention also can be included in the 3rd oxide layer 12 between described silicon layer 2 and the silicon chip 1; Described the 3rd oxide layer 12 centers be provided with silicon chip 1 front on the square hole of square hole same size; Described the 3rd oxide layer 12 thickness are 0.1～10 μ m.

Soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip provided by the invention also can comprise the silicon oxide film protective layer 8 that is deposited between described piezoelectric film 7 and the top electrode 9; Described vertical slit 31 runs through square composite membrane vibration and described silicon oxide film protective layer 8.

Described vertical slit 31 width are 0.1～50 μ m.

Described piezoelectric film 7 is zinc oxide piezoelectric film, aluminium nitride, lead zirconate titanate piezoelectric film, Ca-Ti ore type piezoelectric film or organic piezoelectric film.Described piezoelectric film 7 thickness are 0.1～20 μ m.

Described polyimide film 5 thickness are 0.01～10 μ m.

Described silicon layer 2 thickness are 0.5～100 μ m.

Described first oxide layer, 3 thickness are 0.1～5 μ m.

The preparation method of soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip provided by the invention, its preparation process is as follows:

Clean substrate: clean substrate with acidic cleaning solution and alkaline cleaning fluid respectively earlier, rinse well with deionized water more afterwards;

Described substrate is silicon chip or SOI substrate;

When described substrate was silicon chip, the preparation process of described soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip was as follows:

1) forms the boron diffusion screen by thermal oxidation

On the silicon chip surface, utilizing the thermal oxidation furnace oxide thickness is the oxide layer of 1 μ m, and removes the oxide layer on the silicon chip front;

2) silicon layer 2 forms

In diffusion furnace, silicon chip is carried out boron diffusion, carry out oxidation processes after having spread again, the positive silicon layer 2 that forms boron diffusion of silicon chip this moment utilizes the method for oxidation to form the B silex glass on the silicon chip surface, utilizes buffered hydrofluoric acid solution to remove the B silex glass and the lower surface oxide layer on silicon chip surface;

3) preparation of oxide layer

In oxidation furnace silicon chip is carried out oxidation processes, in positive first oxide layer 3 that forms of silicon chip, silicon chip back of the body surface forms second oxide layer 4;

4) preparation bottom electrode 6

In first oxide layer, 3 upper surface centers, utilize vacuum evaporation equipment or magnetron sputtering apparatus to prepare bottom electrode 6, and graphical; Described bottom electrode 6 is for utilizing the aluminium bottom electrode of vacuum evaporation equipment or sputtering equipment preparation 0.01～1 μ m thickness, or for the compound bottom electrode of Cr/Au that constitutes by Cr layer and Au layer compound, or the compound bottom electrode of Ti/Pt layer for constituting by Ti layer and Pt layer; Described Cr layer and Ti layer thickness are 0.01～0.1 μ m; Described Au layer and Pt layer thickness are 0.05～0.5 μ m;

5) preparation piezoelectric film 7

On the surface of described bottom electrode 6, prepare piezoelectric film; Be coated with positive photoresist on the surface of piezoelectric film, photolithographic exposure forms the piezoelectric film litho pattern; Corrode piezoelectric film with corrosive liquid, form the piezoelectric film of required figure, remove residual photoresist, finish patterned piezoelectric film 7 preparations;

6) on piezoelectric film 7, directly prepare top electrode 9; Perhaps on piezoelectric film 7, prepare the silicon oxide film protective layer earlier, again preparation top electrode 9 on this silicon oxide film protective layer:

(a) the described top electrode 9 that directly prepares on piezoelectric film 7 is:

Resist coating on the silicon chip front, photolithographic exposure forms the top electrode anti-graphics; Again with vacuum evaporation or magnetron sputtering 0.01～0.1 μ m thickness C r layer and 0.05～0.5 μ m thickness A u layer; Or utilize vacuum evaporation equipment or sputtering equipment preparation 0.01～1 μ m thickness A l or 0.01～1 μ m thickness Pt layer to form the top electrode metallic diaphragm; Remove photoresist with acetone, finish the preparation of top electrode 9;

(b) the described silicon oxide film protective layer that on piezoelectric film 7, prepares earlier, preparation top electrode 9 is on this silicon oxide film protective layer again:

On the silicon chip front, utilizing plasma-assisted chemical gaseous phase deposition device deposition thickness is 0.01～0.5 μ m silicon oxide film protective layer;

Be coated with positive photoresist on silicon oxide film protective layer surface, photolithographic exposure forms the protective layer litho pattern; Utilize high-density plasma etching machine to carry out photoetching corrosion, etchant gas is a sulphur hexafluoride, forms the protective layer figure; Remove residual photoresist, finish the preparation of silicon oxide film protective layer 8;

Resist coating on silicon oxide film protective layer 8 surfaces, photolithographic exposure forms the top electrode anti-graphics; Again with vacuum evaporation or magnetron sputtering 0.01～0.1 μ m thickness C r layer and 0.05～0.5 μ m thickness A u layer; Or utilize vacuum evaporation equipment or sputtering equipment preparation 0.01～1 μ m thickness A l or 0.01～1 μ m thickness Pt layer to form the top electrode metallic diaphragm; Remove photoresist with acetone, finish the preparation of top electrode 9;

7) body silicon etching

The Au/Cr composite membrane 10 that deposits the Au of the Cr of 0.01～0.1 μ m thickness and 0.05～0.5 μ m thickness on the surface of the oxide layer 4 at the silicon chip back side comes the mask of assisted oxidation layer 4 as the body silicon etching; On Au/Cr composite membrane 10, be coated with positive photoresist, utilize the double-sided exposure machine to carry out double-sided exposure, organizator etch mask litho pattern on Au/Cr composite membrane 10, and order is corroded Au layer, Cr layer and oxide layer 4, removal residual photoresist, the preparation of perfect aspect etch mask, when corrosion Au layer, Cr layer and oxide layer 4, the silicon chip front will be protected with photoresist, after corroding, removes photoresist;

, put into 35%KOH solution and carry out the body etching the silicon chip sealing and fixing with body etching anchor clamps, carve silicon chip, when etching boron diffusion silicon, stop etching; Resist coating on the silicon chip front, the Au/Cr film at the corrosion silicon chip back side is compound 10, and removes positive photoresist;

8) preparation Al supporting layer 11

In the up-small and down-big square bellmouth of silicon chip, utilize the Al supporting layer 11 of vacuum evaporation equipment or sputtering equipment preparation 0.01～10 μ m thickness, the supporting layer during as the etching slit; The mask layer in silicon chip front is photoresist mask layer or Al mask layer during the slit etching; When using photoresist mask layer, resist coating on the silicon chip front then, photolithographic exposure forms the required photoresist mask of slit etching; When using the Al mask layer, then, utilize and peel off or the graphical Al film of corroding method at the positive deposition of silicon chip 0.01～1 μ m Al film, form the required Al mask of slit etching;

9) etching slit

Utilize wet etching that oxide layer 3 and silicon oxide film protective layer 8 are corroded, utilize dry etching that the silicon layer 2 of B diffusion is carried out etching, finish the etching of slit; When utilizing wet etching corrosion oxidation layer 3 and silicon oxide film protective layer 8, the silicon chip back side applies photoresist, with protection Al supporting layer 11; Simultaneously after the slit etching is intact, the mask layer in erosion removal silicon chip front, and remove the photoresist at the silicon chip back side with acetone, the width of slit is 0.1～50 μ m.

10) filling of slit

Resist coating on the silicon chip front, photolithographic exposure, form and fill the required mask patterns of slit, utilize the Al layer of preparation of vacuum evaporation equipment or sputtering equipment and slit depth same thickness, perhaps utilize the ZnO layer of sputtering equipment preparation and slit depth same thickness, remove photoresist with acetone, graphical Al layer or ZnO layer are finished the filling of slit;

11) preparation polyimide film 5

At the positive preparation of silicon chip thickness is 0.01～10 μ m polyimide film, and it is carried out graphically exposing the pressure welding contact of upper/lower electrode;

12) release of slit and vibrating membrane

Resist coating on the silicon chip front, the protective layer in front during as release slit and vibrating membrane; Silicon chip is put into corrosive liquid, the Al supporting layer 11 at the corrosion silicon chip back side and be filled in the Al layer or the ZnO layer of slit, discharge slit and vibrating membrane, and remove the photoresist in silicon chip front, finish the preparation of soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip;

When substrate was the SOI substrate, the preparation process of described soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip was as follows:

1 ') preparation of oxide layer

In oxidation furnace the SOI substrate is carried out oxidation processes, in positive first oxide layer (3) that forms of SOI substrate, the SOI substrate back forms second oxide layer 4;

2 ') preparation bottom electrode 6

In first oxide layer, 3 upper surface centers, utilize vacuum evaporation equipment or magnetron sputtering apparatus to prepare bottom electrode 6, and graphical; Described bottom electrode 6 is for utilizing the aluminium bottom electrode of vacuum evaporation equipment or sputtering equipment preparation 0.01～1 μ m thickness, or for the compound bottom electrode of Cr/Au that constitutes by Cr layer and Au layer compound, or the compound bottom electrode of Ti/Pt for constituting by Ti layer and Pt layer; Described Cr layer and Ti layer thickness are 0.01～0.1 μ m; Described Au layer and Pt layer thickness are 0.05～0.5 μ m;

3 ') preparation piezoelectric film 7

4 ') on piezoelectric film 7, directly prepare top electrode 9; Perhaps on piezoelectric film 7, prepare the silicon oxide film protective layer earlier, again preparation top electrode 9 on this silicon oxide film protective layer:

(a ') described on piezoelectric film 7 directly preparation top electrode 9 be:

Resist coating on SOI substrate front, photolithographic exposure forms the top electrode anti-graphics; Again with vacuum evaporation or magnetron sputtering 0.01～0.1 μ m thickness C r layer and 0.05～0.5 μ m thickness A u layer; Or utilize vacuum evaporation equipment or sputtering equipment preparation 0.01～1 μ m thickness A l or 0.01～1 μ m thickness Pt layer to form the top electrode metallic diaphragm; Remove photoresist with acetone, finish the preparation of top electrode 9;

(b ') the described silicon oxide film protective layer that on piezoelectric film 7, prepares earlier, preparation top electrode 9 is on this silicon oxide film protective layer again:

On SOI substrate front, utilizing plasma-assisted chemical gaseous phase deposition device deposition thickness is 0.01～0.5 μ m silicon oxide film protective layer;

5 ') body silicon etching

On the surface of second oxide layer 4 of SOI substrate back, deposit the Cr/Au composite membrane 10 that the Au of the Cr of 0.01～0.1 μ m thickness and 0.05～0.5 μ m thickness constitutes and assist the mask of second oxide layer 4 as the body silicon etching; On Cr/Au composite membrane 10, be coated with positive photoresist, utilize the double-sided exposure machine to carry out double-sided exposure, organizator etch mask litho pattern on Cr/Au composite membrane 10, and order is corroded Au layer, Cr layer and second oxide layer 4, removal residual photoresist, the preparation of perfect aspect etch mask, when corrosion Au layer, Cr layer and second oxide layer 4, SOI substrate front is protected with photoresist, after corroding, removes photoresist;

, put into 35%KOH solution and carry out the body etching SOI substrate sealing and fixing with body etching anchor clamps, carve the SOI substrate, during thermooxidative layer in etching into the SOI substrate, stop etching; Resist coating on SOI substrate front, the Cr/Au composite membrane 10 of corrosion SOI substrate back, and remove the photoresist in SOI substrate front;

6 ') thermooxidative layer in the etching SOI substrate

To the two-sided resist coating of SOI substrate, and the SOI substrate back carried out photolithographic exposure, form the photoresist mask pattern of the thermooxidative layer center square hole in the etching SOI substrate; Utilize the method for dry method or wet method that the thermooxidative layer in the SOI substrate is carried out etching, after etching is finished, with the photoresist on the acetone removal SOI;

7 ') preparation Al supporting layer 11

Utilize the Al supporting layer 11 of vacuum evaporation equipment or sputtering equipment preparation 0.01～10 μ m thickness, the supporting layer during as the etching slit at the SOI substrate back; The mask layer in SOI substrate front is photoresist mask layer or Al mask layer during the slit etching; When using photoresist mask layer, resist coating on SOI substrate front then, photolithographic exposure forms the required photoresist mask of slit etching; When using the Al mask layer, then, utilize and peel off or the graphical Al film of corroding method at the positive deposition of SOI substrate 0.01～1 μ m Al film, form the required Al mask of slit etching;

8 ') etching slit

Utilize wet etching that first oxide layer 3 and silicon oxide film protective layer 8 are corroded, utilize dry etching that silicon layer in the SOI substrate is carried out etching, finish the etching of slit; When utilizing wet etching to corrode first oxide layer 3 and silicon oxide film protective layer 8, the SOI substrate back applies photoresist, with the Al supporting layer 11 of protection SOI substrate back; Simultaneously after the slit etching is intact, the mask layer in erosion removal SOI substrate front, and remove the photoresist of SOI substrate back with acetone, the width of slit is 0.1～50 μ m;

9 ') filling of slit

Resist coating on SOI substrate front, photolithographic exposure, form and fill the required mask patterns of slit, utilize the Al layer of preparation of vacuum evaporation equipment or sputtering equipment and slit depth same thickness, perhaps utilize the ZnO layer of sputtering equipment preparation and slit depth same thickness, remove photoresist with acetone, graphical Al layer or ZnO layer are finished the filling of slit;

10 ') preparation polyimide film 5

At the positive preparation of SOI substrate thickness is 0.01～10 μ m polyimide film, and it is carried out graphically exposing the pressure welding contact of upper/lower electrode;

11 ') release of slit and vibrating membrane

Resist coating on SOI substrate front, the protective layer in SOI substrate front during as release slit and square vibrating membrane; The SOI substrate is put into corrosive liquid, the Al supporting layer 11 and the Al layer or the ZnO layer that are filled in slit of corrosion SOI substrate back, discharge slit and square vibrating membrane, and remove the photoresist in SOI substrate front, finish the preparation of soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip.

The present invention is at the positive formation composite membrane vibration that silicon layer and thermooxidative layer constituted of substrate, and the reverse side at silicon chip when the front thermooxidative layer forms also forms one deck thermooxidative layer; Successively depositing metal bottom electrode, piezoelectric layer and top electrode on composite membrane vibration then; Constitute composite metal membrane in the reverse side of substrate deposition by Cr and Au and come the mask of assisted oxidation layer as the body silicon etching; Composite metal membrane and oxide layer to the silicon chip back side are carried out photoetching, etching, the mask that the organizator etching is required; The body etching discharges composite membrane vibration, and at the backside deposition Al of silicon chip layer, during as front slit etching, to the supporting layer of vibrating membrane; On two opposite side of composite membrane vibration, etch slit by dry method and wet etching technique respectively, make square vibrating membrane become the bridge-type vibrating membrane; At silicon chip positive deposition ZnO or Al sacrifice layer, and graphical, finish the filling of slit; Front at silicon chip deposits polyimide film, and graphically exposes the pressure welding contact of electrode; The Al layer supporting layer at the corrosion back side and the sacrifice layer in the slit are finished the preparation of ultrasonic transducer.Method of the present invention prepares ultrasonic transducer and has anti-sound leakage bridge architecture, can obviously improve the sensitivity of ultrasonic transducer, and the realization processing compatibility of this ultrasonic transducer is good, the convenience is feasible.

The present invention adopts the bridge architecture vibrating membrane to replace square vibrating membrane, deposits such as plastic films such as polyimides on the slit that forms bridge architecture again in order to prevent sound leakage, has so promptly prevented the sound leakage phenomenon, again can waterproof.And less to transducer vibration effect, can guarantee that again the piezoelectricity composite bed can produce bigger strain when vibration, the final silicon micro piezoelectric ultrasonic transducer that forms with anti-sound leakage bridge architecture.

The invention has the advantages that: first anti-sound leakage bridge architecture is applied in the vibrating membrane of silicon micro piezoelectric ultrasonic transducer among the present invention, vibrating membrane is owing to have bridge architecture like this, so in the process of vibration, can produce big strain, thereby can improve the sensitivity of transducer.For the leakage sound problem of passing through the both sides slit that prevents that the bridge architecture ultrasonic transducer from existing, deposition polyimide film on slit is because polyimide film is softer, so not too large to the influence of vibration vibration of membrane generation.Therefore the ultrasonic transducer of this structure has higher sensitivity.And when transducer formed array, it can also suppress the harmful vibration coupling between transducer array element effectively.

Description of drawings:

Fig. 1 is the profile that thermooxidative layer/silicon layer composite membrane forms the back ultrasonic transducer;

Fig. 2 forms the generalized section of back ultrasonic transducer for hearth electrode;

Fig. 3 forms the generalized section of back ultrasonic transducer for piezoelectric layer and top electrode;

Fig. 4 is the generalized section of ultrasonic transducer behind the degree of depth body silicon etching;

Fig. 5 is the generalized section of ultrasonic transducer after the slit etching;

Fig. 6 is the schematic top plan view of ultrasonic transducer after the slit etching;

Fig. 7 is a generalized section of the present invention, and wherein 7 (a) realize that by silicon chip 7 (b) realize by the SOI substrate;

Embodiment

With reference to accompanying drawing, will be described in detail embodiment of the present invention.

Embodiment 1, adopts preparation method of the present invention to prepare a novel piezoelectric ultrasonic transducer chip, and its step is as follows:

1) cleans silicon chip 1

Clean silicon chip 1 with acidic cleaning solution and alkaline cleaning fluid respectively earlier, rinse well with deionized water more afterwards;

2) form the B diffusion impervious layer by thermal oxidation

On silicon chip 1, utilizing the thermal oxidation furnace oxide thickness is the oxide layer of 1 μ m, and removes positive oxide layer, and forming thickness like this on the back side of substrate 1 is the oxidation film layer of 1 μ m;

3) boron diffusion

In diffusion furnace, silicon chip 1 is carried out boron diffusion, carry out oxidation processes after having spread again, form the B silex glass on silicon chip 1 surface, utilize buffered HF to remove the B silex glass on silicon chip 1 surface and the oxide layer at the back side, finally the thickness at the positive B diffusion silicon layer that forms of substrate is 13 μ m.

4) preparation of oxide layer

In oxidation furnace silicon chip 1 is carried out oxidation processes, in positive first oxide layer 3 that forms of substrate, thickness is 0.5 μ m, and reverse side has one deck second oxide layer 4, and thickness is 0.5 μ m;

5) preparation bottom electrode 6

On first oxide layer 3, utilize vacuum evaporation equipment to deposit the Al layer of 5 μ m thickness, with the formation lower electrode layer, and utilize pattern technology formationization bottom electrode 6; Finish the preparation of bottom electrode 6;

6) preparation piezoelectric film 7

Preparation piezoelectric film ZnO on the surface of bottom electrode 6, thickness is 6 μ m;

Be coated with positive photoresist on the surface of piezoelectric film, photolithographic exposure forms the piezoelectric film litho pattern; Corrode piezoelectric film with corrosive liquid, form the piezoelectric film 7 of required figure, remove residual photoresist, finish piezoelectric film 7 preparations;

7) preparation top electrode 9

On the surface of piezoelectric film 7, utilizing plasma-assisted chemical gaseous phase deposition device deposition thickness is 0.2 μ m silicon oxide film protective layer;

Be coated with positive photoresist on the protective layer surface, photolithographic exposure forms the protective layer litho pattern; Utilize high-density plasma etching machine to carry out photoetching corrosion, etchant gas is a sulphur hexafluoride, forms the protective layer figure; Remove residual photoresist, finish the preparation of silicon oxide film protective layer 8;

Resist coating on silicon oxide film protective layer 8 surfaces, photolithographic exposure forms the top electrode anti-graphics; Utilize vacuum evaporation equipment to deposit the Al layer of 0.5 μ m thickness again, to form upper electrode layer; Remove photoresist with acetone, finish the preparation of top electrode 9;

8) body silicon etching

The Cr of deposition 0.04 μ m thickness and the Au of 0.1 μ m thickness assist the mask of second oxide layer 4 as the body silicon etching on the surface of second oxide layer 4 at the back side of silicon chip 1.Be coated with positive photoresist, utilize the double-sided exposure machine to carry out double-sided exposure, organizator etch mask litho pattern on silicon chip 1 back side, and order is corroded Au layer, Cr layer, second oxide layer 4, organizator etch mask overleaf; Remove residual photoresist, the preparation of perfect aspect etch mask, when corrosion Au layer, Cr layer, second oxide layer 4, the front will be protected with photoresist, after corroding, removes photoresist;

, put into 35%KOH solution and carry out the body etching silicon chip 1 sealing and fixing with body etching anchor clamps, discharge square composite membrane vibration fully.Resist coating on the front, the Cr and the Au at the corrosion back side, and remove positive photoresist.

9) utilize vacuum evaporation equipment or sputtering equipment to prepare the Al supporting layer 11 of 1 μ m thickness, the supporting layer during as the etching slit at the reverse side of silicon chip 1.Resist coating on the front of silicon chip 1, photolithographic exposure forms the required photoresist mask of slit etching;

10) utilize wet etching that first oxide layer 3 and silicon oxide film protective layer 8 are corroded, utilize dry etching that the silicon layer 2 of B diffusion is carried out etching, finish the etching of slit.When utilizing wet etching first oxide layer 3 and silicon oxide film protective layer 8, the back side of silicon chip 1 will apply photoresist, with the Al supporting layer 11 at the protection back side, after corroding, removes photoresist.After the slit etching is intact, remove positive mask layer simultaneously, the width of slit is 20 μ m.

11) resist coating on the front of silicon chip 1, photolithographic exposure forms and fills the required mask patterns of slit, utilizes vacuum evaporation equipment to prepare the ZnO layer of 13.3 μ m thickness, removes photoresist with acetone, and the graphical ZnO layer is finished the filling of slit.

12) preparing thickness in the front of silicon chip 1 is 0.7 μ m polyimide film, and it is carried out graphically exposing the pressure welding contact of upper/lower electrode.

13) resist coating on the front of silicon chip 1, the protective layer in front during as release slit and vibrating membrane.Silicon chip 1 is put into phosphoric acid corrosion liquid, and the ZnO layer of corrosion back side Al supporting layer 11 and filling slit discharges slit and vibrating membrane, and removes positive photoresist, finishes preparation of devices.

Embodiment 2, adopt preparation method of the present invention to prepare a novel piezoelectric ultrasonic transducer chip, and its step is as follows:

1) cleans the SOI substrate

Clean the SOI substrate with acidic cleaning solution and alkaline cleaning fluid respectively earlier, rinse well with deionized water more afterwards;

2) preparation of oxide layer

In oxidation furnace the SOI substrate is carried out oxidation processes, in positive first oxide layer 3 that forms of substrate, thickness is 0.3 μ m, and reverse side has one deck second oxide layer 4, and thickness is 0.3 μ m;

3) preparation bottom electrode 6

On first oxide layer 3, utilize magnetron sputtering apparatus to prepare the Ti layer of 0.04 μ m thickness and the Pt layer of 0.2 μ m thickness, with formation bottom electrode composite bed, and utilize pattern technology formationization bottom electrode 6; Finish the preparation of bottom electrode 6;

4) preparation piezoelectric film 7

Preparation piezoelectric film PZT on the surface of bottom electrode 6, thickness is 1 μ m;

5) preparation top electrode 9

Resist coating on SOI substrate front, photolithographic exposure forms the top electrode anti-graphics; The Au layer of the Cr of vacuum evaporation 0.04 μ m thickness and 0.1 μ m thickness successively again; Remove photoresist with acetone, finish the preparation of top electrode 9;

6) body silicon etching

The Cr of deposition 0.04 μ m thickness and the Au of 0.1 μ m thickness assist the mask of second oxide layer 4 as the body silicon etching on the surface of second oxide layer 4 at the back side of SOI substrate.Be coated with positive photoresist, utilize the double-sided exposure machine to carry out double-sided exposure, organizator etch mask litho pattern on the SOI substrate back, and order is corroded Au layer, Cr layer, second oxide layer 4, organizator etch mask overleaf; Remove residual photoresist, the preparation of perfect aspect etch mask, when corrosion Au layer, Cr layer, second oxide layer 4, the front will be protected with photoresist, after corroding, removes photoresist;

, put into 35%KOH solution and carry out the body etching SOI substrate sealing and fixing with body etching anchor clamps, during the 3rd oxide layer 12 in etching into SOI, the body silicon etching is finished.Resist coating on the front, the Cr and the Au at the corrosion back side, and remove positive photoresist.

7) the 3rd oxide layer 12 among the etching SOI

To the two-sided resist coating of substrate, and, form the photoresist mask pattern of the 3rd oxide layer 12 center square holes among the etching SOI to back side photolithographic exposure; Utilize the method for dry method or wet method that the 3rd oxide layer 12 among the SOI is carried out etching, after etching is finished, remove on-chip photoresist with acetone.

8) utilize vacuum evaporation equipment or sputtering equipment to prepare the Al supporting layer 11 of 0.5 μ m thickness, the supporting layer during as the etching slit at the reverse side of SOI substrate.Resist coating on the front of SOI substrate, photolithographic exposure forms the required photoresist mask of slit etching;

9) utilize wet etching that first oxide layer 3 is corroded, utilize dry etching that the silicon layer in the SOI substrate 2 is carried out etching, its thickness is 2 μ m, finishes the etching of slit.When utilizing wet etching first oxide layer 3, the back side of SOI substrate will apply photoresist, with the Al supporting layer 11 at the protection back side, after corroding, removes photoresist.After the slit etching is intact, remove positive mask layer simultaneously, the width of slit is 10 μ m.

10) resist coating on the front of SOI substrate (1), photolithographic exposure forms and fills the required mask patterns of slit, utilizes vacuum evaporation equipment to prepare the Al layer of 2.2 μ m thickness, removes photoresist with acetone, and graphical Al layer is finished the filling of slit.

11) preparing thickness in the front of SOI substrate is 0.5 μ m polyimide film, and it is carried out graphically exposing the pressure welding contact of upper/lower electrode.

12) resist coating on the front of SOI substrate, the protective layer in front during as release slit and vibrating membrane.The SOI substrate is put into phosphoric acid corrosion liquid, and the Al layer of corrosion back side Al supporting layer 11 and filling slit discharges slit and vibrating membrane, and removes positive photoresist, finishes preparation of devices.

Embodiment 3, adopt preparation method of the present invention to prepare a novel piezoelectric ultrasonic transducer chip, and its step is as follows:

1) cleans the SOI substrate

2) preparation of oxide layer

3) preparation bottom electrode 6

4) preparation piezoelectric film 7

Preparation piezoelectric film PZT on the surface of bottom electrode 6, thickness is 1.5 μ m;

5) preparation top electrode 9

Resist coating on the substrate one side of piezoelectric film is being arranged, and photolithographic exposure forms the top electrode anti-graphics; The Au layer of the Cr of vacuum evaporation 0.04 μ m thickness and 0.1 μ m thickness successively again; Remove photoresist with acetone, finish the preparation of top electrode 9;

6) body silicon etching

, put into 35%KOH solution and carry out the body etching SOI substrate sealing and fixing with body etching anchor clamps, during the 3rd oxide layer 12 in etching into SOI, the body silicon etching is finished.Discharge square composite membrane vibration fully.Resist coating on the front, the Cr and the Au at the corrosion back side, and remove positive photoresist.

7) the 3rd oxide layer 12 among the etching SOI

8) utilize vacuum evaporation equipment or sputtering equipment to prepare the Al supporting layer 11 of 1.5 μ m thickness, the supporting layer during as the etching slit at the reverse side of SOI substrate.Resist coating on the front of SOI substrate, photolithographic exposure forms the required photoresist mask of slit etching.

9) utilize wet etching that first oxide layer 3 is corroded, utilize dry etching that the silicon layer in the SOI substrate 2 is carried out etching, its thickness is 4 μ m, finishes the etching of slit.When utilizing wet etching first oxide layer 3, the back side of SOI substrate will apply photoresist, with the Al supporting layer 11 at the protection back side, after corroding, removes photoresist.After the slit etching is intact, remove positive mask layer simultaneously, the width of slit is 10 μ m.

11) preparing thickness in the front of SOI substrate is 1 μ m polyimide film, and it is carried out graphically exposing the pressure welding contact of upper/lower electrode.

Embodiment 4, adopt preparation method of the present invention to prepare a novel piezoelectric ultrasonic transducer chip, and its step is as follows:

1) cleans the SOI substrate

2) preparation of oxide layer

In oxidation furnace the SOI substrate is carried out oxidation processes, in positive first oxide layer 3 that forms of substrate, thickness is 0.5 μ m, and reverse side has one deck second oxide layer 4, and thickness is 0.5 μ m;

3) preparation bottom electrode 6

4) preparation piezoelectric film 7

Preparation piezoelectric film PZT on the surface of bottom electrode 6, thickness is 4 μ m;

5) preparation top electrode 9

Resist coating on the substrate one side of piezoelectric film is being arranged, and photolithographic exposure forms the top electrode anti-graphics; Utilize vacuum evaporation equipment to deposit the Al layer of 0.5 μ m thickness again, to form upper electrode layer; Remove photoresist with acetone, finish the preparation of top electrode 9;

6) body silicon etching

7) the 3rd oxide layer 12 among the etching SOI

9) utilize wet etching that first oxide layer 3 is corroded, utilize dry etching that the silicon layer in the SOI substrate 2 is carried out etching, its thickness is 13 μ m, finishes the etching of slit.When utilizing wet etching first oxide layer 3, the back side of SOI substrate will apply photoresist, with the Al supporting layer 11 at the protection back side, after corroding, removes photoresist.After the slit etching is intact, remove positive mask layer simultaneously, the width of slit is 20 μ m.

10) resist coating on the front of SOI substrate, photolithographic exposure forms and fills the required mask patterns of slit, utilizes vacuum evaporation equipment to prepare the ZnO layer of 13.3 μ m thickness, removes photoresist with acetone, and the graphical ZnO layer is finished the filling of slit.

11) preparing thickness in the front of SOI substrate is 0.7 μ m polyimide film, and it is carried out graphically exposing the pressure welding contact of upper/lower electrode.

12) resist coating on the front of SOI substrate, the protective layer in front during as release slit and vibrating membrane.The SOI substrate is put into phosphoric acid corrosion liquid, and the ZnO layer of corrosion back side Al supporting layer 11 and filling slit discharges slit and vibrating membrane, and removes positive photoresist, finishes preparation of devices.

Embodiment 5, adopt preparation method of the present invention to prepare a novel piezoelectric ultrasonic transducer chip, and its step is as follows:

1) cleans the SOI substrate

2) preparation of oxide layer

In oxidation furnace the SOI substrate is carried out oxidation processes, in positive first oxide layer 3 that forms of substrate, thickness is 0.4 μ m, and reverse side has one deck second oxide layer 4, and thickness is 0.4 μ m;

3) preparation bottom electrode 6

On first oxide layer 3, utilize vacuum evaporation equipment to prepare the Cr layer of 0.04 μ m thickness and the Au layer of 0.1 μ m thickness, with formation bottom electrode composite bed, and utilize pattern technology formationization bottom electrode 6; Finish the preparation of bottom electrode 6;

4) preparation piezoelectric film 7

Preparation piezoelectric film ZnO on the surface of bottom electrode 6, thickness is 5 μ m;

5) preparation top electrode 9

Resist coating on the surface of piezoelectric film 7, photolithographic exposure forms the top electrode anti-graphics; The Au layer of the Cr of vacuum evaporation 0.04 μ m thickness and 0.1 μ m thickness successively again; Remove photoresist with acetone, finish the preparation of top electrode 9;

6) body silicon etching

, put into 35%KOH solution and carry out the body etching SOI substrate sealing and fixing with body etching anchor clamps, during the 3rd oxide layer 12 in etching into the SOI substrate, the body silicon etching is finished.Resist coating on the front, the Cr and the Au at the corrosion back side, and remove positive photoresist.

7) the 3rd oxide layer 12 in the etching SOI substrate

To the two-sided resist coating of substrate, and, form the photoresist mask pattern of the 3rd oxide layer 12 center square holes in the etching SOI substrate to back side photolithographic exposure; Utilize the method for dry method or wet method that the 3rd oxide layer 12 in the SOI substrate is carried out etching, after etching is finished, remove on-chip photoresist with acetone.

8) utilize vacuum evaporation equipment or sputtering equipment to prepare the Al supporting layer 11 of 0.5 μ m thickness, the supporting layer during as the etching slit at the reverse side of SOI substrate.Resist coating on the front of SOI substrate, photolithographic exposure forms the required photoresist mask of slit etching.

9) utilize wet etching that first oxide layer 3 is corroded, utilize dry etching that the silicon layer in the SOI substrate 2 is carried out etching, its thickness is 8 μ m, finishes the etching of slit.When utilizing wet etching first oxide layer 3, the back side of SOI substrate will apply photoresist, with the Al supporting layer 11 at the protection back side, after corroding, removes photoresist.After the slit etching is intact, remove positive mask layer simultaneously, the width of slit is 30 μ m.

10) resist coating on the front of SOI substrate, photolithographic exposure forms and fills the required mask patterns of slit, utilizes vacuum evaporation equipment to prepare the Al layer of 8.5 μ m thickness, removes photoresist with acetone, and graphical Al layer is finished the filling of slit.

11) preparing thickness in the front of SOI substrate is 0.8 μ m polyimide film, and it is carried out graphically exposing the pressure welding contact of upper/lower electrode.

Embodiment 6, adopt preparation method of the present invention to prepare a novel piezoelectric ultrasonic transducer chip, and its step is as follows:

1) cleans silicon chip 1

2) form the B diffusion impervious layer by thermal oxidation

On silicon chip 1, utilizing the thermal oxidation furnace oxide thickness is the oxide layer of 1 μ m, and removes positive oxide layer, and forming thickness like this on the reverse side of substrate 1 is the oxidation film layer of 1 μ m;

3) boron diffusion

In diffusion furnace, silicon chip 1 is carried out boron diffusion, carry out oxidation processes after having spread again, form the B silex glass on silicon chip 1 surface, utilize buffered HF to remove the B silex glass on silicon chip 1 surface and the oxide layer of reverse side, the thickness of the final B diffusion silicon layer that forms is 20 μ m.

4) preparation of oxide layer

In oxidation furnace silicon chip 1 is carried out oxidation processes, in positive first oxide layer 3 that forms of substrate, thickness is 1 μ m, and reverse side has one deck second oxide layer 4, and thickness is 1 μ m;

5) preparation bottom electrode 6

On first oxide layer 3, utilize sputtering equipment to deposit the Al layer of 0.5 μ m thickness, with the formation lower electrode layer, and utilize pattern technology formationization bottom electrode 6; Finish the preparation of bottom electrode 6;

6) preparation piezoelectric film 7

Preparation piezoelectric film ZnO on the surface of bottom electrode 6, thickness is 10 μ m;

7) preparation top electrode 9

Resist coating on silicon oxide film protective layer 8 surfaces, photolithographic exposure forms the top electrode anti-graphics; Utilize vacuum evaporation equipment to deposit the Al layer of 0.3 μ m thickness again, to form upper electrode layer; Remove photoresist with acetone, finish the preparation of top electrode 9;

8) body silicon etching

9) utilize vacuum evaporation equipment or sputtering equipment to prepare the Al supporting layer 11 of 1.5 μ m thickness, the supporting layer during as the etching slit at the reverse side of silicon chip 1.Resist coating on the front of silicon chip 1, photolithographic exposure forms the required photoresist mask of slit etching;

10) utilize wet etching that first oxide layer 3 and silicon oxide film protective layer 8 are corroded, utilize dry etching that the silicon layer 2 of B diffusion is carried out etching, finish the etching of slit.When utilizing wet etching first oxide layer 3 and silicon oxide film protective layer 8, the back side of silicon chip 1 will apply photoresist, with the Al supporting layer 11 at the protection back side, after corroding, removes photoresist.After the slit etching is intact, remove positive mask layer simultaneously, the width of slit is 15 μ m.

11) resist coating on the front of silicon chip 1, photolithographic exposure forms and fills the required mask patterns of slit, utilizes vacuum evaporation equipment to prepare the ZnO layer of 21 μ m thickness, removes photoresist with acetone, and the graphical ZnO layer is finished the filling of slit.

12) preparing thickness in the front of silicon chip 1 is 1 μ m polyimide film, and it is carried out graphically exposing the pressure welding contact of upper/lower electrode.

Embodiment 7, adopt preparation method of the present invention to prepare a novel piezoelectric ultrasonic transducer chip, and its step is as follows:

1) cleans the SOI substrate

2) preparation of oxide layer

3) preparation bottom electrode 6

4) preparation piezoelectric film 7

Preparation piezoelectric film PZT on the surface of bottom electrode 6, thickness is 2 μ m;

5) preparation top electrode 9

6) body silicon etching

7) the 3rd oxide layer 12 among the etching SOI

8) utilize vacuum evaporation equipment or sputtering equipment to prepare the Al supporting layer 11 of 1 μ m thickness, the supporting layer during as the etching slit at the reverse side of SOI substrate.Deposit 0.8 μ m Al film in the front of SOI substrate, utilize the graphical Al film of peeling off of method, form the required Al mask of slit etching.

9) utilize wet etching that first oxide layer 3 is corroded, utilize dry etching that the silicon layer in the SOI substrate 2 is carried out etching, its thickness is 8 μ m, finishes the etching of slit.When utilizing wet etching first oxide layer 3 and during the positive mask layer of corrosion, the back side of SOI substrate will apply photoresist, with the Al supporting layer 11 at the protection back side.The photoresist at the back side is removed with acetone, and the width of slit is 30 μ m.

Embodiment 8, adopt preparation method of the present invention to prepare a novel piezoelectric ultrasonic transducer chip, and its step is as follows:

1) cleans silicon chip 1

2) form the B diffusion impervious layer by thermal oxidation

3) boron diffusion

4) preparation of oxide layer

In oxidation furnace silicon chip 1 is carried out oxidation processes, in positive first oxide layer 3 that forms of substrate, thickness is 0.7 μ m, and reverse side has one deck second oxide layer 4, and thickness is 0.7 μ m;

5) preparation bottom electrode 6

6) preparation piezoelectric film 7

Preparation piezoelectric film BaTiO3 on the surface of bottom electrode 6, thickness is 2 μ m;

7) preparation top electrode 9

Resist coating on the substrate one side of piezoelectric film is being arranged, and photolithographic exposure forms the top electrode anti-graphics; The Pt layer of magnetron sputtering 0.2 μ m thickness; Remove photoresist with acetone, finish the preparation of top electrode 9;

8) body silicon etching

9) utilize vacuum evaporation equipment or sputtering equipment to prepare the Al supporting layer 11 of 0.5 μ m thickness, the supporting layer during as the etching slit at the reverse side of silicon chip 1.Deposit 0.5 μ m Al film in the front of silicon chip 1, utilize the graphical Al film of peeling off of method, form the required Al mask of slit etching.

10) utilize wet etching that first oxide layer 3 is corroded, utilize dry etching that the silicon layer 2 of B diffusion is carried out etching, finish the etching of slit.When utilizing wet etching first oxide layer 3 and during the positive mask layer of corrosion, the back side of silicon chip 1 will apply photoresist, with the Al supporting layer 11 at the protection back side.The photoresist at the back side is removed with acetone, and the width of slit is 15 μ m.

Embodiment 9, adopt preparation method of the present invention to prepare a novel piezoelectric ultrasonic transducer chip, and its step is as follows:

1) cleans the SOI substrate

2) preparation of oxide layer

In oxidation furnace the SOI substrate is carried out oxidation processes, in positive first oxide layer 3 that forms of substrate, thickness is 0.2 μ m, and reverse side has one deck second oxide layer 4, and thickness is 0.2 μ m;

3) preparation bottom electrode 6

4) preparation piezoelectric film 7

Preparation piezoelectric film PZT on the surface of bottom electrode 6, thickness is 2.5 μ m;

5) preparation top electrode 9

6) body silicon etching

7) the 3rd oxide layer 12 among the etching SOI

8) utilize vacuum evaporation equipment or sputtering equipment to prepare the Al supporting layer 11 of 1.5 μ m thickness, the supporting layer during as the etching slit at the reverse side of SOI substrate.Deposit 0.5 μ mAl film in the front of SOI substrate, utilize the graphical Al film of peeling off of method, form the required Al mask of slit etching.

9) utilize wet etching that first oxide layer 3 is corroded, utilize dry etching that the silicon layer in the SOI substrate 2 is carried out etching, its thickness is 5 μ m, finishes the etching of slit.When utilizing wet etching first oxide layer 3 and front mask layer, the back side of SOI substrate will apply photoresist, with the Al supporting layer 11 at the protection back side.The photoresist at the back side is removed with acetone, and the width of slit is 5 μ m.

10) resist coating on the front of SOI substrate, photolithographic exposure forms and fills the required mask patterns of slit, utilizes vacuum evaporation equipment to prepare the ZnO layer of 5.8 μ m thickness, removes photoresist with acetone, and the graphical ZnO layer is finished the filling of slit.

11) preparing thickness in the front of SOI substrate is 1.2 μ m polyimide films, and it is carried out graphically exposing the pressure welding contact of upper/lower electrode.

Embodiment 10, adopt preparation method of the present invention to prepare a novel piezoelectric ultrasonic transducer chip, and its step is as follows:

1) cleans silicon chip 1

2) form the B diffusion impervious layer by thermal oxidation

3) boron diffusion

In diffusion furnace, silicon chip 1 is carried out boron diffusion, carry out oxidation processes after having spread again, form the B silex glass on silicon chip 1 surface, utilize buffered HF to remove the B silex glass on silicon chip 1 surface and the oxide layer of reverse side, the thickness of the final B diffusion silicon layer that forms is 15 μ m.

4) preparation of oxide layer

5) preparation bottom electrode 6

On first oxide layer 3, utilize electron-beam coating equipment to prepare the Al layer of 0.3 μ m thickness, with formation bottom electrode composite bed, and utilize pattern technology formationization bottom electrode 6; Finish the preparation of bottom electrode 6;

6) preparation piezoelectric film 7

Preparation piezoelectric film AlN on the surface of bottom electrode 6, thickness is 2 μ m;

7) preparation top electrode 9

Resist coating on the substrate one side of piezoelectric film is being arranged, and photolithographic exposure forms the top electrode anti-graphics; The Al layer of magnetron sputtering 0.3 μ m thickness; Remove photoresist with acetone, finish the preparation of top electrode 9;

8) body silicon etching

9) utilize vacuum evaporation equipment or sputtering equipment to prepare the Al supporting layer 11 of 1.2 μ m thickness, the supporting layer during as the etching slit at the reverse side of silicon chip 1.Resist coating on the front of silicon chip 1, photolithographic exposure forms the required photoresist mask of slit etching;

10) utilize wet etching that first oxide layer 3 is corroded, utilize dry etching that the silicon layer 2 of B diffusion is carried out etching, finish the etching of slit.When utilizing wet etching first oxide layer 3, the back side of silicon chip 1 will apply photoresist, with the Al supporting layer 11 at the protection back side, after corroding, removes photoresist.After the slit etching is intact, remove positive mask layer simultaneously, the width of slit is 25 μ m.

11) resist coating on the front of silicon chip 1, photolithographic exposure forms and fills the required mask patterns of slit, utilizes vacuum evaporation equipment to prepare the ZnO layer of 16.1 μ m thickness, removes photoresist with acetone, and the graphical ZnO layer is finished the filling of slit.

12) preparing thickness in the front of silicon chip 1 is 1.5 μ m polyimide films, and it is carried out graphically exposing the pressure welding contact of upper/lower electrode.

Piezoelectric film 7 also can be organic piezoelectric film in the embodiment of the present invention, as PVDF or other Ca-Ti ore type piezoelectric films.

Claims

1, a kind of soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip, it comprises:

One silicon chip (1); Described silicon chip (1) center is provided with the up-small and down-big square bellmouth that forms by the body etching; Be covered with one deck silicon layer (2) and first oxide layer (3) on described silicon chip (1) front successively, described silicon chip (1) is covered with one deck second oxide layer (4) on the back side; Described second oxide layer (4) center be provided with silicon chip (1) back side on the square hole of square hole same size; Silicon layer (2) and first oxide layer (3) corresponding on the positive upper aperture of described silicon chip (1) are square vibrating membrane, the a pair of opposite side of this square vibrating membrane one of etching respectively runs through the vertical slit (31) of silicon layer (2) and first oxide layer (3), and the vertical projection of described vertical slit (31) is positioned at the inboard, positive upper aperture edge of described silicon chip (1);

Be deposited on the described square vibrating membrane and the graphical bottom electrode (6) that forms; Described bottom electrode (6) is the aluminium bottom electrode with vacuum evaporation equipment or sputtering equipment preparation 0.01～1 μ m thickness, or the compound bottom electrode of Cr/Au for being made of Cr layer and Au layer, or the compound bottom electrode of Ti/Pt for being made of Ti layer and Pt layer; Described Cr layer and Ti layer thickness are 0.01～0.1 μ m; Described Au layer and Pt layer thickness are 0.05～0.5 μ m;

Be deposited on the piezoelectric film (7) that bottom electrode (6) is gone up and graphically formed;

Be deposited on the lip-deep patterned top electrode of described piezoelectric film (7) (9); With

Be deposited on the patterned polyimide film (5) on each parts on described silicon chip (1) upper surface;

The square vibrating membrane and the polyimide film (5) that are etched with vertical slit (31) constitute the anti-sound leakage bridge-type vibrating membrane of soft support jointly.

2, by the described soft support bridge type silicon minute-pressure electricity of claim 1 ultrasonic transducer chip, it is characterized in that, also be included in the 3rd oxide layer (12) between described silicon layer (2) and the silicon chip (1); Described the 3rd oxide layer (12) center be provided with silicon chip (1) front on the square hole of square hole same size; Described the 3rd oxide layer (12) thickness is 0.1～10 μ m.

3, by claim 1 or 2 described soft support bridge type silicon minute-pressure electricity ultrasonic transducer chips, it is characterized in that, also comprise the silicon oxide film protective layer (8) that is deposited between described piezoelectric film (7) and the top electrode (9); Described vertical slit (31) runs through square composite membrane vibration and described silicon oxide film protective layer (8).

4, by the described soft support bridge type silicon minute-pressure electricity of claim 1 ultrasonic transducer chip, it is characterized in that described vertical slit (31) width is 0.1～50 μ m.

5, by the described soft support bridge type silicon minute-pressure electricity of claim 1 ultrasonic transducer chip, it is characterized in that described piezoelectric film (7) is zinc oxide piezoelectric film, aluminium nitride, lead zirconate titanate piezoelectric film, Ca-Ti ore type piezoelectric film or organic piezoelectric film.

6, by claim 1 or 3 described soft support bridge type silicon minute-pressure electricity ultrasonic transducer chips, it is characterized in that described piezoelectric film (7) thickness is 0.1～20 μ m.

7, by the described soft support bridge type silicon minute-pressure electricity of claim 1 ultrasonic transducer chip, it is characterized in that described polyimide film (5) thickness is 0.01～10 μ m.

8, by the described soft support bridge type silicon minute-pressure electricity of claim 1 ultrasonic transducer chip, it is characterized in that described silicon layer (2) thickness is 0.5～100 μ m.

9, by the described soft support bridge type silicon minute-pressure electricity of claim 1 ultrasonic transducer chip, it is characterized in that described first oxide layer (3) thickness is 0.1～5 μ m.

10, the preparation method of the described soft support bridge type silicon minute-pressure electricity of a kind of claim 1 ultrasonic transducer chip, its preparation process is as follows:

Clean substrate

Clean substrate with acidic cleaning solution and alkaline cleaning fluid respectively earlier, rinse well with deionized water more afterwards;

Described substrate is silicon chip or SOI substrate;

1) forms the boron diffusion screen by thermal oxidation

2) silicon layer (2) forms

In diffusion furnace, silicon chip is carried out boron diffusion, carry out oxidation processes after having spread again, the positive silicon layer (2) that forms boron diffusion of silicon chip this moment, utilize the method for oxidation to form the B silex glass, utilize buffered hydrofluoric acid solution to remove the B silex glass and the lower surface oxide layer on silicon chip surface on the silicon chip surface;

3) preparation of oxide layer

In oxidation furnace silicon chip is carried out oxidation processes, in positive first oxide layer (3) that forms of silicon chip, silicon chip back of the body surface forms second oxide layer (4);

4) preparation bottom electrode (6)

In first oxide layer (3) upper surface center, utilize vacuum evaporation equipment or magnetron sputtering apparatus to prepare bottom electrode (6), and graphical; Described bottom electrode (6) is for utilizing the aluminium bottom electrode of vacuum evaporation equipment or sputtering equipment preparation 0.01～1 μ m thickness, or for the compound bottom electrode of Cr/Au that constitutes by Cr layer and Au layer compound, or the compound bottom electrode of Ti/Pt layer for constituting by Ti layer and Pt layer; Described Cr layer and Ti layer thickness are 0.01～0.1 μ m; Described Au layer and Pt layer thickness are 0.05～0.5 μ m;

5) preparation piezoelectric film (7)

On the surface of described bottom electrode (6), prepare piezoelectric film; Be coated with positive photoresist on the surface of piezoelectric film, photolithographic exposure forms the piezoelectric film litho pattern; Corrode piezoelectric film with corrosive liquid, form the piezoelectric film of required figure, remove residual photoresist, finish patterned piezoelectric film (7) preparation;

6) go up directly preparation top electrode (9) at piezoelectric film (7); Perhaps go up preparation silicon oxide film protective layer earlier, on this silicon oxide film protective layer, prepare top electrode (9) again at piezoelectric film (7):

(a) the described top electrode (9) that directly prepares on piezoelectric film (7) is:

Resist coating on the silicon chip front, photolithographic exposure forms the top electrode anti-graphics; Again with vacuum evaporation or magnetron sputtering 0.01～0.1 μ m thickness C r layer and 0.05～0.5 μ m thickness A u layer; Or utilize vacuum evaporation equipment or sputtering equipment preparation 0.01～1 μ m thickness A l or 0.01～1 μ m thickness Pt layer to form the top electrode metallic diaphragm; Remove photoresist with acetone, finish the preparation of top electrode (9);

(b) described going up at piezoelectric film (7) prepares the silicon oxide film protective layer earlier, prepares top electrode (9) again and be on this silicon oxide film protective layer:

Be coated with positive photoresist on silicon oxide film protective layer surface, photolithographic exposure forms the protective layer litho pattern; Utilize high-density plasma etching machine to carry out photoetching corrosion, etchant gas is a sulphur hexafluoride, forms the protective layer figure; Remove residual photoresist, finish the preparation of silicon oxide film protective layer (8);

Resist coating on silicon oxide film protective layer (8) surface, photolithographic exposure forms the top electrode anti-graphics; Again with vacuum evaporation or magnetron sputtering 0.01～0.1 μ m thickness C r layer and 0.05～0.5 μ m thickness A u layer; Or utilize vacuum evaporation equipment or sputtering equipment preparation 0.01～1 μ m thickness A l or 0.01～1 μ m thickness Pt layer to form the top electrode metallic diaphragm; Remove photoresist with acetone, finish the preparation of top electrode (9);

7) body silicon etching

The Au/Cr composite membrane (10) that deposits the Au of the Cr of 0.01～0.1 μ m thickness and 0.05～0.5 μ m thickness on the surface of the oxide layer (4) at the silicon chip back side comes the mask of assisted oxidation layer (4) as the body silicon etching; On Au/Cr composite membrane (10), be coated with positive photoresist, utilize the double-sided exposure machine to carry out double-sided exposure, go up organizator etch mask litho pattern at Au/Cr composite membrane (10), and order is corroded Au layer, Cr layer and oxide layer (4), removal residual photoresist, the preparation of perfect aspect etch mask, when corrosion Au layer, Cr layer and oxide layer (4), the silicon chip front will be protected with photoresist, after corroding, removes photoresist;

, put into 35%KOH solution and carry out the body etching the silicon chip sealing and fixing with body etching anchor clamps, carve silicon chip, when etching boron diffusion silicon, stop etching; Resist coating on the silicon chip front, the Au/Cr film compound (10) at the corrosion silicon chip back side, and remove positive photoresist;

8) preparation Al supporting layer (11)

In the up-small and down-big square bellmouth of silicon chip, utilize the Al supporting layer (11) of vacuum evaporation equipment or sputtering equipment preparation 0.01～10 μ m thickness, the supporting layer during as the etching slit; The mask layer in silicon chip front is photoresist mask layer or Al mask layer during the slit etching; When using photoresist mask layer, resist coating on the silicon chip front then, photolithographic exposure forms the required photoresist mask of slit etching; When using the Al mask layer, then, utilize and peel off or the graphical Al film of corroding method at the positive deposition of silicon chip 0.01～1 μ m Al film, form the required Al mask of slit etching;

9) etching slit

Utilize wet etching that oxide layer (3) and silicon oxide film protective layer (8) are corroded, utilize dry etching that the silicon layer (2) of B diffusion is carried out etching, finish the etching of slit; When utilizing wet etching corrosion oxidation layer (3) and silicon oxide film protective layer (8), the silicon chip back side applies photoresist, with protection Al supporting layer (11); Simultaneously after the slit etching is intact, the mask layer in erosion removal silicon chip front, and remove the photoresist at the silicon chip back side with acetone, the width of slit is 0.1～50 μ m.

10) filling of slit

11) preparation polyimide film (5)

12) release of slit and vibrating membrane

Resist coating on the silicon chip front, the protective layer in front during as release slit and vibrating membrane; Silicon chip is put into corrosive liquid, the Al supporting layer (11) at the corrosion silicon chip back side and be filled in the Al layer or the ZnO layer of slit, discharge slit and vibrating membrane, and remove the photoresist in silicon chip front, finish the preparation of soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip;

1 ') preparation of oxide layer

In oxidation furnace the SOI substrate is carried out oxidation processes, in positive first oxide layer (3) that forms of SOI substrate, the SOI substrate back forms second oxide layer (4);

2 ') preparation bottom electrode (6)

In first oxide layer (3) upper surface center, utilize vacuum evaporation equipment or magnetron sputtering apparatus to prepare bottom electrode (6), and graphical; Described bottom electrode (6) prepares the aluminium bottom electrode of 0.01～1 μ m thickness for utilizing vacuum evaporation equipment or sputtering equipment, or is the compound bottom electrode of Cr/Au that is made of Cr layer and Au layer, or the compound bottom electrode of Ti/Pt for being made of Ti layer and Pt layer; Described Cr layer and Ti layer thickness are 0.01～0.1 μ m; Described Au layer and Pt layer thickness are 0.05～0.5 μ m;

3 ') preparation piezoelectric film (7)

4 ') go up directly preparation top electrode (9) at piezoelectric film (7); Perhaps go up preparation silicon oxide film protective layer earlier, on this silicon oxide film protective layer, prepare top electrode (9) again at piezoelectric film (7):

(a ') described to go up directly at piezoelectric film (7) that preparation top electrode (9) is:

Resist coating on SOI substrate front, photolithographic exposure forms the top electrode anti-graphics; Again with vacuum evaporation or magnetron sputtering 0.01～0.1 μ m thickness C r layer and 0.05～0.5 μ m thickness A u layer; Or utilize vacuum evaporation equipment or sputtering equipment preparation 0.01～1 μ m thickness A l or 0.01～1 μ m thickness Pt layer to form the top electrode metallic diaphragm; Remove photoresist with acetone, finish the preparation of top electrode (9);

(b ') is described to go up preparation silicon oxide film protective layer earlier at piezoelectric film (7), prepares top electrode (9) again and be on this silicon oxide film protective layer:

5 ') body silicon etching

On the surface of second oxide layer (4) of SOI substrate back, deposit the Cr/Au composite membrane (10) that the Au of the Cr of 0.01～0.1 μ m thickness and 0.05～0.5 μ m thickness constitutes and assist the mask of second oxide layer (4) as the body silicon etching; On Cr/Au composite membrane (10), be coated with positive photoresist, utilize the double-sided exposure machine to carry out double-sided exposure, go up organizator etch mask litho pattern at Cr/Au composite membrane (10), and order is corroded Au layer, Cr layer and second oxide layer (4), removal residual photoresist, the preparation of perfect aspect etch mask, when corrosion Au layer, Cr layer and second oxide layer (4), SOI substrate front is protected with photoresist, after corroding, removes photoresist;

, put into 35%KOH solution and carry out the body etching SOI substrate sealing and fixing with body etching anchor clamps, carve the SOI substrate, during thermooxidative layer in etching into the SOI substrate, stop etching; Resist coating on SOI substrate front, the Cr/Au composite membrane of corrosion SOI substrate back, and remove the photoresist in SOI substrate front;

6 ') thermooxidative layer in the etching SOI substrate

7 ') preparation Al supporting layer (11)

Utilize the Al supporting layer (11) of vacuum evaporation equipment or sputtering equipment preparation 0.01～10 μ m thickness, the supporting layer during as the etching slit at the SOI substrate back; The mask layer in SOI substrate front is photoresist mask layer or Al mask layer during the slit etching; When using photoresist mask layer, resist coating on SOI substrate front then, photolithographic exposure forms the required photoresist mask of slit etching; When using the Al mask layer, then, utilize and peel off or the graphical Al film of corroding method at the positive deposition of SOI substrate 0.01～1 μ m Al film, form the required Al mask of slit etching;

8 ') etching slit

Utilize wet etching that first oxide layer (3) and silicon oxide film protective layer (8) are corroded, utilize dry etching that silicon layer in the SOI substrate is carried out etching, finish the etching of slit; When utilizing wet etching to corrode first oxide layer (3) and silicon oxide film protective layer (8), the SOI substrate back applies photoresist, with the Al supporting layer (11) of protection SOI substrate back; Simultaneously after the slit etching is intact, the mask layer in erosion removal SOI substrate front, and remove the photoresist of SOI substrate back with acetone, the width of slit is 0.1～50 μ m;

9 ') filling of slit

10 ') preparation polyimide film (5)

11 ') release of slit and vibrating membrane

Resist coating on SOI substrate front, the protective layer in SOI substrate front during as release slit and square vibrating membrane; The SOI substrate is put into corrosive liquid, the Al supporting layer (11) of corrosion SOI substrate back and be filled in the Al layer or the ZnO layer of slit, discharge slit and square vibrating membrane, and remove the photoresist in SOI substrate front, finish the preparation of soft support bridge type silicon minute-pressure electricity ultrasonic transducer chip.