CN101639726A - Platform-based idle-time processing - Google Patents
Platform-based idle-time processing Download PDFInfo
- Publication number
- CN101639726A CN101639726A CN200910157432A CN200910157432A CN101639726A CN 101639726 A CN101639726 A CN 101639726A CN 200910157432 A CN200910157432 A CN 200910157432A CN 200910157432 A CN200910157432 A CN 200910157432A CN 101639726 A CN101639726 A CN 101639726A
- Authority
- CN
- China
- Prior art keywords
- cpu
- management unit
- operation state
- key operation
- system management
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012545 processing Methods 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 44
- 238000003860 storage Methods 0.000 claims description 51
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 230000000737 periodic effect Effects 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 16
- 230000000694 effects Effects 0.000 abstract description 15
- 230000007704 transition Effects 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 16
- 230000008859 change Effects 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
A system and method for transitions a computing system between operating modes that have different power consumption characteristics. When a system management unit (SMU) determines that the computingsystem is in a low activity state, the SMU transitions the central processing unit (CPU) into a low power operating mode after the CPU stores critical operating state of the CPU in a memory. The SMU then intercepts and processes interrupts intended for the CPU, modifying a copy of the critical operating state. This effectively extends the time during which the CPU stays in lower power mode. When the SMU determines that the computing system exits a low activity state, the copy of the critical operating state is stored in the memory and the SMU transitions the CPU into a high power operating mode using the modified critical operating state.
Description
Technical field
Embodiments of the invention relate generally to the power consumption that reduces the mobile computing platform, relate in particular in core logic dynamic process and interrupt and keep the CPU (central processing unit) (CPU) of computing platform to be in off-position simultaneously.
Background technology
Normally, when having only seldom or not having activity, CPU (central processing unit) (CPU) still is used to handling interrupt.Therefore, when being in idle state activity level when very low, the major part of CPU and Front Side Bus is still switched on and lasting consumed power.Interruption can be upgraded by activity, display renewal or the system clock of input media (such as mouse) and produce.
Therefore, what prior art needed is a kind of like this system and method, this system and method is used for keeping CPU and Front Side Bus with the longer time and with the outage of higher frequency ground, to reduce the computing system power consumption adaptively when system activity seldom or when not having activity.
Summary of the invention
A kind of have that thereby conversion Calculation system between a plurality of operator schemes of different power consumption characteristic prolongs the cpu idle time effectively and the system and method that reduces power consumption.When computing system was in low active state, computing system was switched to low-power operating mode.Under low active state, System Management Unit (SMU) intercepting and processing should be by the interruptions of CPU processing.The key operation state copies that is modified according to need when SMU is stored in handling interrupt.When activity level changed, by the key operation state copies being stored in the storer and upgrading the key operation state of being stored by CPU, SMU was transformed into the high power operation pattern with computing system from low-power operating mode.Yet CPU uses this key operation state copies to recover handling interrupt.
Of the present invention a kind of the various embodiment of the method for conversion Calculation system comprise having between a plurality of operator schemes of different power consumption adaptively: determine that computing system is in low active state and is CPU (central processing unit) (CPU) the start-up system management interrupt (SMI) in the computing system.Then with the key operation state storage of CPU in system storage, and CPU is configured to move under low-power operating mode.System Management Unit (SMU) intercepting and processing should be by the interruptions of CPU processing.
Various embodiment of the present invention comprises and is configured to have between a plurality of operator schemes of different power consumption the computing system of conversion adaptively.Calculation element comprises can be configured to the CPU (central processing unit) of moving (CPU), the local storage that is configured to store the key operation state under low-power operating mode and high power operation pattern, and core logic, this core logic comprises the System Management Unit (SMU) of energy replaced C PU handling interrupt.SMU is configured to when computing system is in low active state to CPU start-up system management interrupt, and to system storage, establishing CPU is at low-power operating mode with the key operation state storage of CPU, and the interruption that should be handled by CPU is handled in intercepting.
Description of drawings
In order at length to understand the above-mentioned feature of the present invention, reference example is done more detailed description to the above-mentioned brief overview of the present invention, embodiment wherein shown in the drawings.But it should be noted that accompanying drawing only shows exemplary embodiments of the present invention, therefore can not be considered to limitation of the present invention, the present invention covers other effective embodiment that is equal to.
Figure 1A and 1B are for implementing the block diagram of the one or more aspects of the present invention configuring computer system;
Fig. 2 A and 2B are respectively the block diagrams of the core logic of the computer system of one or more aspects according to the present invention shown in Figure 1A and the 1B;
Fig. 3 is the process flow diagram of the method step of changing between high-power mode and low-power mode of one or more aspects according to the present invention;
Fig. 4 A, 4B and 4C are the process flow diagrams of the method step that enters low-power mode of one or more aspects according to the present invention;
Fig. 5 is the process flow diagram of the method step that withdraws from low-power mode of one or more aspects according to the present invention;
Fig. 6 is the process flow diagram of the method step of computer system shown in Figure 1A and 1B that starts according to the present invention one or more aspects.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
System survey
Figure 1A is for implementing the block diagram of the one or more aspects of the present invention configuring computer system 100.Computer system 100 is the computing platforms of mixing, and comprises that a plurality of processing units are to provide different activity levels and power consumption levels.Computer system 100 comprises CPU (central processing unit) (CPU) 102 and the system storage 104 that communicates by total thread path, and total thread path comprises core logic 105.Key operation state 160 is stored in the system storage 104.Before being transformed into low-power operating mode, CPU102 stores key operation state 160 in the system storage 104 into.Key operation state 160 can comprise one or more interrupt service routines, need serve the part operation system of interrupting and upgrading cursor position, minimum device driver and current display surface (pixel image data).In some embodiments of the invention, key operation state 160 occupies the 64K byte of system storage 104.
Computer system 100 can be chosen wantonly and comprise graphic process unit (GPU) 112 and voltage regulator 155.GPU 112 is connected in core logic 105 by bus or other communication paths (for example PCI Express, Accelerated Graphics Port or super transmissions links); GPU 112 transmits the graphics subsystem of pixel to display device 110 in one embodiment.Device driver can be stored in the system storage 104, realizes interface between Processing tasks of being carried out by CPU 102 (for example application program) and GPU 112, translates required programmed instruction so that carried out by GPU 112.In key operation state 160, can comprise minimum device driver.When being in low-power operating mode, core logic 105 can be controlled the voltage that is input to GPU 112 by voltage regulator 155 and come GP configuring U 112 to enter off-position.Similarly, core logic 105 can configuration-system storer 104 enters off-position by other voltage regulator (not shown) control input voltages.Core logic 105 also is applied to normal working voltage CPU 102 and GPU 112 respectively again by voltage regulator 150 and 155.
Figure 1B is for implementing another block diagram of the one or more aspects of the present invention configuring computer system 100.Compare with Figure 1A, system storage 104 directly by connecting 103 rather than be connected with CPU 122 by core logic 105, communicate by letter with system storage 104 with CPU 122 by core logic 115 by other devices.
Be understandable that the system that illustrates just schematically can change and revises it here.The connection topological structure be can change as required, the number and the arrangement of bridge comprised.In other selectable topological structures, GPU 112 directly is connected with CPU 122 with CPU 102, rather than is connected with core logic 105 or core logic 115.In other embodiments, core logic 105 or core logic 115 can be distributed in a plurality of chips.Here the specific features that illustrates is chosen wantonly; For example, can support the outer plug-in card or the peripheral hardware of arbitrary number.In certain embodiments, saved switch 116, network adapter 118 directly is connected with core logic 105 or core logic 115 with outer plug-in card 120,121.
GPU 112 is connected too and can changes with system's 100 remainders.In certain embodiments, GPU 112 is embodied as an outer plug-in card, and it can be inserted in the expansion slot of system 100.In other embodiments, GPU 112 energy and core logic 105 or core logic 115 are integrated on the one chip together.In other some other embodiment, some or all assemblies of GPU 112 can be integrated on the one chip together with CPU 102 or CPU 122.
The core logic general introduction
Fig. 2 A is the block diagram of the core logic 105 of the computer system 100 shown in the Figure 1A of one or more aspects according to the present invention.Fig. 2 B is the block diagram of the core logic 115 of the computer system 100 shown in the Figure 1B of one or more aspects according to the present invention.Core logic 105 and core logic 115 include System Management Unit 200, and this System Management Unit 200 can be embedded low-power processor, for example ARM (reduced instruction set computer machine), PowerPC or similarly processor.System Management Unit 200 compares CPU 102 or CPU 122 consumes energy still less, and can be configured to carry out the Processing tasks that at least a portion is carried out by CPU 102 or CPU 122.In a preferred embodiment of the invention, System Management Unit 200 is configured to carry out this part process that need serve system break.
In some embodiments of the invention, core logic 105 comprises the memory interface 214 that is used for system storage 104 interfaces.Because system processing unit 200 and CPU 102 or CPU 122 can be activated, and CPU 102 or CPU 122 can be closed when System Management Unit 200 is enabled, so System Management Unit 200 can provide the processing power of mixing for computer system 100.
Handle standby time
Fig. 3 is the process flow diagram of the method step that one or more aspects are changed between high-power mode and low-power mode according to the present invention.In step 300, computer system 100 is activated, and CPU 102 and core logic 105 are all powered on, and perhaps CPU 122 and core logic 115 are all powered on.The example of boot sequence will describe in conjunction with Fig. 6.
In step 305, computer system 100 operates under the high-power mode.In step 310, System Management Unit 200 determines whether computer system 100 is in low active state.Low active state when being lower than minimum threshold, the frequency that does not have activity or system break just takes place.The system activity timer can be used to determine whether the time-delay between the interruption has constituted low active state.In some embodiments of the invention, operating system determines whether computer system 100 is in low active state.If do not detect low active state in step 310, computer system 100 remains running in high power state in step 305 so.Otherwise as what describe in detail in conjunction with Fig. 4 A, 4B and 4C, computer system 100 enters low-power mode in step 320.
In step 350, System Management Unit 200 determines whether computer system 100 still is in low active state, if computer system 100 is returned step 345 and remained running in low-power mode.Otherwise in step 355, as what describe in detail in conjunction with Fig. 5, computer system 100 withdraws from low-power mode, and returns step 305 to be transformed into high-power mode from low-power mode.Frequency increases or when key operation state copies 260 was not enough to serve the interruption that is intercepted, System Management Unit 200 or operating system can determine that activity level increases, and need be transformed into high-power mode from low-power mode when interrupting.
Fig. 4 A is the process flow diagram of method step of the execution step 320 shown in Figure 3 of one or more aspects according to the present invention.In step 415, System Management Unit start-up system management interrupt (SMI) is given CPU 102 or CPU 122, will be transformed into the low-power operation state to show computer system 100.In step 420, CPU 102 or CPU 122 store current key operation state 160 in the system storage 104 into.When CPU 102 or CPU 122 can store the part of key operation state in the impact damper among CPU 102 or the CPU 122, content in the impact damper is written to system storage 104 (being that impact damper is cleared), is accurate to guarantee current key operation state 160.
In step 425, System Management Unit 200 is by closing voltage regulator 150 and dispose CPU102 or CPU 122 operating in low-power mode.At low-power operating mode, System Management Unit 200 intercepting systems interrupt handling, rather than system break is given to CPU 102 or CPU 122.In step 430, System Management Unit 200 determines whether to receive the system break that is intercepted, and if not, 200 waits of System Management Unit are interrupted with intercepting system.After system break is intercepted, System Management Unit 200 advances to step 435 and determines whether a part of key operation state 160 that needs to handle this interruption is not present in the key operation state 160, if there is no, System Management Unit 220 copies to key operation state copies 260 with at least a portion key operation state 160 in step 440.In a preferred embodiment of the invention, CPU 102 or CPU 122 are configured to key operation state 160 is copied in the local storage 205 and system storage 104 of System Management Unit 200.In other embodiment of the present invention, the part of key operation state 160 is replicated from system storage 104 by System Management Unit 200 on demand.In other embodiment of the present invention, duplicate whole key operation state 160 by System Management Unit 200.Be noted that when 200 of System Management Unit duplicate part key operation state 160 on demand and interrupt to handle each, can repeating step 435 and 440.
As previously mentioned, key operation state 160 comprises that System Management Unit 200 need be in order to the data of disposal system interruption.Key operation state 160 can comprise one or more interrupt service routines, need be in order to serve the part operation system of interrupting and upgrading cursor position, minimum device driver and current display surface.
Fig. 4 B is another process flow diagram of the method step of step 320 in the execution graph 3 of one or more aspects according to the present invention.Step 415 and 420 is carried out according to foregoing mode.In step 422, System Management Unit 200 duplicates key operation state 160 so that key operation state copies 260 is loaded in the local storage 205.Method shown in Fig. 4 B is loaded into key operation state 160 in the local storage 205 on one's own initiative producing key operation state copies 260, rather than has no progeny in intercepting system and duplicate key operation state 160 all or part.Step 425 and 430 is carried out according to foregoing mode.
Fig. 4 C is the another process flow diagram of the method step of step 320 in the execution graph 3 of one or more aspects according to the present invention.Step 415,420,422 and 425 is carried out according to foregoing mode.In step 428, System Management Unit 200 comes configuration-system storer 104 to operate in low-power mode by closing voltage regulator 155.Remove the power consumption that the power supply supply of system storage 104 has been lowered further computer system 100.When computer system 100 when low-power operating mode is transformed into the high power operation pattern, System Management Unit 200 can trigger voltage regulator 155 to recover power supply to system storage 104.Step 430 is carried out according to foregoing mode.
Fig. 5 is the process flow diagram of the method step of step 355 from the low-power operation state exchange to the high power operation state in the execution graph 3 of one or more aspects according to the present invention.In step 555, System Management Unit 200 interrupts showing that computer system 100 no longer is in low active state for itself starting.Arrive system storage 104 to upgrade key operation state 160 in the current key operation state copies 260 of step 560 System Management Unit 200 storages.In step 565, CPU 102 is set System Management Unit 200 or CPU 122 operates in high-power mode.In step 570, CPU 102 or CPU 122 read key operation state 160 and handle in company with the key operation recovering state that upgrades from system storage 104, and the key operation state of this renewal is revised by System Management Unit 200 when handling the interruption of intercepting.
Fig. 6 be in the execution graph 3 of one or more aspects according to the present invention step 300 to start the process flow diagram of the method step of computer system 100 among Figure 1A and the 1B.In step 600, System Management Unit 200 is powered on.In step 605, System Management Unit 200 is that computer system 100 is carried out power-on self-test (POST) function.In usual system, CPU carries out POST by high-performance.Using system administrative unit 200 is carried out POST and has been reduced power consumption.In step 610, CPU 102 or CPU122 are powered on, and in step 620, start-up course is finished.In some embodiments of the invention, step 610 is delayed up to application program and is loaded, to reduce power consumption in start-up course.
In some embodiments of the invention, restriction based on different computing platforms performance and/or power, operating system is given Processing tasks different processing units adaptively and is handled, for example CPU 102 or CPU 122, GPU 122, System Management Unit 200 and low-power GPU 210.When system activity is very low, operating system can start the low-power operation state that is transformed into, and this conversion makes CPU 102 or CPU 122 outages to System Management Unit 200 and in all critical processes by at first shifting critical processes after CPU 102 or CPU 122 have shifted.
Coordinate conversion computer system 100 can prolong the time that computer system 100 relies on the powered battery operation having between a plurality of operator schemes of different power consumption characteristics adaptively.System Management Unit 200 or operating system can determine when that computer system 100 should change between different power modes.Should be in 200 interceptings of low-power mode System Management Unit and processing by the interruption of CPU 102 or CPU 122 processing and the copy of renewal key operation state.When activity level changed, CPU 102 or CPU122 used the key operation state of being revised by System Management Unit 200 to recover handling interrupt.By starting or close the power supply power supply of CPU 102 or CPU 122, System Management Unit 200, GPU 112 and system storage 104, can realize different power consumption levels.
The present invention describes as above with reference to specific embodiment.But, it will be appreciated by persons skilled in the art that according to instruction of the present invention and can also make more kinds of variants and modifications that these variants and modifications are not to still breaking away from the spirit and scope of the present invention that the appended claim of the present invention defines.One embodiment of the present of invention can be implemented as software product to use with computer system.The software definition of software product the function of embodiment (comprising method described herein), and can be included on the different computer readable storage medium.Computer readable storage medium for example can include but not limited to: (i) information can not be rewritten storage medium (for example, driving readable ROM devices such as CD-ROM dish, flash memory, rom chip or other solid state non-volatile semiconductor memory accesses such as CD-ROM in the computing machine) by permanent storage on it; (ii) storage can change the readable storage medium (for example, floppy disk such as disk drive program or hard drive program or other any solid-state random-access semiconductor memory) of information.Correspondingly, the description of front and accompanying drawing should be regarded schematic rather than restrictive.
Claims (10)
1, a kind of adaptively in the method with conversion Calculation system between a plurality of operator schemes of different power consumption, this method comprises:
Determine that described computing system is in low active state;
In described computing system, send system management interrupt to CPU (central processing unit);
The key operation state storage of described CPU (central processing unit) is arrived system storage;
Described CPU (central processing unit) is set is in low-power operating mode; With
Intercepting should be handled by System Management Unit being used for by the interruption of central processing unit for processing.
2, in accordance with the method for claim 1, further may further comprise the steps: the described key operation state of described CPU (central processing unit) is loaded into described System Management Unit from described system storage, to produce the copy of described key operation state, the copy of described key operation state is owing to be modified by described System Management Unit handling interrupt.
3, in accordance with the method for claim 2, further may further comprise the steps:
Determine that described computing system is not in low active state; With
Produce interruption so that described System Management Unit starts the conversion from low-power operating mode to the high power operation pattern by described System Management Unit.
4, in accordance with the method for claim 3, further may further comprise the steps: store the copy of described crucial treatment state into described system storage from described System Management Unit, to upgrade described key operation state.
5, in accordance with the method for claim 4, further may further comprise the steps:
From described system storage, read described key operation state by described CPU (central processing unit); With
Dispose described CPU (central processing unit) and operate in the high power operation pattern.
6, in accordance with the method for claim 1, the described key operation state of wherein said CPU (central processing unit) comprises that display surface, interrupt service routine and a part of operating system are wherein at least a.
7, in accordance with the method for claim 1, further may further comprise the steps:
Determine that the described key operation state of a part that described System Management Unit need be used for handling the described CPU (central processing unit) of interrupting that intercepts is not stored in the described System Management Unit; And
From described system storage with this part key operation state load of described CPU (central processing unit) to described System Management Unit.
8, in accordance with the method for claim 1, come from input media, periodic system renewal and periodically USB (universal serial bus) circulation at least one interruption wherein wherein said should comprising by the interruption that CPU handles.
9, in accordance with the method for claim 1, comprise that further the described system storage of configuration is in the step of low-power operating mode.
10, in accordance with the method for claim 1, before determining that described computing system is in the step of low active state, further may further comprise the steps:
Power on for described System Management Unit; With
Before powering on, carry out and power on and self-check program to described CPU (central processing unit).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/182,074 | 2008-07-29 | ||
US12/182,074 US7779191B2 (en) | 2008-07-29 | 2008-07-29 | Platform-based idle-time processing |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101639726A true CN101639726A (en) | 2010-02-03 |
CN101639726B CN101639726B (en) | 2012-02-01 |
Family
ID=41609552
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2009101574322A Active CN101639726B (en) | 2008-07-29 | 2009-07-29 | Platform-based idle-time processing |
Country Status (5)
Country | Link |
---|---|
US (1) | US7779191B2 (en) |
JP (1) | JP5093620B2 (en) |
KR (1) | KR101078485B1 (en) |
CN (1) | CN101639726B (en) |
TW (1) | TWI405076B (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103914347A (en) * | 2012-12-28 | 2014-07-09 | 联发科技股份有限公司 | Processing system and associated method |
CN103988190A (en) * | 2011-12-16 | 2014-08-13 | 英特尔公司 | Method, apparatus, and system for expanding graphical processing via external display-data i/o port |
CN104102322A (en) * | 2013-04-07 | 2014-10-15 | 索尼公司 | Method and device for prolonging CPU sleep time |
CN104102321A (en) * | 2013-04-07 | 2014-10-15 | 索尼公司 | Method for lowering energy consumption of CPU (Central Processing Unit) |
CN104169879A (en) * | 2012-04-24 | 2014-11-26 | 英特尔公司 | Dynamic interrupt reconfiguration for effective power management |
CN104813254A (en) * | 2012-12-28 | 2015-07-29 | 英特尔公司 | Apparatus and method to manage energy usage of a processor |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003058879A1 (en) | 2002-01-08 | 2003-07-17 | Seven Networks, Inc. | Secure transport for mobile communication network |
US8943347B2 (en) * | 2009-09-09 | 2015-01-27 | Advanced Micro Devices, Inc. | Controlling the power state of an idle processing device |
US8362645B2 (en) * | 2010-03-29 | 2013-01-29 | Intel Corporation | Method to reduce system idle power through system VR output adjustments during S0ix states |
CN102213971B (en) * | 2010-04-09 | 2015-09-09 | 赛恩倍吉科技顾问(深圳)有限公司 | Sequential control circuit and there is the Front Side Bus power supply of this sequential control circuit |
CA2857458A1 (en) | 2010-07-26 | 2012-02-09 | Michael Luna | Mobile application traffic optimization |
CA2806549C (en) | 2010-07-26 | 2014-10-28 | Seven Networks, Inc. | Context aware traffic management for resource conservation in a wireless network |
US8806232B2 (en) * | 2010-09-30 | 2014-08-12 | Apple Inc. | Systems and method for hardware dynamic cache power management via bridge and power manager |
US10817043B2 (en) * | 2011-07-26 | 2020-10-27 | Nvidia Corporation | System and method for entering and exiting sleep mode in a graphics subsystem |
US8707073B2 (en) | 2011-08-31 | 2014-04-22 | International Business Machines Corporation | Energy-efficient polling loop |
US8810584B2 (en) | 2011-09-13 | 2014-08-19 | Nvidia Corporation | Smart power management in graphics processing unit (GPU) based cluster computing during predictably occurring idle time |
US9329658B2 (en) * | 2012-12-28 | 2016-05-03 | Intel Corporation | Block-level sleep logic |
US10540292B2 (en) * | 2016-06-08 | 2020-01-21 | Google Llc | TLB shootdowns for low overhead |
KR102631245B1 (en) * | 2016-11-16 | 2024-01-29 | 매직 립, 인코포레이티드 | Mixed reality system with reduced power rendering |
US10963036B2 (en) | 2018-04-16 | 2021-03-30 | Nxp Usa, Inc. | Idle loop detection and control for processors |
CN111077976B (en) * | 2018-10-18 | 2021-07-20 | 珠海全志科技股份有限公司 | Method for realizing idle state low power consumption mode of multi-core processor and processor |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5537656A (en) * | 1994-06-17 | 1996-07-16 | Intel Corporation | Method and apparatus for a microprocessor to enter and exit a reduced power consumption state |
US6105142A (en) * | 1997-02-11 | 2000-08-15 | Vlsi Technology, Inc. | Intelligent power management interface for computer system hardware |
TW509843B (en) * | 1998-07-24 | 2002-11-11 | Mitac Technology Corp | Control method and system for dynamically adjusting processor |
US6711691B1 (en) * | 1999-05-13 | 2004-03-23 | Apple Computer, Inc. | Power management for computer systems |
US6772241B1 (en) * | 2000-09-29 | 2004-08-03 | Intel Corporation | Selective interrupt delivery to multiple processors having independent operating systems |
US6986066B2 (en) * | 2001-01-05 | 2006-01-10 | International Business Machines Corporation | Computer system having low energy consumption |
TW541453B (en) * | 2001-12-27 | 2003-07-11 | Asustek Comp Inc | Power saving device for computer and method thereof |
US7191349B2 (en) * | 2002-12-26 | 2007-03-13 | Intel Corporation | Mechanism for processor power state aware distribution of lowest priority interrupt |
US7240228B2 (en) * | 2003-05-05 | 2007-07-03 | Microsoft Corporation | Method and system for standby auxiliary processing of information for a computing device |
US7363411B2 (en) * | 2003-10-06 | 2008-04-22 | Intel Corporation | Efficient system management synchronization and memory allocation |
TWI258083B (en) * | 2003-11-20 | 2006-07-11 | Via Tech Inc | Interrupt signal control system and control method |
US7730335B2 (en) * | 2004-06-10 | 2010-06-01 | Marvell World Trade Ltd. | Low power computer with main and auxiliary processors |
US7664970B2 (en) * | 2005-12-30 | 2010-02-16 | Intel Corporation | Method and apparatus for a zero voltage processor sleep state |
JP2006221381A (en) * | 2005-02-09 | 2006-08-24 | Sharp Corp | Processor system and image forming device provided with this processor system |
WO2007026405A1 (en) * | 2005-08-30 | 2007-03-08 | Fujitsu Limited | Information processor for measuring operating time |
US7496770B2 (en) * | 2005-09-30 | 2009-02-24 | Broadcom Corporation | Power-efficient technique for invoking a co-processor |
US20080082710A1 (en) * | 2006-09-29 | 2008-04-03 | Dell Products L.P. | System and method for managing system management interrupts in a multiprocessor computer system |
GB2455744B (en) * | 2007-12-19 | 2012-03-14 | Advanced Risc Mach Ltd | Hardware driven processor state storage prior to entering a low power mode |
US7962771B2 (en) * | 2007-12-31 | 2011-06-14 | Intel Corporation | Method, system, and apparatus for rerouting interrupts in a multi-core processor |
-
2008
- 2008-07-29 US US12/182,074 patent/US7779191B2/en active Active
-
2009
- 2009-07-21 JP JP2009170148A patent/JP5093620B2/en active Active
- 2009-07-28 TW TW098125308A patent/TWI405076B/en active
- 2009-07-29 CN CN2009101574322A patent/CN101639726B/en active Active
- 2009-07-29 KR KR1020090069656A patent/KR101078485B1/en active IP Right Grant
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103988190A (en) * | 2011-12-16 | 2014-08-13 | 英特尔公司 | Method, apparatus, and system for expanding graphical processing via external display-data i/o port |
CN104169879A (en) * | 2012-04-24 | 2014-11-26 | 英特尔公司 | Dynamic interrupt reconfiguration for effective power management |
CN104169879B (en) * | 2012-04-24 | 2019-01-04 | 英特尔公司 | For dynamically interrupting the method and computer system that reconfigure |
US10990407B2 (en) | 2012-04-24 | 2021-04-27 | Intel Corporation | Dynamic interrupt reconfiguration for effective power management |
CN103914347A (en) * | 2012-12-28 | 2014-07-09 | 联发科技股份有限公司 | Processing system and associated method |
CN104813254A (en) * | 2012-12-28 | 2015-07-29 | 英特尔公司 | Apparatus and method to manage energy usage of a processor |
CN104813254B (en) * | 2012-12-28 | 2018-09-21 | 英特尔公司 | The device and method that energy for management processor uses |
CN104102322A (en) * | 2013-04-07 | 2014-10-15 | 索尼公司 | Method and device for prolonging CPU sleep time |
CN104102321A (en) * | 2013-04-07 | 2014-10-15 | 索尼公司 | Method for lowering energy consumption of CPU (Central Processing Unit) |
CN104102321B (en) * | 2013-04-07 | 2018-06-26 | 索尼公司 | The method for reducing CPU energy consumptions |
CN104102322B (en) * | 2013-04-07 | 2018-08-03 | 索尼公司 | Extend the method and device of CPU sleeping times |
Also Published As
Publication number | Publication date |
---|---|
KR101078485B1 (en) | 2011-10-31 |
CN101639726B (en) | 2012-02-01 |
JP5093620B2 (en) | 2012-12-12 |
US7779191B2 (en) | 2010-08-17 |
US20100031071A1 (en) | 2010-02-04 |
TW201011526A (en) | 2010-03-16 |
KR20100012846A (en) | 2010-02-08 |
JP2010061644A (en) | 2010-03-18 |
TWI405076B (en) | 2013-08-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101639726B (en) | Platform-based idle-time processing | |
US7117377B2 (en) | Computer apparatus, power supply control method and program for reducing the standby power requirement in a computer supporting a wake-up function | |
KR100352045B1 (en) | Methods and apparatus for reducing power consumption in computer systems | |
KR100396460B1 (en) | Information handling system with suspend/resume operation | |
CN100489785C (en) | Methods and arrangements for dynamically activating processors | |
US8327173B2 (en) | Integrated circuit device core power down independent of peripheral device operation | |
CN109739563B (en) | Terminal control method, device, system and storage medium | |
KR101519082B1 (en) | Sleep processor | |
JP3301064B2 (en) | Low power mode computer | |
KR100368079B1 (en) | Computer and power control method for computer | |
JP3974510B2 (en) | Computer apparatus, power management method, and program | |
CN102053857A (en) | Apparatus for managing a running virtual machine and switching method thereof | |
CN101373433A (en) | Method for updating BIOS and computer and system using the same | |
TW200422819A (en) | Method and apparatus for controlling a data processing system during debug | |
WO2014199678A1 (en) | Configuration control system and configuration control method | |
CN101943941A (en) | Method for controlling power on a computer system having a network device and a wakeup function | |
CN107122316B (en) | SOC power supply method and SOC | |
JP2002099502A (en) | Computer system and control method for data transfer | |
CN102810007B (en) | A kind of computer mode conversion method, device and computing machine | |
CN111124094A (en) | Server hard disk power-on and power-off control method, control device and control equipment | |
CN102301307B (en) | Distributed Table-driven Power Mode Computation For Controlling Optimal Clock And Voltage Switching | |
CN102141920B (en) | Method for dynamically configuring C-State and communication equipment | |
US11579876B2 (en) | Reducing save restore latency for power control based on write signals | |
US20230004400A1 (en) | System and method for providing system level sleep state power savings | |
US20220207813A1 (en) | Graphics processing units with power management and latency reduction |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |