CN101634783B - Pixel structure of liquid crystal display panel of thin film transistor and manufacturing method - Google Patents
Pixel structure of liquid crystal display panel of thin film transistor and manufacturing method Download PDFInfo
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Abstract
The invention discloses a pixel structure of a liquid crystal display panel of a thin film transistor, which comprises a substrate, a grid scanning line, a grid electrode, a grid insulating layer, an active layer, source and drain electrodes, a data scanning line, a semiconductor layer, a passivation layer and pixel electrodes, wherein the grid scanning line and the grid electrode are formed on the substrate; the grid insulating layer is formed on the grid scanning line and the grid electrode; the active layer is formed on the grid insulating layer; the source and drain electrodes are formed on the active layer, and the data scanning line is formed on the grid insulating layer and is not interconnected with the active layer under the source and drain electrodes; the semiconductor layer is formed above the source and drain electrodes and the grid insulating layer, and covers a part of drain electrode and a part of grid insulating layer; the passivation layer is formed on the semiconductor layer; and the pixel electrodes are formed above the passivation layer, the drain electrode and the grid insulating layer. The invention simultaneously discloses a manufacturing method for the pixel structure of the liquid crystal display panel of the thin film transistor. The pixel structure and the manufacturing method can avoid the problems of short circuit of the source and drain electrodes, open circuit of a channel and the like, and improve the yield of array substrates.
Description
Technical field
The present invention relates to thin film transistor (TFT) (TFT) display panels (LCD) manufacturing technology, relate in particular to pixel structure of liquid crystal display panel of thin film transistor and manufacture method thereof.
Background technology
At present, the world has entered the information revolution epoch, and display technique and display device have occupied crucial status in the evolution of infotech.Wherein, flat pannel display has become the direction of display technique development owing to have little, radiationless, the advantage such as do not glimmer of in light weight, thin thickness, volume.In flat panel display, display panels has characteristics low in energy consumption, that manufacturing cost is relatively low, radiationless because of it, has occupied leading position in panel display board market.
Shown in Fig. 1 a and Fig. 1 b the single dot structure vertical view of display panels of present main flow and the schematic cross-section at A-A position thereof.Shown in Fig. 1 a and Fig. 1 b, be formed with controlling grid scan line 11 (not shown among Fig. 1 b) and gate electrode 12 on the substrate 01, in dot structure, the semiconductor regions between the source-drain electrode is called channel region; Substrate 01 is not formed with gate insulator 21 on the part of controlling grid scan line 11 and gate electrode 12 coverings and the gate electrode 12; Be positioned on the part of grid pole insulation course 21 of gate electrode 12 tops, be formed with amorphous silicon and doped amorphous silicon layer 22; Form active electrode 31 and drain electrode 32 on portion of amorphous silicon and the doped amorphous silicon layer 22 and on the part of grid pole insulation course 21; The part that amorphous silicon and doped amorphous silicon layer 22 are not covered by source electrode 31, drain electrode 32, gate insulator 21 by on the part and most source electrode 31 and drain electrode 32 of source electrode 31 and drain electrode 32 coverings, are not formed with passivation layer 43; Passivation layer via hole 42 is formed on the drain electrode; Be formed with pixel electrode 51 on the passivation layer 43.
For above-mentioned dot structure, manufacture method of the prior art can be used 4 masking process of tradition, and concrete steps are:
Steps A: deposition gate metal layer film on substrate 01, and, form controlling grid scan line 11 and gate electrode 12 figures by composition technology.
Wherein, described composition technology comprises: mask plate mask, exposure, development, etching and technology such as peel off.
Step B: deposition gate insulator layer film on the substrate 01 of completing steps A forms gate insulator 21; Afterwards, the source-drain electrode layer film at deposition of amorphous silicon and doped amorphous silicon layer film and source electrode 31 and drain electrode 32 places again, form amorphous silicon and doped amorphous silicon layer 22, source electrode 31, drain electrode 32 and data scanning line 33 figures by composition technology again, wherein the mask that adopted of composition technology is intermediate tone mask version or gray tone mask.
Step C: deposit passivation layer film on the substrate 01 of completing steps B, and form passivation layer 43 figures, comprise passivation layer via hole 42 by composition technology.
Step D: deposit transparent pixel electrode layer film on the substrate 01 of completing steps C forms transparent pixels electrode 51 figures by composition technology.
According to the description of above dot structure and manufacture method thereof as can be known, when in step B, forming source electrode and drain electrode, owing to used intermediate tone mask or gray tone masking process, be easy to produce the residual and source-drain electrode layer metal residual of doped amorphous silicon layer at the raceway groove place, thereby cause the source-drain electrode short circuit; Perhaps, be easy to generate amorphous silicon layer at the raceway groove place and spend quarter, and cause pixel bad phenomenon such as raceway groove open circuit.The problems referred to above also can have a strong impact on the yields of array base palte.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of pixel structure of liquid crystal display panel of thin film transistor and manufacture method thereof, can avoid problems such as source-drain electrode short circuit, raceway groove open circuit, and then improves the yields of array base palte.
For achieving the above object, technical scheme of the present invention is achieved in that
The invention provides a kind of pixel structure of liquid crystal display panel of thin film transistor, comprising:
Substrate;
Controlling grid scan line and gate electrode are formed on the described substrate;
Gate insulator is formed at described substrate not by on part, described controlling grid scan line and the gate electrode of described controlling grid scan line and the covering of described gate electrode;
Active layer is formed on the described gate insulator of part;
Source electrode, drain electrode and data scanning line, wherein said source electrode, described drain electrode and described data scanning are linear to be formed on the described active layer, and described source electrode, drain electrode and lay respectively at described source electrode and do not link to each other mutually with active layer under the drain electrode;
Semiconductor layer is formed on the part that the described gate insulator between described source electrode and the described drain electrode do not cover by described active layer and on described source electrode and the described drain electrode of part;
Passivation layer is formed on the described semiconductor layer;
Pixel electrode is on the described drain electrode that be formed on the described passivation layer of part, is not covered by described semiconductor layer and not on the described gate insulator that is covered by described active layer.
Wherein, described active layer is the individual layer that doped amorphous silicon constitutes; Perhaps, described active layer is the composite bed that amorphous silicon layer and doped amorphous silicon layer constitute.
Described gate electrode, controlling grid scan line, data scanning line, source electrode and electric leakage be very: individual layer or composite bed that individual layer that one of aluminium, chromium, tungsten, tantalum, titanium, molybdenum and aluminium nickel constitute or above-mentioned metal material combination in any constitute.
The material of pixel electrode is: tin indium oxide or aluminum zinc oxide.
The material of gate insulator and passivation layer is: silicon nitride or silicon oxynitride.
The present invention provides a kind of manufacture method of pixel structure of liquid crystal display panel of thin film transistor simultaneously, and this method comprises:
A1, on substrate deposition gate metal layer film, form controlling grid scan line and gate electrode figure by composition technology;
B1, on the substrate of completing steps A1, deposit gate insulator layer film, active layer film and source-drain electrode layer film successively, form data scanning line, source electrode, drain electrode and active layer figure by composition technology, and, in described composition technology, be etched away at the active layer at raceway groove place;
C1, on the substrate of completing steps B1, deposited semiconductor layer film and passivation layer film successively form passivation layer and semiconductor layer by composition technology;
D1, on the substrate of completing steps C1, pixel deposition electrode layer film forms pixel electrode by composition technology.
Wherein, described formation data scanning line, source electrode, drain electrode and active layer are specially: adopt common mask that source-drain electrode layer film and active layer film are carried out mask, form data scanning line, source electrode, drain electrode and active layer figure by composition technology.
The present invention provides the manufacture method of another kind of pixel structure of liquid crystal display panel of thin film transistor simultaneously, and this method comprises:
A2, on substrate deposition gate metal film, form controlling grid scan line and gate electrode figure by composition technology;
B2, on the substrate of completing steps A2, deposit gate insulator layer film, active layer film and source-drain electrode layer film successively, form data scanning line, source electrode, drain electrode and active layer figure by composition technology, and, in described composition technology, be etched away at the active layer at raceway groove place;
C2, on the substrate of completing steps B2, deposited semiconductor layer film and passivation layer film successively by mask mask, exposure, development, etching technics, form the figure that keeps unexposed photoresist;
D2, on the substrate of completing steps C2, pixel deposition electrode layer film by peeling off described unexposed photoresist, forms semiconductor layer, pixel electrode figure.
Pixel structure of liquid crystal display panel of thin film transistor provided by the present invention and manufacture method thereof, when forming source-drain electrode, carry out photoetching process by common mask mode, to guarantee that source-drain electrode layer film, the active layer film etching at raceway groove place is clean, do not have residual; At this moment, since on the gate insulator at raceway groove place without any material, therefore, need deposit the layer of semiconductor layer film again, to guarantee the characteristic of semiconductor at raceway groove place, thereby fundamentally solve the raceway groove place owing to use intermediate tone mask or gray tone mask mode when carrying out photoetching process, exist the source-drain electrode layer residual or doped amorphous silicon layer is residual or amorphous silicon layer is crossed problems such as quarter, avoid the generation of situations such as source-drain electrode short circuit that the problems referred to above cause or raceway groove open circuit, improved the yields of array base palte.
Description of drawings
Fig. 1 a is a single dot structure vertical view on the prior art liquid crystal display panel array substrate;
Fig. 1 b is the A-A part cross sectional representation of Fig. 1 a;
Fig. 2 is single dot structure vertical view on the liquid crystal display panel array substrate of the present invention;
Fig. 3 is the A-A part cross sectional representation of Fig. 2;
Fig. 4 a is the cross sectional representation at the thin film transistor (TFT) position behind formation controlling grid scan line and the gate electrode;
Fig. 4 b is for depositing the cross sectional representation at gate insulator, active layer and source-drain electrode layer thin film transistor (TFT) position afterwards successively;
Fig. 4 c etches away the source-drain electrode layer at raceway groove place and the cross sectional representation at the thin film transistor (TFT) position after the active layer;
Fig. 4 d is that cross sectional representation is located in the source-drain electrode layer and the active layer gate electrode polar curve zone (Gate Pad) afterwards that etch away the raceway groove place;
Fig. 4 e is that cross sectional representation is located in the source-drain electrode layer and the active layer data scanning line polar curve zone (Data Pad) afterwards that etch away the raceway groove place;
Fig. 4 f is the cross sectional representation at the thin film transistor (TFT) position after the depositing semiconductor layers;
Fig. 4 g is the cross sectional representation at the thin film transistor (TFT) position after the deposit passivation layer;
Fig. 4 h etches away the passivation layer of pixel region and the cross sectional representation at the thin film transistor (TFT) position after the semiconductor layer;
Fig. 4 i is for forming the cross sectional representation at pixel electrode thin film transistor (TFT) position afterwards;
Fig. 5 a is for forming the cross sectional representation at the figure thin film transistor (TFT) position afterwards that keeps unexposed photoresist;
Fig. 5 b is for forming the cross sectional representation at pixel electrode thin film transistor (TFT) position afterwards.
Reference numeral: 01, substrate; 11, controlling grid scan line; 12, gate electrode; 21, gate insulator; 22, amorphous silicon and doped amorphous silicon layer; 23, semiconductor layer film; 24, active layer film; 25, active layer; 26, semiconductor layer 30, source-drain electrode layer film; 31, source electrode; 32, drain electrode; 33, data scanning line; 41, passivation layer film; 42, passivation layer via hole; 43, passivation layer; 51, pixel electrode; 52, photoresist layer.
Embodiment
Basic thought of the present invention is: when forming source-drain electrode, carry out photoetching process by common mask (Full Tone Mask) mode, and to guarantee that source-drain electrode layer film, the active layer film etching at raceway groove place is clean, do not have residual; Afterwards, on source electrode and part drain electrode and the raceway groove place deposit the layer of semiconductor layer film again, to guarantee the characteristic of semiconductor at raceway groove place.
Below, be described with reference to the accompanying drawings the realization of pixel structure of liquid crystal display panel of thin film transistor of the present invention and manufacture method thereof by specific embodiment.
Fig. 2 is single dot structure vertical view on the liquid crystal display panel array substrate among the present invention, and Fig. 3 is the A-A part cross sectional representation of Fig. 2, as shown in Figures 2 and 3, is formed with controlling grid scan line 11 (not shown among Fig. 3) and gate electrode 12 on the substrate 01; Substrate 01 is not formed with gate insulator 21 on part, controlling grid scan line 11 and the gate electrode 12 of controlling grid scan line 11 and gate electrode 12 coverings; Be formed with active layer 25 on the part of grid pole insulation course 21; Form active electrode 31, drain electrode 32 and data scanning line 33 (not shown among Fig. 3) on the described active layer 25, source electrode 31, drain electrode 32 and lay respectively at source electrode 31 and be not connected mutually with active layer 25 under the drain electrode 32; Be formed with semiconductor layer 26 on the part that gate insulator 21 between source electrode 31 and the drain electrode 32 is not covered by active layer 25 and source electrode 31 and the part drain electrode 32, this semiconductor layer 26 has guaranteed the characteristic of semiconductor of channel region; On semiconductor layer 26, be formed with passivation layer 43; On the drain electrode 32 that on the part passivation layer 43, is not covered by semiconductor layer 26 and be not formed with pixel electrode 51 on the gate insulator 21 that is covered by active layer 25, wherein, the part that pixel electrode 51 is connected with drain electrode 32 can be finished the function of passivation layer via hole, can regard the passivation layer via hole 42 in the dot structure of the present invention as.By above description in conjunction with the accompanying drawings 3 as can be known, be formed with semiconductor layer 26 and passivation layer 43 between described unconnected source electrode 31 and the drain electrode 32 and between unconnected active layer 25.
In addition, active layer 25 can be the individual layer of doped amorphous silicon formation, also can be the composite bed that amorphous silicon and doped amorphous silicon constitute.
Described gate electrode 12, controlling grid scan line 11, data scanning line 33, source electrode 31, drain electrode 32 are generally the individual layer of one of aluminium, chromium, tungsten, tantalum, titanium, molybdenum and aluminium nickel formation or individual layer or the composite bed that above-mentioned metal material combination in any constitutes.
The material of pixel electrode 51 is generally: transparent electrode materials such as tin indium oxide or aluminum zinc oxide.
The material of gate insulator 21 and passivation layer 43 is generally: silicon nitride or silicon oxynitride.
Above-mentioned dot structure is the basic structure that specific embodiments of the invention provide, and can carry out the variation of further structure on basis of the present invention, is used for forming memory capacitance on the controlling grid scan line such as pixel electrode part is overlapped on; Also can shield bars be set at the periphery of pixel electrode; Or further on substrate, form public electrode, and form memory capacitance etc. by public electrode.
Above-mentioned dot structure can be manufactured by the following method and form, and this manufacture method is specially:
Steps A 1: deposition gate metal layer film on substrate 01 forms controlling grid scan line 11 and gate electrode 12 figures by composition technology.
Wherein, described composition technology comprises: mask mask, exposure, development, etching and technology such as peel off.
Wherein, can adopt metal deposition deposition gate metal films such as physical sputtering method, shown in Fig. 4 a.
Wherein, how to carry out the metal deposition, how to use described composition technology all to belong to known technology, repeat no more here by the physical sputtering method.
Step B1: deposition gate insulator layer film on the substrate 01 of completing steps A1 forms gate insulator 21; Deposit active layer film 24 afterwards, sedimentary origin drain electrode layer film 30 again, form data scanning line 33, source electrode 31, drain electrode 32 and active layer 25 figures by composition technology, wherein, the etching technics etching source-drain electrode layer film 30 of composition technology and the active layer film 24 of below.
Wherein, can adopt deposition gate insulator layer film, active layer films 24 such as chemical gaseous phase depositing process; Can adopt physical sputtering method sedimentary origin drain electrode layer film 30, shown in Fig. 4 b.
Wherein, how deposit and belong to known technology, repeat no more here by chemical gaseous phase depositing process.
Wherein, composition technology does not adopt gray tone mask of the prior art or intermediate tone mask, and adopts common mask mode that source-drain electrode layer film 30 and active layer film 24 are carried out mask; By exposure, development, etching and composition technology such as peel off and form data scanning line 33, source electrode 31, drain electrode 32 and active layer 25 figures, and when carrying out etching technics, the active layer film 24 of etching source-drain electrode layer film 30 and below.The corresponding region is a channel region between source electrode 31 and the drain electrode 32.Shown in Fig. 4 c.In addition, finish this step after, the cross-sectional view of gate electrode polar curve location is shown in Fig. 4 d on the array base palte, the cross sectional representation of data scanning line polar curve location is shown in Fig. 4 e.
Wherein, above-mentioned etching technics can be wet-etching technology or dry etch process.
Step D1: on the substrate 01 of completing steps C1, deposited semiconductor layer film 23 and passivation layer film 41 successively.
Wherein, can adopt chemical gaseous phase depositing process deposited semiconductor layer film 23 and passivation layer film 41, as Fig. 4 f, shown in Fig. 4 g.
Step F 1: on the substrate 01 of completing steps E1, form passivation layer 43 and semiconductor layer 26 figures by composition technology, shown in Fig. 4 h.
Step G1: on the substrate 01 of completing steps F1, pixel deposition electrode layer film, and by composition technology formation pixel electrode 51 figures.
In this step, on the substrate 01 of completing steps F1, adopt physical sputtering method pixel deposition electrode layer film, and form pixel electrode 51 figures by composition technology.Finish film crystal tube portion cross sectional representation after this step shown in Fig. 4 i.
Wherein, the part that pixel electrode 51 is connected with drain electrode 32 can be finished the function of passivation layer via hole, can regard the passivation layer via hole 42 in the dot structure of the present invention as.
Below, will introduce the manufacture method of another kind of pixel structure of liquid crystal display panel of thin film transistor in detail, this method comprises:
Steps A 2: deposition gate metal film on substrate 01 forms controlling grid scan line 11 and gate electrode figure 12 figures by composition technology.
Step B2: on the substrate 01 of completing steps A2, deposit gate insulator layer film, active layer film 24 and source-drain electrode layer film 30 successively, form data scanning line 33, source electrode 31, drain electrode 32 and active layer 25 figures by composition technology, and, in described composition technology, be etched away at the active layer film 24 at raceway groove place;
Steps A 2～B2 is identical with the disposal route of steps A 1～C1, repeats no more here.
Step C2: on the substrate of completing steps B2, deposited semiconductor layer film and passivation layer film by technologies such as mask mask, exposure, development, etchings, form the figure that keeps unexposed photoresist successively.
Finishing in the film crystal tube portion cross sectional representation after this step shown in Fig. 5 a on the passivation layer 43, remains with photoresist layer 52.
Step D2: on the substrate of completing steps C2, pixel deposition electrode layer film by peeling off described unexposed photoresist layer 52, forms semiconductor layer 26 and passivation level pixel electrode 51 figures.
Finish this step film crystal tube portion cross sectional representation afterwards shown in Fig. 5 b.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.
Claims (8)
1. a pixel structure of liquid crystal display panel of thin film transistor is characterized in that, comprising:
Substrate;
Controlling grid scan line and gate electrode are formed on the described substrate;
Gate insulator is formed at described substrate not by on part, described controlling grid scan line and the gate electrode of described controlling grid scan line and the covering of described gate electrode;
Active layer is formed on the described gate insulator of part;
Source electrode, drain electrode and data scanning line, wherein said source electrode, described drain electrode and described data scanning are linear to be formed on the described active layer, and described source electrode, drain electrode and lay respectively at described source electrode and do not link to each other mutually with active layer under the drain electrode;
Semiconductor layer is formed on the part that the described gate insulator between described source electrode and the described drain electrode do not cover by described active layer and on described source electrode and the described drain electrode of part;
Passivation layer is formed on the described semiconductor layer;
Pixel electrode is on the described drain electrode that be formed on the described passivation layer of part, is not covered by described semiconductor layer and not on the described gate insulator that is covered by described active layer.
2. dot structure according to claim 1 is characterized in that, described active layer is the individual layer that doped amorphous silicon constitutes; Perhaps, described active layer is the composite bed that amorphous silicon layer and doped amorphous silicon layer constitute.
3. dot structure according to claim 1 and 2, it is characterized in that, described gate electrode, controlling grid scan line, data scanning line, source electrode and electric leakage very: individual layer or composite bed that individual layer that one of aluminium, chromium, tungsten, tantalum, titanium, molybdenum and aluminium nickel constitute or above-mentioned metal material combination in any constitute.
4. dot structure according to claim 1 and 2 is characterized in that, the material of described pixel electrode is: tin indium oxide or aluminum zinc oxide.
5. dot structure according to claim 1 and 2 is characterized in that, the material of described gate insulator and passivation layer is: silicon nitride or silicon oxynitride.
6. the manufacture method of a pixel structure of liquid crystal display panel of thin film transistor is characterized in that, this method comprises:
A1, on substrate deposition gate metal layer film, form controlling grid scan line and gate electrode figure by composition technology;
B1, on the substrate of completing steps A1, deposit gate insulator layer film, active layer film and source-drain electrode layer film successively, form data scanning line, source electrode, drain electrode and active layer figure by composition technology, and, in described composition technology, be etched away at the active layer at raceway groove place;
C1, on the substrate of completing steps B1, deposited semiconductor layer film and passivation layer film successively form passivation layer and semiconductor layer figure by composition technology;
D1, on the substrate of completing steps C1, pixel deposition electrode layer film forms pixel electrode by composition technology.
7. manufacture method according to claim 6, it is characterized in that, described formation data scanning line, source electrode, drain electrode and active layer are specially: adopt common mask that source-drain electrode layer film and active layer film are carried out mask, form data scanning line, source electrode, drain electrode and active layer figure by composition technology.
8. the manufacture method of a pixel structure of liquid crystal display panel of thin film transistor is characterized in that, this method comprises:
A2, on substrate deposition gate metal film, form controlling grid scan line and gate electrode figure by composition technology;
B2, on the substrate of completing steps A2, deposit gate insulator layer film, active layer film and source-drain electrode layer film successively, form data scanning line, source electrode, drain electrode and active layer figure by composition technology, and, in described composition technology, be etched away at the active layer at raceway groove place;
C2, on the substrate of completing steps B2, deposited semiconductor layer film and passivation layer film successively by mask mask, exposure, development, etching technics, form the figure that keeps unexposed photoresist;
D2, on the substrate of completing steps C2, pixel deposition electrode layer film by peeling off described unexposed photoresist, forms semiconductor layer, pixel electrode figure.
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| CN102386237A (en) * | 2011-11-23 | 2012-03-21 | 深圳市华星光电技术有限公司 | Thin-film transistor, array substrate and device and preparation method |
| CN112103300B (en) * | 2020-09-15 | 2023-09-05 | 江苏集萃有机光电技术研究所有限公司 | Silicon-based display panel and preparation method thereof |
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