CN102810558B - A thin film transistor array substrate and a liquid crystal display and the manufacturing method - Google Patents

A thin film transistor array substrate and a liquid crystal display and the manufacturing method Download PDF

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CN102810558B
CN102810558B CN 201210279838 CN201210279838A CN102810558B CN 102810558 B CN102810558 B CN 102810558B CN 201210279838 CN201210279838 CN 201210279838 CN 201210279838 A CN201210279838 A CN 201210279838A CN 102810558 B CN102810558 B CN 102810558B
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electrode
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张弥
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京东方科技集团股份有限公司
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Abstract

本发明的实施例提供一种薄膜晶体管、阵列基板及其制造方法和液晶显示器,涉及液晶面板制造领域,可以减小薄膜晶体管的厚度。 Embodiments of the present invention provide a thin film transistor array substrate and a method of manufacturing a liquid crystal display, to a liquid crystal panel manufacturing field, it is possible to reduce the thickness of the thin film transistor. 该薄膜晶体管,包括:基板;在基板上形成有栅极;覆盖栅极的栅绝缘层;在栅绝缘层上形成有半导体有源层,像素电极层、源极和漏极;其中,所述像素电极层位于所述源极和漏极下方,与所述源极和漏极相接触;且所述源极及其下方的像素电极层的叠层、漏极及其及下方的像素电极层的叠层位于所述半导体有源层的同一层;所述源极及其下方的像素电极层的叠层、所述漏极及其下方的像素电极层的叠层被所述半导体有源层断开;在所述源极、漏极、像素电极层和半导体有源层上形成有钝化层。 The thin film transistor, comprising: a substrate; a gate electrode on a substrate; a gate insulating layer covering the gate; on the gate insulating layer formed on the semiconductor active layer, a pixel electrode layer, source and drain electrodes; wherein the a pixel electrode layer is located below the source and drain electrodes in contact with the source and drain electrodes; and the pixel electrode and the source electrode layer of the laminate layer under the pixel electrode, and the drain and underneath lamination in the same layer of the semiconductor active layer; stack of the source and the pixel electrode layer under the drain and the pixel electrode layer stacked below the active layer by the semiconductor OFF; electrode, the drain electrode is formed on the passivation layer, pixel electrode layer and the semiconductor active layer in the source. 本发明的实施例用于液晶显示器制造。 Embodiments of the present invention for a liquid crystal display manufacturing.

Description

薄膜晶体管、阵列基板及其制作方法和液晶显示器 A thin film transistor array substrate and a liquid crystal display and the manufacturing method

技术领域 FIELD

[0001] 本发明涉及液晶显示领域,尤其涉及一种薄膜晶体管、阵列基板及其制作方法和液晶显示器。 [0001] The present invention relates to a liquid crystal display, and particularly relates to a thin film transistor array substrate and a liquid crystal display and the manufacturing method.

背景技术 Background technique

[0002] 在平板显不技术中,TFT-LCD(Thin Film Transistor-Liquid Crystal Display, 薄膜晶体管液晶显示器)具有功耗低、制造成本相对较低、和无辐射的特点,因此在平板显示器市场占据了主导地位。 [0002] In flat panel display technology is not, TFT-LCD (Thin Film Transistor-Liquid Crystal Display, TFT-LCD) having a low power, relatively low manufacturing cost, and no radiation characteristics, thus occupying the flat panel display market a dominant position. TFT-LCD是由TFT (薄膜晶体管)阵列基板和彩膜基板对盒形成的。 TFT-LCD is a TFT (thin film transistor) array substrate and the color filter substrate is formed on the cassette.

[0003] 目前主流的非晶硅TFT阵列基板5-Mask (5-掩膜)工艺,每一次工艺都包括沉积、 曝光、显影、刻蚀、剥离等。 [0003] The current mainstream amorphous silicon TFT array substrate 5-Mask (5- mask) process, each process includes depositing, exposing, developing, etching, peeling. 通过各次构图在基板上依次形成栅线、栅绝缘层、半导体有源层、 数据线和源、漏极、钝化层、以及像素电极层。 Each is formed by sequentially patterning the gate line on a substrate, a gate insulating layer, a semiconductor active layer, a data line and a source, a drain, a passivation layer, and a pixel electrode layer.

[0004] 在目前的TFT阵列基板中,由于TFT大多是纵向层叠结构,因此盒厚较厚,降低了液晶响应速度。 [0004] In the current TFT array substrate, since the TFT mostly longitudinal laminated structure, cell thickness so thick, the liquid crystal response speed is reduced.

发明内容 SUMMARY

[0005] 本发明的实施例提供一种薄膜晶体管、阵列基板及其制作方法和液晶显示器,减小了薄膜场效应管的厚度。 Example [0005] The present invention provides a thin film transistor array substrate and a liquid crystal display and fabrication method, reducing the thickness of the film field-effect transistor.

[0006] 为达到上述目的,本发明的实施例采用如下技术方案: [0006] To achieve the above object, embodiments of the present invention adopts the following technical solutions:

[0007] -方面,提供了一种薄膜晶体管,包括: [0007] - aspect, there is provided a thin film transistor, comprising:

[0008] 基板; [0008] a substrate;

[0009] 在所述基板上形成有栅极; [0009] The gate electrode is formed on the substrate;

[0010] 覆盖所述栅极的栅绝缘层; [0010] covering the gate of the gate insulating layer;

[0011] 在所述栅绝缘层上形成有半导体有源层,像素电极层、源极和漏极;其中,所述像素电极层位于所述源极和漏极下方,与所述源极和漏极相接触;且所述源极及其下方的像素电极层的叠层、漏极及其及下方的像素电极层的叠层位于所述半导体有源层的同一层; 所述源极及其下方的像素电极层的叠层、所述漏极及其下方的像素电极层的叠层被所述半导体有源层断开; [0011] The semiconductor active layer is formed, the pixel electrode layer, source and drain electrodes on the gate insulating layer; wherein the pixel electrode layer is located below the source and drain, and the source and a drain contact; and the source and the stack layer beneath the pixel electrode, the pixel electrode layer stack and the bottom of the drain and the same layer of the semiconductor active layer; the source and the pixel electrode layers laminated thereunder, beneath the laminate and the drain electrode layer of the pixel is the disconnected semiconductor active layer;

[0012] 在所述源极、漏极、像素电极层和半导体有源层上形成有钝化层。 [0012] The passivation layer is formed on the electrode, the drain electrode, the pixel electrode layer and a semiconductor active layer of the source.

[0013] 所述源极及其下方的像素电极层的叠层的厚度、所述漏极及其下方的像素电极层的叠层的厚度与所述半导体有源层的厚度相同。 [0013] The thickness of the laminate and a source electrode layer under the pixel, the same thickness as the laminate of the pixel electrode and the drain layer beneath the semiconductor active layer.

[0014] 一方面,提供一种阵列基板,包括纵横交叉的栅线、数据线及存储电容底电极,所述栅线和数据线围成像素单元,所述像素单元包括上述的薄膜晶体管。 [0014] In one aspect, it provides an array substrate, comprising vertical and horizontal cross the gate lines, data lines and the storage capacitor bottom electrode, the gate line and the data line surrounded pixel unit, the pixel unit includes the above thin film transistor.

[0015] 在所述存储电容底电极和所述数据线之间的交叠处形成有隔垫半导体层; [0015] The semiconductor layer is formed with a septum in the overlapping between the data line electrode and the bottom of the storage capacitor;

[0016] 和/或,在所述栅线和所述数据线之间的交叠处形成有隔垫半导体层。 [0016] and / or overlap is formed between the gate lines and the data lines are semiconductor spacer layer.

[0017] 还包括:位于所述像素单元边缘与所述存储电容底电极和所述栅线同层的挡光条。 [0017] further comprising: means in said edge of said pixel storage capacitor bottom electrode and the gate line with the strip light blocking layer.

[0018] 所述数据线下方形成有所述像素电极层。 [0018] The data lines are formed below the pixel electrode layer.

[0019] 一方面,提供一种液晶显示器,包括上述的任一阵列基板。 [0019] In one aspect, there is provided a liquid crystal display comprising an array substrate of any of the above.

[0020] -方面,提供一种薄膜晶体管的制作方法,包括: [0020] - aspect, a method for manufacturing a thin film transistor, comprising:

[0021] 在基板上形成一层金属薄膜通过构图工艺形成栅极; [0021] forming a metal film on the substrate by forming a gate patterning process;

[0022] 在所述基板上形成栅绝缘层; [0022] forming a gate insulating layer on the substrate;

[0023] 在所述栅绝缘层上形成有源层并通过构图工艺处理得到位于所述栅极上方的半导体有源层; [0023] The active layer is formed on the gate insulating layer and the semiconductor active layer is obtained above the gate electrode by a patterning process;

[0024] 在所述基板上先后形成一层像素电极层和一层金属薄膜; [0024] successively form a pixel electrode layer and a metal thin film on the substrate;

[0025] 通过一次构图工艺形成源极和漏极并去除所述半导体有源层上方的所述像素电极层和金属薄膜; [0025] The source and drain are formed through one patterning process and removing the pixel electrode layer and the metal thin film above the semiconductor active layer;

[0026] 在以此得到的所述整个基板上形成钝化层。 [0026] forming a passivation layer over the entire substrate thus obtained.

[0027] -方面,提供一种阵列基板的制作方法,包括: [0027] - aspect, a method for manufacturing an array substrate, comprising:

[0028] 在基板上形成一层金属薄膜,通过构图工艺形成栅线、栅极、存储电容底电极; [0028] The metal thin film layer formed on a substrate, forming a gate line, a gate, a storage capacitor bottom electrode by a patterning process;

[0029] 在所述基板上形成栅绝缘层; [0029] forming a gate insulating layer on the substrate;

[0030] 在所述栅绝缘层上形成有源层并通过构图工艺处理得到位于所述栅极上方的半导体有源层; [0030] The active layer is formed on the gate insulating layer and the semiconductor active layer is obtained above the gate electrode by a patterning process;

[0031] 在所述基板上先后形成一层像素电极层和一层金属薄膜; [0031] successively form a pixel electrode layer and a metal thin film on the substrate;

[0032] 通过构图工艺处理得到数据线、源极、漏极和像素电极并去除所述半导体有源层上方的所述像素电极层和金属薄膜; [0032] The data obtained by the patterning process line, the source electrode, the drain electrode and the pixel electrode and removing the pixel electrode layer and the metal thin film above the semiconductor active layer;

[0033] 在以此得到的所述整个基板上形成钝化层。 [0033] forming a passivation layer over the entire substrate thus obtained.

[0034] 通过形成所述栅线、栅极、存储电容底电极构图工艺同时形成挡光条。 [0034] By forming the gate line, the gate, storage capacitor bottom electrode patterning process simultaneously forming a light blocking bar.

[0035] 通过形成所述栅极上方的半导体有源层的构图工艺同时形成位于所述存储电容底电极和所述数据线之间的交叠处的隔垫半导体层,和/或位于所述栅线和所述数据线之间的交叠处的隔垫半导体层。 [0035] The patterning process simultaneously formed by forming the semiconductor active layer over the gate electrode overlapping the spacer between the bottom capacitor electrode and the data line pad semiconductor layer located at the storage, and / or at the overlapping the spacer between the gate line and the data line pad of the semiconductor layer.

[0036] 本发明提供的薄膜晶体管、阵列基板及其制造方法和液晶显示器,其中薄膜晶体管的源极、漏极位于像素电极层之上,且被半导体有源层断开,源极、漏极以及其下的像素电极层和半导体有源层位于同层,且厚度相同;这样,相比现有技术中层叠结构的薄膜晶体管,本发明实施例提供的薄膜晶体管更薄,因此采用该薄膜晶体管的阵列基板更薄,进而做成的面板盒厚较薄,从而提高了液晶响应速度。 [0036] The present invention provides a thin film transistor array substrate and a method of manufacturing a liquid crystal display, wherein the source of the thin film transistor, the pixel electrode layer located over the drain, is turned off and the semiconductor active layer, a source electrode, a drain and a pixel electrode layer and the semiconductor active layer which is located under the same layer thickness and the same; Thus, a thin film transistor as compared to the prior art laminated structures, the thinner the thin film transistor according to an embodiment of the present invention, thus using the thin film transistor the array substrate thinner, and thus make the panel thinner cell thickness, thereby improving the liquid crystal response speed.

附图说明 BRIEF DESCRIPTION

[0037] 为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,还可以根据这些附图获得其他的附图。 [0037] In order to more clearly illustrate the technical solutions in the embodiments or the prior art embodiment of the present invention, briefly introduced hereinafter, embodiments are described below in the accompanying drawings or described in the prior art needed to be used in describing the embodiments the drawings are only some embodiments of the present invention, those of ordinary skill in the art is concerned, it may derive from these drawings other drawings.

[0038] 图1为本发明实施例提供的薄膜晶体管结构示意图; [0038] FIG. 1 is a schematic structural diagram of a thin film transistor of the embodiment of the present invention;

[0039] 图2为本发明实施例提供的薄膜晶体管制作方法流程示意图; [0039] FIG. 2 is a schematic flow method for manufacturing a thin film transistor according to an embodiment of the present invention;

[0040] 图3为制造本发明实施例提供的薄膜晶体管制作过程中的结构示意图一; [0040] FIG. 3 is a structure of the present invention for manufacturing a thin film transistor fabrication process provided in a schematic embodiment;

[0041] 图4为制造本发明实施例提供的薄膜晶体管制作过程中的结构示意图二; [0041] FIG 4 is a structure of a thin film transistor fabrication process embodiment provided by the present invention for manufacturing a schematic view of two embodiments;

[0042]图5为制造本发明实施例提供的薄膜晶体管制作过程中的结构示意图三; The thin film transistors manufactured according to the present invention is to provide a process embodiment of the structure [0042] FIG. 5 is a schematic three;

[0043]图6为制造本发明实施例提供的薄膜晶体管制作过程中的结构示意图四; [0043] FIG. 6 is a manufacturing process for manufacturing a thin film transistor provided in the four structural diagram of the invention;

[0044]图7为制造本发明实施例提供的薄膜晶体管制作过程中的结构示意图五; [0044] FIG. 7 is a process for manufacturing the structure of the thin film transistors provided in the embodiment of the present invention, a schematic view of five;

[0045] 图8为本发明实施例提供的薄膜晶体管阵列基板结构示意图; [0045] Figure 8 a schematic view of a thin film transistor array substrate according to an embodiment of the present invention;

[0046] 图9为图8的AA向截面图; [0046] FIG. 9 is a diagram of the sectional view AA 8;

[0047] 图10为本发明的实施例提供的一种阵列基板的制作方法。 A method of making an array substrate provided in [0047] FIG. 10 of the present invention.

具体实施方式 detailed description

[0048] 下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。 [0048] below in conjunction with the present invention in the accompanying drawings, technical solutions of embodiments of the present invention are clearly and completely described, obviously, the described embodiments are merely part of embodiments of the present invention, but not all embodiments example.

[0049] 本发明的实施例提供一种薄膜晶体管,如图1所示,包括:基板201 ;在基板201 上形成有栅极202 ;覆盖栅极202的栅绝缘层203 ;在栅绝缘层203上形成有半导体有源层207,像素电极层204、源极208和漏极206 ;其中,像素电极层204位于源极208和漏极206 下方,与源极208和漏极206相接触;且源极208及其下方的像素电极层204的叠层、漏极206及其下方的像素电极层204的叠层位于半导体有源层207的同一层;源极208及其下方的像素电极层204的叠层、漏极206及其下方的像素电极层204的叠层被半导体有源层207断开;在源极208、漏极206、像素电极层204和半导体有源层207上形成有钝化层209。 [0049] Embodiments of the present invention provide a thin film transistor shown in Figure 1, comprising: a substrate 201; the gate electrode 202 is formed on the substrate 201; the gate insulating layer 203 covering the gate electrode 202; a gate insulating layer 203 is formed on the semiconductor active layer 207, the pixel electrode layer 204, source 208 and drain 206; wherein the pixel electrode layer 204 is located beneath the source electrode 208 and drain 206, 208 and the drain electrode 206 in contact with the source; and the source 208 and the laminate layer under the pixel electrode 204, the pixel electrode layer stack 206 and the drain 204 is located below the same layer as the semiconductor active layer 207; source 208 and the pixel electrode layer 204 below the laminate, a drain 206 and a lamination layer below the pixel electrode 204 is disconnected the semiconductor active layer 207; source 208, drain 206, and 204 are formed on the passivation layer of the semiconductor active layer, a pixel electrode 207 layer 209.

[0050] 优选的,源极208及其下方的像素电极层204的叠层的厚度、漏极206及其下方的像素电极层204的叠层的厚度与半导体有源层207的厚度相同。 The thickness of the laminate [0050] Preferably, the source electrode 208 and the pixel electrode layer 204 below the same thickness as the drain electrode 206 and the pixel electrode layer stack 204 below the thickness of the semiconductor active layer 207.

[0051] 本发明提供的薄膜晶体管的源极、漏极位于像素电极层之上,且被半导体有源层断开,源极、漏极以及其下的像素电极层和半导体有源层位于同层,且厚度相同;这样,相比现有技术中层叠结构的薄膜晶体管,本发明实施例提供的薄膜晶体管更薄,因此采用该薄膜晶体管的阵列基板更薄,进而做成的面板盒厚较薄,从而提高了液晶响应速度。 [0051] The source of the present invention to provide a thin film transistor, a drain electrode layer located above the pixel, is turned off and the semiconductor active layer, a source, a drain and a pixel electrode layer and that the semiconductor active layer located under the same layer, and the same thickness; Thus, a thin film transistor as compared to the prior art laminated structures, the thinner the thin film transistor according to an embodiment of the present invention, thus using the thin film transistor array substrate is thinner, and thus made thicker than the panel case thin, thereby improving the liquid crystal response speed.

[0052] 本发明的实施例还提供了一种薄膜晶体管的制造方法,参照图2〜7所示,包括以下步骤: [0052] Example embodiments of the present invention further provides a method of manufacturing a thin film transistor, as shown with reference to FIG. 2~7, comprising the steps of:

[0053] S101、如图3所示,在基板201上形成一层金属薄膜,通过构图工艺处理形成栅极202。 [0053] S101, as shown in FIG. 3, a metal thin film is formed on the substrate 201, a gate 202 is formed by a patterning process.

[0054] 可以使用磁控溅射方法,在基板上制备一层厚度在 [0054] magnetron sputtering method may be used, prepared on a substrate in a thickness

Figure CN102810558BD00061

to

Figure CN102810558BD00062

的金属薄膜。 The metal thin film. 制作金属薄膜的金属材料通常可以采用钥、铝、铝镍合金、钥钨合金、铬、或铜等,也可以使用上述几种材料薄膜的组合结构。 Making the metal thin film may be a metal material usually used key, aluminum, aluminum-nickel alloys, keyhole tungsten alloy, chromium, copper, or the like, may be used in combination with the above-described structure of several thin film of material. 然后,用掩模版通过曝光、显影、刻蚀、剥离等工艺处理, 在基板的一定区域上形成栅极202 ;其中,栅极202成膜即金属薄膜的成膜方法具体可以为等离子增强化学气相沉积(PECVD)、磁控溅射、热蒸发或其它成膜方法。 Then, with the mask by the exposure, development, etching, peeling process, a gate 202 is formed on a certain region of the substrate; wherein, the gate 202 deposition method of forming a metal thin film that is specifically plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation deposition, or other methods.

[0055] S102、如图4所示,在基板201上形成栅极绝缘层203。 [0055] S102, as shown in FIG. 4, the gate insulating layer 203 is formed on the substrate 201.

[0056] 然后可以利用化学汽相沉积法在基板上连续沉积厚度为 [0056] then using a chemical vapor deposition process is continuously deposited on the substrate to a thickness of

Figure CN102810558BD00063

to

Figure CN102810558BD00064

的栅绝缘层薄膜;栅绝缘层的材料通常是氮化硅,也可以使用氧化硅和氮氧化硅等,栅绝缘层的成膜方法可以采用沉积方式、旋涂方式或滚涂方式。 A gate insulating film layer; a gate insulating layer material is typically silicon nitride, and silicon oxide may be silicon oxynitride, the gate insulating layer is deposited film formation method may employ, spin coating or roll coating method.

[0057] S103、如图5所示,在栅极绝缘层203上形成有源层并通过构图工艺处理得到位于栅极202上方的半导体有源层207。 [0057] S103, as shown in FIG. 5, the active layer is formed on the gate insulating layer 203 and to obtain the semiconductor active layer 207 is located above the gate electrode 202 by a patterning process.

[0058] 可以在栅绝缘层上利用化学汽相沉积法沉积厚度为 [0058] The thickness may be deposited using a chemical vapor deposition method on the gate insulating layer

Figure CN102810558BD00065

to

Figure CN102810558BD00066

的非晶硅薄膜和n+非晶硅薄膜,也可以是在栅绝缘层薄膜之上沉积金属氧化物半导体薄膜;用有源层的掩模版对非晶硅薄膜进行曝光,之后对该非晶硅薄膜进行干法刻蚀,在栅极的上方形成有源层。 The amorphous silicon thin film and the n + amorphous silicon thin film, may be a metal oxide semiconductor thin film is deposited over the gate insulating film layer; the amorphous silicon film is exposed with reticle active layer, after the amorphous silicon dry etching the thin film, forming an active layer over the gate electrode. 此外,如果是在栅绝缘层薄膜之上沉积金属氧化物半导体薄膜作为有源层,则对金属氧化物薄膜进行一次构图工艺即可形成有源层,即在光刻胶涂覆后,用普通的掩模版对基板进行曝光、显影、刻蚀形成半导体有源层即可。 Further, if it is a metal oxide semiconductor thin film is deposited over the gate insulating layer thin film as an active layer, the metal oxide thin film patterning process to form the active layer, i.e. the photoresist coating, ordinary reticle substrate is exposed and developed, etching the semiconductor active layer can be formed.

[0059] S104、如图6所不,在基板上先后形成一层像素电极层30和一层金属薄膜40。 [0059] S104, FIG. 6 is not, to form a layer on the substrate has a pixel electrode layer 30 and the metal thin film layer 40.

[0060] S105、如图7所示,通过构图工艺形成源极208、漏极206同时,去除掉半导体有源层207上方的像素电极层30和金属薄膜40。 [0060] S105, as shown in FIG. 7, a patterning process to form the source 208, drain 206 at the same time, to remove the pixel electrode layer 30 and the metal film 40 above the semiconductor active layer 207. 使得源极208及其下方的像素电极层204的叠层、漏极206及其下方的像素电极层204的叠层被半导体有源层207断开。 So that the source 208 and the pixel electrode layer below the stack 204, a drain 206 and a lamination layer below the pixel electrode 204 is disconnected semiconductor active layer 207.

[0061] 此时,源极208及其下方的像素电极层204的叠层、漏极206以及其下的像素电极层204的叠层位于半导体有源层207的同一层,优选的,源极208及其下方的像素电极层204的叠层的厚度、漏极206及其下方的像素电极层204的叠层的厚度与半导体有源层207 的厚度相同。 [0061] At this time, the source electrode 208 and a lamination stack below the pixel electrode layer, the drain electrode 206 and the pixel electrode layer 204 under the active layer 204 of the semiconductor layer 207 with, preferably, a source the thickness of the laminate layer 208 and beneath the pixel electrode 204, the drain 206 of the same thickness of the laminate and below the pixel electrode layer 204 and the thickness of the semiconductor active layer 207.

[0062] 可以采用和制作栅极类似的工艺,在基板上先后沉积透明像素电极层和30 -层金属薄膜40,通过刻蚀去除半导体有源层207上方的像素电极层30和金属薄膜40。 [0062] and the production process can be similar to gate electrode, is deposited on the substrate has a transparent pixel electrode layer and 30-- metal thin film layer 40, the pixel electrode layer 30 is removed and the metal film 40 above the semiconductor active layer 207 by etching.

[0063] S106、在整个基板201上形成钝化层209,如图1所示。 [0063] S106, a passivation layer 209 is formed on the entire substrate 201, as shown in FIG.

[0064] 在已形成的源极、漏极、半导体有源层区域的图形上,采用化学气相沉积(PECVD) 或其他成膜方法,沉积厚度为 [0064] electrode, the drain electrode, the active layer pattern on a semiconductor region by chemical vapor deposition (PECVD), or other film forming method have been formed in the source, the deposition thickness

Figure CN102810558BD00071

的保护层,保护层可以选用氧化物、氮化物或氧氮化合物,对应的反应气体可以为SiH4、NH3、N2的混合气体或SiH 2Cl2、NH3、N2的混合气体。 A protective layer, a protective layer may be oxide, nitride or oxynitride, corresponding to the reaction gas may be a mixed gas of SiH4, NH3, N2 or a mixed gas of SiH 2Cl2, NH3, N2 of.

[0065] 本发明提供的薄膜晶体管制造方法,使得源极、漏极位于像素电极层之上,且被半导体有源层断开,源极、漏极以及其下的像素电极层和半导体有源层位于同层,且厚度相同;这样,相比现有技术中层叠结构的薄膜晶体管,采用本发明实施例提供的薄膜晶体管制造方法制作的薄膜晶体管更薄,因此采用该薄膜晶体管的阵列基板更薄,进而做成的面板盒厚较薄,从而提1¾ 了液晶响应速度。 [0065] The thin film transistor of the present invention provides a method for producing such a source, a drain located above the pixel electrode layer and the semiconductor active layer is turned off, the source electrode, the drain and the pixel electrode layer and the semiconductor active under the layer is the same layer, and the same thickness; Thus, a thin film transistor as compared to prior art laminated structure, a method of manufacturing a thin film transistor provided in a thin film transistor made thinner embodiment of the present invention, thus using the thin film transistor array substrate more thin, thick panel case further made thinner, thereby improving the liquid crystal response speed 1¾.

[0066] 参照图8和9所示,对本发明实施例所提供的阵列基板进行说明。 As shown in [0066] Referring to FIGS. 8 and 9, will be described array substrate provided by embodiments of the present invention. 该阵列基板包括纵横交叉的栅线11、数据线14及存储电容底电极13,栅线11和数据线14围成像素单元, 像素单元包括上述实施例提供的TFT。 The array substrate includes a gate line 11 of the crossbar, the data lines 14 and 13, the gate lines 11 and data lines 14 surrounded pixel unit comprises a pixel unit TFT storage capacitor bottom electrode provided in the above-described embodiments. 具体的该阵列基板包括:基板201 ;在基板201上形成有栅线11、栅极202、以及存储电容底电极13 ;在栅线11、栅极202、存储电容底电极13和基板201上形成有栅绝缘层203 ;在栅绝缘层203上形成有半导体有源层207,像素电极层204和数据线14、源极208、漏极206。 The particular array substrate comprising: a substrate 201; the gate line 11, a gate 202, and a storage capacitor bottom electrode 13 is formed on the substrate 201; is formed on the gate line 11, a gate 202, a storage capacitor electrode 13 and the bottom substrate 201 a gate insulating layer 203; 207 is formed with a semiconductor active layer, a pixel electrode layer 204 and the data line 14 on the gate insulating layer 203, source electrode 208, drain electrode 206.

[0067] 优选的,该阵列基板还可以包括位于像素单元边缘与存储电容底电极和栅线同层的挡光条12,以防止漏光及相邻像素单元间的光串扰现象发生。 [0067] Preferably, the array substrate may further include a light blocking bar 12 positioned pixel cell bottom edge of the storage capacitor line and the gate electrode in the same layer, to prevent light leakage and optical crosstalk between adjacent pixel cells occurs.

[0068] 在本实施例中,如图9所示,像素电极层204位于数据线(图9中未表示)、源极208、漏极206下方,与数据线、源极208、漏极206相接触。 [0068] In the present embodiment, as shown in FIG. 9, the pixel electrode layer 204 in a data line (not shown in FIG. 9), the source 208, drain 206 below the data line, source electrode 208, drain electrode 206 contact. 在薄膜晶体管区域,源极208、漏极206及其下方的像素电极层204位于半导体有源层207的同一层,优选的,源极208及其下方的像素电极层204的叠层的厚度、漏极206及其下方的像素电极层204的叠层的厚度与半导体有源层207的厚度相同,源极208及其下方的像素电极层204的叠层、漏极206及其下方的像素电极层204的叠层被半导体有源层207断开。 In the thin film transistor region, a source electrode 208, drain electrode 206 and the pixel electrode layer 204 is located below the active layer of the semiconductor layer 207 with, preferably, a source electrode 208 and the pixel below the thickness of the laminate layer 204, the pixel electrode layer stack 206 and the drain 204 below the thickness of the semiconductor active layer 207 of the same thickness, the pixel electrode 208 and the source electrode stack layer below the pixel electrode 204, the drain 206 and the bottom of the laminate layer 204 is disconnected semiconductor active layer 207.

[0069] 本发明提供的阵列基板,在阵列基板的薄膜晶体管区域,源极、漏极位于像素电极层之上,且被半导体有源层断开,源极、漏极以及其下的像素电极层和半导体有源层位于同层,且厚度相同。 [0069] The present invention provides an array substrate, in the region of the thin film transistor array substrate, a source electrode, a drain electrode layer located above the pixel, is turned off and the semiconductor active layer, a source electrode, a drain electrode and a pixel in which The semiconductor layer and the active layer in the same layer and the same thickness. 这样,相比现有技术中层叠结构的薄膜晶体管,本发明实施例提供的薄膜晶体管更薄,因此该薄膜晶体管阵列基板更薄,进而做成的面板盒厚较薄,从而提高了液晶响应速度。 Thus, compared to the prior art thin film transistor of the laminated structure, the thinner the thin film transistor according to an embodiment of the present invention, so that the thinner the thin film transistor array substrate, further panel made of thin cell gap, thereby improving the liquid crystal response speed .

[0070] 进一步的,如图8所示,在本实施例中,在形成半导体有源层207的同时,可以在栅线11和数据线14之间的交叠处形成有隔垫半导体层2071 ;和/或,在存储电容底电极13 和数据线14之间的交叠处形成隔垫半导体层2072。 [0070] Further, as shown in FIG. 8, in the present embodiment, while forming the semiconductor active layer 207, the spacer may be formed in a semiconductor layer 2071 overlapping between the gate lines 14 and data lines 11 ; and / or, in the storage capacitor is formed between the bottom electrode overlap the data lines 13 and 14 of the semiconductor spacer layer 2072.

[0071] 这样一来,增加了数据线和栅线的交叠处,数据线和存储电容底电极的交叠处的层高,避免了交叠处的金属线层间端差过大导致的液晶旋转异常现象的发生。 [0071] Thus, increasing the overlap of the data lines and the gate lines, data lines overlapping the storey and a storage capacitor bottom electrode, the difference between the end of avoiding overlapping the metal wire layer is too large to LCD rotation anomalies occur. 同时,减少了栅线和数据线间发生静电击穿,以及数据线发生断裂的概率。 At the same time, reducing the probability of occurrence of electrostatic breakdown between the gate and data lines, and the data lines fracture. 另外,当存储电容底电极发生断裂时,可以用激光将存储电容底电极和像素电极连接,通过像素电极来传输公共电极信号,同时需要将该像素变成暗点。 Further, when the storage capacitor bottom electrode breakage occurs, a laser may be a bottom electrode and a storage capacitor connected to the pixel electrode, the common electrode signal transmitted through the pixel electrode, while the need for a dark pixel point. 由于有源层的存在,使得连接面积加大,成功率更高。 Due to the presence of the active layer, so that the connection area is increased, a higher success rate.

[0072] 结合本发明的实施例提供的薄膜晶体管的制造方法本发明还本实施例提供了阵列基板的具体的制作方法,参照图10所示,包括以下流程: [0072] The method of manufacturing a thin film transistor with an embodiment of the present invention provides the principal embodiment of the present invention provides a specific method for manufacturing the array substrate, with reference to FIG. 10, the process comprising:

[0073] S201、在基板201上形成一层金属薄膜,通过构图工艺处理形成栅线、栅极202、存储电容底电极13。 [0073] S201, the substrate 201 is formed on the metal thin film layer, a gate line is formed by a patterning process, the gate 202, the bottom electrode of the storage capacitor 13.

[0074] 当然,可选的在该步骤中还可以形成挡光条12。 [0074] Of course, further optional light blocking bar 12 may be formed in this step.

[0075] S202、在基板201上形成栅极绝缘层203。 [0075] S202, a gate insulating layer 203 is formed on the substrate 201.

[0076] S203、在栅极绝缘层203上方形成有源层并通过构图工艺处理得到位于栅极202 上方的半导体有源层207。 [0076] S203, an active layer formed over the gate insulating layer 203 and to obtain the semiconductor active layer 207 is located above the gate electrode 202 by a patterning process.

[0077] 可选的在该步骤中还可以同时形成位于存储电容底电极13和数据线14之间的交叠处的隔垫半导体层2072,和/或位于栅线11和数据线14之间的交叠处的隔垫半导体层2071。 [0077] Optionally in this step may also be simultaneously formed between the bottom electrode 14 is located in the storage capacitor and the data line 13 at the overlap between the spacer pads 14 of the semiconductor layer 2072, and / or of the gate lines and the data lines 11 overlapping the pad across the semiconductor layer 2071.

[0078] S204、在基板上先后形成一层像素电极层和30 -层金属薄膜40。 [0078] S204, successively formed on the substrate layer and the pixel electrode layer 30-- metal thin film layer 40.

[0079] S205、通过构图工艺处理得到数据线、源极208、漏极206和像素电极204,同时,去除掉半导体有源层207上方的像素电极层30和金属薄膜40。 [0079] S205, the data obtained by the patterning process line, a source electrode 208, drain electrode 206 and the pixel electrode 204, simultaneously, to get rid of the pixel electrode layer 30 and the metal film 40 above the semiconductor active layer 207. 使得源极208及其下方的像素电极层204、漏极206及其下方的像素电极层204被半导体有源层207断开。 So that the source 208 and the pixel electrode layer 204 below drain 206 and the pixel electrode layer 204 is below the semiconductor active layer 207 OFF.

[0080] 此时,源极208、漏极206以及其下的像素电极层204位于半导体有源层207同一层,优选的,源极208及其下方的像素电极层204的叠层的厚度、漏极206以及其下的像素电极层204的叠层的厚度与半导体有源层207厚度相同。 [0080] At this time, the source electrode 208, drain electrode 206 and the pixel electrode layer 204 is located under the same layer as the semiconductor active layer 207, preferably, the source electrode 208 and the pixel electrode layer under the laminate thickness 204, drain 206 and the same stack of layers under the pixel electrode 204 and the thickness of the semiconductor active layer 207 thickness.

[0081] 这样像素单元中用于控制液晶偏转的像素电极可以与薄膜晶体管中源极及漏极下方的像素电极层同时形成且直接与漏极电连接,与现有技术中通过过孔连接像素电极和漏极的方式相比可以减少制作工艺节约成本。 The pixel electrode [0081] Such a pixel unit for controlling the deflection of the liquid crystal may be formed simultaneously, and directly connected to the drain electrode of the thin film electrode and the pixel electrode layer below the drain of the transistor source, the prior art through the via hole connecting the pixel and a drain electrode can be reduced as compared to the way the production process cost savings.

[0082] S206、在整个基板201上形成钝化层209。 [0082] S206, a passivation layer 209 is formed over the entire substrate 201.

[0083] 其中,以上步骤中的具体制作流程可参照薄膜晶体管的制作流程此处不再赘述。 [0083] wherein the specific production process of the above steps can be referred to the production process of a thin film transistor will not be repeated here.

[0084] 本发明提供的阵列基板的制造方法,在阵列基板的薄膜晶体管区域,源极、漏极位于像素电极层之上,且被半导体有源层断开,源极、漏极以及其下的像素电极层和半导体有源层位于同层,且厚度相同。 [0084] The method of manufacturing the array substrate of the present invention provides, in the region of the thin film transistor array substrate, a source electrode, a drain electrode layer located above the pixel, is turned off and the semiconductor active layer, a source, a drain, and a lower the pixel electrode layer and the semiconductor active layer in the same layer and the same thickness. 这样,相比现有技术中层叠结构的薄膜晶体管,本发明实施例提供的薄膜晶体管更薄,因此该薄膜晶体管阵列基板更薄,进而做成的面板盒厚较薄,从而提商了液晶响应速度。 Thus, compared to the prior art thin film transistor of the laminated structure, the thinner the thin film transistor according to an embodiment of the present invention, so that the thinner the thin film transistor array substrate, further panel made of thin cell gap, thereby improving the liquid crystal response List speed.

[0085] 本发明提供的液晶显示器可以为采用上述阵列基板,其基板的结构与上一实施例相同,在此不再赘述。 [0085] The liquid crystal display of the present invention may be provided in the above array substrate, a substrate structure which is same as a previous embodiment, are not repeated herein.

[〇〇86] 以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本发明的保护范围之内。 [〇〇86] The above are only specific embodiments of the present invention, but the scope of the present invention is not limited thereto, any skilled in the art in the art within the scope of the invention disclosed can be easily thought changes or replacements shall fall within the protection scope of the present invention. 因此,本发明的保护范围应以所述权利要求的保护范围为准。 Accordingly, the scope of the present invention should be defined by the scope of the claims.

Claims (11)

  1. 1. 一种薄膜晶体管,其特征在于,包括: 基板; 在所述基板上形成有栅极; 覆盖所述栅极的栅绝缘层; 在所述栅绝缘层上形成有半导体有源层,像素电极层、源极和漏极;其中,所述像素电极层位于所述源极和漏极下方,与所述源极和漏极相接触;且所述源极及其下方的像素电极层的叠层、漏极及其及下方的像素电极层的叠层位于所述半导体有源层的同一层;所述源极及其下方的像素电极层的叠层、所述漏极及其下方的像素电极层的叠层被所述半导体有源层断开; 在所述源极、漏极、像素电极层和半导体有源层上形成有钝化层。 A thin film transistor comprising: a substrate; a gate is formed on the substrate; a gate covering the gate insulating layer; forming a gate insulating layer on the semiconductor active layer, a pixel electrode layer, source and drain electrodes; wherein the pixel electrode layer is located below the source and the drain, and the drain electrode in contact with said source; and the source electrode and the pixel electrode layer under the laminate, the laminate and the drain electrode and the lower layer of the pixel in the same layer of the semiconductor active layer; the source electrode and the pixel below the laminated layer, and the drain below the pixel electrode layer are laminated with the semiconductor active layer disconnected; a passivation layer is formed on the electrode, the drain electrode, the pixel electrode layer and a semiconductor active layer of the source.
  2. 2. 根据权利要求1所述的薄膜晶体管,其特征在于,所述源极及其下方的像素电极层的叠层的厚度、所述漏极及其下方的像素电极层的叠层的厚度与所述半导体有源层的厚度相同。 2. The thin film transistor according to a thickness of the stack and the pixel electrode layer below the drain according to claim, characterized in that the source electrode and the thickness of the laminate layer under the pixel electrode, the same as the thickness of the semiconductor active layer.
  3. 3. -种阵列基板,包括纵横交叉的栅线、数据线,及存储电容底电极,所述栅线和数据线围成像素单元,其特征在于,所述像素单元包括权利要求1或2所述的薄膜晶体管。 3 - Species array substrate, comprising vertical and horizontal cross the gate lines, data lines, and the storage capacitor bottom electrode, the gate line and the data line surrounded pixel unit, wherein the pixel unit comprises a claimed in claim 1 or 2, the thin film transistor described later.
  4. 4. 根据权利要求3所述的阵列基板,其特征在于,在所述存储电容底电极和所述数据线之间的交叠处形成有隔垫半导体层; 和/或,在所述栅线和所述数据线之间的交叠处形成有隔垫半导体层。 4. The array substrate of claim 3, wherein the spacer is formed in the semiconductor layer overlapping the storage capacitance between the bottom electrode and the data lines; and / or, in the gate line and overlapping the data line is formed between said semiconductor layer with a septum.
  5. 5. 根据权利要求3所述的阵列基板,其特征在于,还包括:位于所述像素单元边缘的与所述存储电容底电极以及所述栅线同层的挡光条。 The array substrate according to claim 3, characterized in that, further comprising: means located at the edge of the pixel light blocking strip and a bottom electrode of the storage capacitor and the same layer as the gate line.
  6. 6. 根据权利要求3所述的阵列基板,其特征在于,所述数据线下方形成有所述像素电极层。 6. The array substrate according to claim 3, wherein the pixel electrode layer is formed below the data line.
  7. 7. -种液晶显示器,其特征在于,包括权利要求3〜6所述的任一阵列基板。 7. - kind of liquid crystal display, wherein said array substrate according to any one of claims 3 ~ 6 comprises.
  8. 8. -种薄膜晶体管的制作方法,其特征在于,包括: 在基板上形成一层金属薄膜通过构图工艺形成栅极; 在所述基板上形成栅绝缘层; 在所述栅绝缘层上形成有源层并通过构图工艺处理得到位于所述栅极上方的半导体有源层; 在所述基板上先后形成一层像素电极层和一层金属薄膜; 通过一次构图工艺形成源极和漏极并去除所述半导体有源层上方的所述像素电极层和金属薄膜;其中所述源极及其下方的像素电极层的叠层、漏极及其及下方的像素电极层的叠层位于所述半导体有源层的同一层;所述源极及其下方的像素电极层的叠层、所述漏极及其下方的像素电极层的叠层被所述半导体有源层断开; 在以此得到的所述整个基板上形成钝化层。 8. - method for manufacturing thin-film transistor, comprising: forming a gate by patterning process of forming a metal film on the substrate; forming a gate insulating layer on the substrate; is formed on the gate insulating layer source layer and the semiconductor active layer is obtained above the gate electrode by a patterning process; successively formed one pixel electrode layer and a metal thin film on the substrate; formed through one patterning process is removed and the source and drain the semiconductor active layer and the pixel electrode layer over the metal thin film; wherein the source stack and the pixel electrode layer below the stack and the drain electrode and the pixel below the layer of the semiconductor with one active layer; laminated the source electrode layer and the pixel below, and the drain of the stack below the pixel electrode layer of the semiconductor active layer are disconnected; in order to obtain forming a passivation layer over the entire substrate.
  9. 9. 一种阵列基板的制作方法,其特征在于,包括: 在基板上形成一层金属薄膜,通过构图工艺形成栅线、栅极、存储电容底电极; 在所述基板上形成栅绝缘层; 在所述栅绝缘层上形成有源层并通过构图工艺处理得到位于所述栅极上方的半导体有源层; 在所述基板上先后形成一层像素电极层和一层金属薄膜; 通过构图工艺处理得到数据线、源极、漏极和像素电极并去除所述半导体有源层上方的所述像素电极层和金属薄膜; 在以此得到的所述整个基板上形成钝化层。 9. A method for manufacturing an array substrate, comprising: forming a layer of a metal thin film on a substrate, forming a gate line, a gate, a storage capacitor bottom electrode is formed by a patterning process; forming a gate insulating layer on the substrate; It is formed on the gate insulating layer and the active layer to obtain the semiconductor active layer positioned above the gate electrode by a patterning process; successively formed one pixel electrode layer and a metal thin film on the substrate; patterning process by processing to obtain the data line, source electrode, drain electrode and the pixel electrode and removing the pixel electrode layer and the metal thin film above the semiconductor active layer; forming a passivation layer on the entire substrate thus obtained.
  10. 10. 根据权利要求9所述的方法,其特征在于,还包括: 通过形成所述栅线、栅极、存储电容底电极的构图工艺同时形成挡光条。 10. The method according to claim 9, characterized in that, further comprising: forming the gate line, a gate, a storage capacitor bottom electrode patterning process simultaneously forming a light blocking bar.
  11. 11. 根据权利要求9或10所述的方法,其特征在于,还包括: 通过形成所述栅极上方的半导体有源层的构图工艺同时形成位于所述存储电容底电极和所述数据线之间的交叠处的隔垫半导体层,和/或位于所述栅线和所述数据线之间的交叠处的隔垫半导体层。 11. The method of claim 9 or claim 10, characterized in that, further comprising: forming a bottom capacitor electrode and the data line is in the memory simultaneously formed by patterning process of the semiconductor active layer above the gate of the interval between the semiconductor layer overlapping the pad, and / or overlapping the spacer positioned between the gate line and the data line pad of the semiconductor layer.
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