CN101622700B - 利用电镀的导电过孔形成 - Google Patents

利用电镀的导电过孔形成 Download PDF

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Publication number
CN101622700B
CN101622700B CN2008800064171A CN200880006417A CN101622700B CN 101622700 B CN101622700 B CN 101622700B CN 2008800064171 A CN2008800064171 A CN 2008800064171A CN 200880006417 A CN200880006417 A CN 200880006417A CN 101622700 B CN101622700 B CN 101622700B
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China
Prior art keywords
conductive layer
forming
semiconductor substrate
layer
continuous conductive
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CN2008800064171A
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English (en)
Chinese (zh)
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CN101622700A (zh
Inventor
T·G·斯巴克斯
R·E·琼斯
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of CN101622700A publication Critical patent/CN101622700A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0261—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
CN2008800064171A 2007-02-27 2008-01-25 利用电镀的导电过孔形成 Active CN101622700B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/679,512 2007-02-27
US11/679,512 US7741218B2 (en) 2007-02-27 2007-02-27 Conductive via formation utilizing electroplating
PCT/US2008/051987 WO2008106256A1 (en) 2007-02-27 2008-01-25 Conductive via formation utilizing electroplating

Publications (2)

Publication Number Publication Date
CN101622700A CN101622700A (zh) 2010-01-06
CN101622700B true CN101622700B (zh) 2011-05-25

Family

ID=39716386

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008800064171A Active CN101622700B (zh) 2007-02-27 2008-01-25 利用电镀的导电过孔形成

Country Status (5)

Country Link
US (1) US7741218B2 (enExample)
JP (1) JP5366833B2 (enExample)
CN (1) CN101622700B (enExample)
TW (1) TWI483312B (enExample)
WO (1) WO2008106256A1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7939941B2 (en) * 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
US7872357B2 (en) * 2008-03-05 2011-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Protection for bonding pads and methods of formation
US8853830B2 (en) * 2008-05-14 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. System, structure, and method of manufacturing a semiconductor substrate stack
US8691664B2 (en) * 2009-04-20 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Backside process for a substrate
TWI471977B (zh) * 2009-05-15 2015-02-01 精材科技股份有限公司 功率金氧半場效電晶體封裝體
TWI504780B (zh) * 2009-09-04 2015-10-21 穩懋半導體股份有限公司 一種利用無電解電鍍法將金屬種子層鍍在半導體晶片的背面及導孔的製程方法
US8304863B2 (en) 2010-02-09 2012-11-06 International Business Machines Corporation Electromigration immune through-substrate vias
US8654541B2 (en) 2011-03-24 2014-02-18 Toyota Motor Engineering & Manufacturing North America, Inc. Three-dimensional power electronics packages
US9105628B1 (en) * 2012-03-29 2015-08-11 Valery Dubin Through substrate via (TSuV) structures and method of making the same
US9219032B2 (en) 2012-07-09 2015-12-22 Qualcomm Incorporated Integrating through substrate vias from wafer backside layers of integrated circuits
US9159699B2 (en) * 2012-11-13 2015-10-13 Delta Electronics, Inc. Interconnection structure having a via structure
JP6104772B2 (ja) * 2013-03-29 2017-03-29 ソニーセミコンダクタソリューションズ株式会社 積層構造体及びその製造方法
US9754883B1 (en) * 2016-03-04 2017-09-05 International Business Machines Corporation Hybrid metal interconnects with a bamboo grain microstructure
US10432172B2 (en) * 2016-09-01 2019-10-01 Samsung Electro-Mechanics Co., Ltd. Bulk acoustic filter device and method of manufacturing the same
JP6877290B2 (ja) * 2017-08-03 2021-05-26 東京エレクトロン株式会社 被処理体を処理する方法
US10699954B2 (en) 2018-04-19 2020-06-30 Teledyne Scientific & Imaging, Llc Through-substrate vias formed by bottom-up electroplating
KR102904447B1 (ko) 2019-07-23 2025-12-29 삼성전자주식회사 반도체 장치
US11949008B2 (en) 2020-12-30 2024-04-02 Win Semiconductors Corp. Semiconductor structure and method for forming the same
US12412810B2 (en) * 2022-03-25 2025-09-09 Applied Materials, Inc. Single side via fill process for through-vias

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08279510A (ja) 1995-04-04 1996-10-22 Murata Mfg Co Ltd 半導体装置の製造方法
US6221769B1 (en) * 1999-03-05 2001-04-24 International Business Machines Corporation Method for integrated circuit power and electrical connections via through-wafer interconnects
US7109068B2 (en) * 2004-08-31 2006-09-19 Micron Technology, Inc. Through-substrate interconnect fabrication methods

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11135506A (ja) * 1997-10-31 1999-05-21 Nec Corp 半導体装置の製造方法
US6852627B2 (en) * 2003-03-05 2005-02-08 Micron Technology, Inc. Conductive through wafer vias
US7179738B2 (en) * 2004-06-17 2007-02-20 Texas Instruments Incorporated Semiconductor assembly having substrate with electroplated contact pads
JP2006210369A (ja) * 2005-01-25 2006-08-10 Murata Mfg Co Ltd 半導体装置およびその製造方法
JP2007049103A (ja) * 2005-08-05 2007-02-22 Zycube:Kk 半導体チップおよびその製造方法、ならびに半導体装置
US7772116B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
US7608538B2 (en) * 2007-01-05 2009-10-27 International Business Machines Corporation Formation of vertical devices by electroplating

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08279510A (ja) 1995-04-04 1996-10-22 Murata Mfg Co Ltd 半導体装置の製造方法
US6221769B1 (en) * 1999-03-05 2001-04-24 International Business Machines Corporation Method for integrated circuit power and electrical connections via through-wafer interconnects
US7109068B2 (en) * 2004-08-31 2006-09-19 Micron Technology, Inc. Through-substrate interconnect fabrication methods

Also Published As

Publication number Publication date
US7741218B2 (en) 2010-06-22
CN101622700A (zh) 2010-01-06
TW200850102A (en) 2008-12-16
US20080206984A1 (en) 2008-08-28
JP5366833B2 (ja) 2013-12-11
JP2010519780A (ja) 2010-06-03
TWI483312B (zh) 2015-05-01
WO2008106256A1 (en) 2008-09-04

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Patentee before: Fisical Semiconductor Inc.

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