CN101622700B - 利用电镀的导电过孔形成 - Google Patents

利用电镀的导电过孔形成 Download PDF

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Publication number
CN101622700B
CN101622700B CN2008800064171A CN200880006417A CN101622700B CN 101622700 B CN101622700 B CN 101622700B CN 2008800064171 A CN2008800064171 A CN 2008800064171A CN 200880006417 A CN200880006417 A CN 200880006417A CN 101622700 B CN101622700 B CN 101622700B
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China
Prior art keywords
conductive layer
forming
semiconductor substrate
layer
continuous conductive
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CN2008800064171A
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Chinese (zh)
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CN101622700A (zh
Inventor
T·G·斯巴克斯
R·E·琼斯
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of CN101622700A publication Critical patent/CN101622700A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
CN2008800064171A 2007-02-27 2008-01-25 利用电镀的导电过孔形成 Active CN101622700B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/679,512 US7741218B2 (en) 2007-02-27 2007-02-27 Conductive via formation utilizing electroplating
US11/679,512 2007-02-27
PCT/US2008/051987 WO2008106256A1 (en) 2007-02-27 2008-01-25 Conductive via formation utilizing electroplating

Publications (2)

Publication Number Publication Date
CN101622700A CN101622700A (zh) 2010-01-06
CN101622700B true CN101622700B (zh) 2011-05-25

Family

ID=39716386

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008800064171A Active CN101622700B (zh) 2007-02-27 2008-01-25 利用电镀的导电过孔形成

Country Status (5)

Country Link
US (1) US7741218B2 (enExample)
JP (1) JP5366833B2 (enExample)
CN (1) CN101622700B (enExample)
TW (1) TWI483312B (enExample)
WO (1) WO2008106256A1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7939941B2 (en) * 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
US7872357B2 (en) * 2008-03-05 2011-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Protection for bonding pads and methods of formation
US8853830B2 (en) 2008-05-14 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. System, structure, and method of manufacturing a semiconductor substrate stack
US8691664B2 (en) * 2009-04-20 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Backside process for a substrate
TWI471977B (zh) * 2009-05-15 2015-02-01 精材科技股份有限公司 功率金氧半場效電晶體封裝體
TWI504780B (zh) * 2009-09-04 2015-10-21 Win Semiconductors Corp 一種利用無電解電鍍法將金屬種子層鍍在半導體晶片的背面及導孔的製程方法
US8304863B2 (en) 2010-02-09 2012-11-06 International Business Machines Corporation Electromigration immune through-substrate vias
US8654541B2 (en) 2011-03-24 2014-02-18 Toyota Motor Engineering & Manufacturing North America, Inc. Three-dimensional power electronics packages
US9105628B1 (en) * 2012-03-29 2015-08-11 Valery Dubin Through substrate via (TSuV) structures and method of making the same
US9219032B2 (en) 2012-07-09 2015-12-22 Qualcomm Incorporated Integrating through substrate vias from wafer backside layers of integrated circuits
US9159699B2 (en) * 2012-11-13 2015-10-13 Delta Electronics, Inc. Interconnection structure having a via structure
JP6104772B2 (ja) * 2013-03-29 2017-03-29 ソニーセミコンダクタソリューションズ株式会社 積層構造体及びその製造方法
US9754883B1 (en) * 2016-03-04 2017-09-05 International Business Machines Corporation Hybrid metal interconnects with a bamboo grain microstructure
US10432172B2 (en) * 2016-09-01 2019-10-01 Samsung Electro-Mechanics Co., Ltd. Bulk acoustic filter device and method of manufacturing the same
JP6877290B2 (ja) * 2017-08-03 2021-05-26 東京エレクトロン株式会社 被処理体を処理する方法
US10699954B2 (en) 2018-04-19 2020-06-30 Teledyne Scientific & Imaging, Llc Through-substrate vias formed by bottom-up electroplating
KR20210012084A (ko) 2019-07-23 2021-02-03 삼성전자주식회사 반도체 장치
US11949008B2 (en) 2020-12-30 2024-04-02 Win Semiconductors Corp. Semiconductor structure and method for forming the same
US12412810B2 (en) * 2022-03-25 2025-09-09 Applied Materials, Inc. Single side via fill process for through-vias

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08279510A (ja) 1995-04-04 1996-10-22 Murata Mfg Co Ltd 半導体装置の製造方法
US6221769B1 (en) * 1999-03-05 2001-04-24 International Business Machines Corporation Method for integrated circuit power and electrical connections via through-wafer interconnects
US7109068B2 (en) * 2004-08-31 2006-09-19 Micron Technology, Inc. Through-substrate interconnect fabrication methods

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11135506A (ja) * 1997-10-31 1999-05-21 Nec Corp 半導体装置の製造方法
US6852627B2 (en) * 2003-03-05 2005-02-08 Micron Technology, Inc. Conductive through wafer vias
US7179738B2 (en) * 2004-06-17 2007-02-20 Texas Instruments Incorporated Semiconductor assembly having substrate with electroplated contact pads
JP2006210369A (ja) * 2005-01-25 2006-08-10 Murata Mfg Co Ltd 半導体装置およびその製造方法
JP2007049103A (ja) * 2005-08-05 2007-02-22 Zycube:Kk 半導体チップおよびその製造方法、ならびに半導体装置
US7772116B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
US7608538B2 (en) * 2007-01-05 2009-10-27 International Business Machines Corporation Formation of vertical devices by electroplating

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08279510A (ja) 1995-04-04 1996-10-22 Murata Mfg Co Ltd 半導体装置の製造方法
US6221769B1 (en) * 1999-03-05 2001-04-24 International Business Machines Corporation Method for integrated circuit power and electrical connections via through-wafer interconnects
US7109068B2 (en) * 2004-08-31 2006-09-19 Micron Technology, Inc. Through-substrate interconnect fabrication methods

Also Published As

Publication number Publication date
TW200850102A (en) 2008-12-16
US7741218B2 (en) 2010-06-22
WO2008106256A1 (en) 2008-09-04
TWI483312B (zh) 2015-05-01
CN101622700A (zh) 2010-01-06
JP5366833B2 (ja) 2013-12-11
US20080206984A1 (en) 2008-08-28
JP2010519780A (ja) 2010-06-03

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Address after: Texas in the United States

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Patentee before: Fisical Semiconductor Inc.

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