CN101584048B - Trench gate type transistor and method for manufacturing the same - Google Patents
Trench gate type transistor and method for manufacturing the same Download PDFInfo
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- CN101584048B CN101584048B CN200880000659XA CN200880000659A CN101584048B CN 101584048 B CN101584048 B CN 101584048B CN 200880000659X A CN200880000659X A CN 200880000659XA CN 200880000659 A CN200880000659 A CN 200880000659A CN 101584048 B CN101584048 B CN 101584048B
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Abstract
In a trench gate type transistor, generation of a gate leak current is eliminated and a gate capacitance is reduced. A trench (14) is formed on an N-type semiconductor layer (12). In the trench (14), a thin silicon oxide film (15B) is formed in a region to be a transistor activation region on the N-type semiconductor layer (12). On the region not to be the activation region, a silicon oxide film (15A) thicker than the silicon oxide film (15B) is formed. Furthermore, an extracting section (16S) extending outward from the inside of the trench (14) forms a gate electrode (16) which is brought into contact with a silicon oxide film (15A). Thus, in the extracting section (16S) of the gate electrode (16), since a long distance between the gate electrode (16) and a corner section (12C) of the N-type semiconductor layer (12) is ensured, generation of the gate leak current is eliminated and the gate capacitance can be reduced.
Description
Technical field
The present invention relates to trench gate type (trench gate) transistor and manufacture method thereof.
Background technology
The DMOS transistor is the MOS FET of dual diffusion, as the power semiconductor element of power circuit or drive circuit etc. and be used.Transistorized a kind of as DMOS, known have a trench gate type transistor.
This trench gate type transistor forms grid oxidation film 215 as shown in figure 48 in the groove 214 that is formed at semiconductor layer 212, grid oxidation film 215 ground in the covering groove 214 have formed gate electrode 216.In addition, the surface at the semiconductor layer 212 of the sidewall of groove 214 by the dual diffusion of vertical direction, forms not shown main body (body) layer and source layer.
In addition, for example in open communique 2005-322949 number of Japan Patent, 2003-188379 number, put down in writing at trench gate type transistor.
As shown in figure 48, among part (hereinafter referred to as the extension) 116S of protruding gate electrode 216 in groove 214, exist the problem that can between gate electrode 216 and semiconductor layer 212, produce leakage current (hereinafter referred to as grid leakage current).According to present inventor's research, its reason is, first, the thin thickness of grid oxidation film 215; The second, in extension 216S, the bight 212C of semiconductor layer 212 is opposed across thin grid oxidation film 215 and gate electrode 216, and therefore, this part generation electric field is concentrated.
Summary of the invention
Trench gate type transistor of the present invention is characterised in that to possess: semiconductor layer; Form being formed within the groove of described semiconductor layer, extend to the gate insulating film on the described semiconductor layer outside the described groove; Be formed on the gate electrode on the described gate insulating film; Be formed on the near surface of described semiconductor layer, with the body layer that described gate insulating film on the sidewall of described groove joins, described gate insulating film possesses: the first grid dielectric film that has first thickness in the part of joining with described body layer; Part on the described semiconductor layer that extends in described groove outside the described groove has the second grid dielectric film of second thickness thicker than described first thickness.
According to this structure, by the part on the described semiconductor layer that in described groove, extends to outside the described groove, formed second grid dielectric film (thick gate insulating film) with second thickness bigger than described first thickness, in the extension of gate electrode, the distance in the bight of gate electrode and semiconductor layer can be guaranteed for longer, therefore, the generation of grid leakage current not only can be prevented, and grid capacitance (constituting) can be reduced by gate electrode, dielectric film, semiconductor layer.
In addition, by having formed first grid dielectric film (thin gate insulating film), can guarantee transistor having excellent characteristic (low threshold value, low on-resistance) with first thickness in the part (activate zone) of joining with described body layer.
The manufacture method of trench gate type transistor of the present invention is characterised in that, comprising: the operation that forms groove on semiconductor layer; By the semiconductor layer that has formed described groove is carried out thermal oxidation, the surface of the described semiconductor layer in comprising described groove forms the operation of oxide-film; Optionally remove the operation of the described oxide-film in the activate zone in the described groove; After optionally having removed described oxide-film, by the described semiconductor layer that has formed described groove is carried out thermal oxidation, form first grid oxide-film on the activate zone in described groove, and form the operation of second grid oxide-film in described transistorized deactivation zone with second thickness thicker than described first thickness with first thickness; This gate electrode is formed in the described groove across described first and second grid oxidation film, and extends to the operation that forms gate electrode outside the described groove across described second grid oxide-film; On the sidewall of described groove, form the operation of body layer with described first grid oxide-film with joining.
According to this structure, can form first grid oxide-film (thin grid oxidation film) in the activate zone, form second grid oxide-film (thick grid oxidation film) in the deactivation zone, can access and above-mentioned same effect.
In addition, trench gate type transistor of the present invention is characterised in that to possess: semiconductor layer; The gate insulating film that in being formed at the groove of described semiconductor layer, forms; Join and form at the end of described groove and described gate insulating film, have thick insulating film than the thickness of described gate insulator thickness; Cover the described gate insulating film in the described groove and extend to gate electrode on the described thick insulating film; Be formed on the near surface of described semiconductor layer, the body layer that joins with the described gate insulating film of the sidewall of described groove.
According to this structure, because by forming described thick insulating film, in the extension of gate electrode, the distance in the bight of gate electrode and semiconductor layer can be guaranteed for longer, so, the generation of grid leakage current not only can be prevented, and grid capacitance (constituting) can be reduced by gate electrode, dielectric film, semiconductor layer.
In addition, the manufacture method of trench gate type transistor of the present invention is characterized in that, comprising: the operation that forms the groove with minor face and long limit on the surface of semiconductor layer; By from direction angle-tilt ion implanted dopant along the long limit of described groove, to the described semiconductor layer of the sidewall of described groove and bottom surface, and with the surface of the semiconductor substrate of described groove adjacency, first ion injecting process of importing impurity; By from direction angle-tilt ion implanted dopant along the minor face of described groove, to the described semiconductor layer of the sidewall top of described groove and with the surface of the semiconductor substrate of described groove adjacency, import second ion injecting process of impurity; Based on the speedup oxidation, form the operation of gate insulating film in the part that has imported impurity by described first and second ion injecting process with thick thickness; Gate electrode across the gate insulating film with thick thickness that forms by described speedup oxidation, extends to the operation that forms gate electrode on the semiconductor layer outside the described groove in described groove.
According to this structure, by utilizing the speedup oxidation that imports based on impurity, form thick gate insulating film, in the extension of gate electrode, the distance in the bight of gate electrode and semiconductor layer can be guaranteed for longer, therefore, the generation of grid leakage current can be prevented, and grid capacitance (constituting) can be reduced by gate electrode, dielectric film, semiconductor layer.
According to trench gate type transistor of the present invention and manufacture method thereof, can prevent the generation of grid leakage current, and can reduce grid capacitance.In addition, also can guarantee outstanding transistor characteristic (low threshold value, low on-resistance).
Description of drawings
Fig. 1 is the vertical view that trench gate type transistor that first execution mode of the present invention is related to and manufacture method thereof describe.
Fig. 2 is the cutaway view that trench gate type transistor that first execution mode of the present invention is related to and manufacture method thereof describe.
Fig. 3 is the cutaway view that trench gate type transistor that first execution mode of the present invention is related to and manufacture method thereof describe.
Fig. 4 is the cutaway view that trench gate type transistor that first execution mode of the present invention is related to and manufacture method thereof describe.
Fig. 5 is the cutaway view that trench gate type transistor that first execution mode of the present invention is related to and manufacture method thereof describe.
Fig. 6 is the cutaway view that trench gate type transistor that first execution mode of the present invention is related to and manufacture method thereof describe.
Fig. 7 is the cutaway view that trench gate type transistor that first execution mode of the present invention is related to and manufacture method thereof describe.
Fig. 8 is the cutaway view that trench gate type transistor that first execution mode of the present invention is related to and manufacture method thereof describe.
Fig. 9 is the cutaway view that trench gate type transistor that first execution mode of the present invention is related to and manufacture method thereof describe.
Figure 10 is the cutaway view that trench gate type transistor that first execution mode of the present invention is related to and manufacture method thereof describe.
Figure 11 is the cutaway view that trench gate type transistor that first execution mode of the present invention is related to and manufacture method thereof describe.
Figure 12 is the cutaway view that trench gate type transistor that first execution mode of the present invention is related to and manufacture method thereof describe.
Figure 13 is the vertical view that trench gate type transistor that first execution mode of the present invention is related to and manufacture method thereof describe.
Figure 14 is the vertical view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 15 is the cutaway view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 16 is the cutaway view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 17 is the cutaway view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 18 is the cutaway view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 19 is the cutaway view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 20 is the cutaway view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 21 is the cutaway view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 22 is the cutaway view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 23 is the cutaway view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 24 is the cutaway view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 25 is the cutaway view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 26 is the cutaway view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 27 is the cutaway view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 28 is the vertical view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 29 is the vertical view that trench gate type transistor that second execution mode of the present invention is related to and manufacture method thereof describe.
Figure 30 is the vertical view that trench gate type transistor that the of the present invention the 3rd and the 4th execution mode is related to and manufacture method thereof describe.
Figure 31 is the cutaway view that trench gate type transistor that the 3rd execution mode of the present invention is related to and manufacture method thereof describe.
Figure 32 is the cutaway view that trench gate type transistor that the 3rd execution mode of the present invention is related to and manufacture method thereof describe.
Figure 33 is the cutaway view that trench gate type transistor that the 3rd execution mode of the present invention is related to and manufacture method thereof describe.
Figure 34 is the cutaway view that trench gate type transistor that the 3rd execution mode of the present invention is related to and manufacture method thereof describe.
Figure 35 is the cutaway view that trench gate type transistor that the 3rd execution mode of the present invention is related to and manufacture method thereof describe.
Figure 36 is the cutaway view that trench gate type transistor that the 3rd execution mode of the present invention is related to and manufacture method thereof describe.
Figure 37 is the cutaway view that trench gate type transistor that the 3rd execution mode of the present invention is related to and manufacture method thereof describe.
Figure 38 is the cutaway view that trench gate type transistor that the 3rd execution mode of the present invention is related to and manufacture method thereof describe.
Figure 39 is the cutaway view that trench gate type transistor that the 3rd execution mode of the present invention is related to and manufacture method thereof describe.
Figure 40 is the cutaway view that trench gate type transistor that the 3rd execution mode of the present invention is related to and manufacture method thereof describe.
Figure 41 is the cutaway view that trench gate type transistor that the 4th execution mode of the present invention is related to and manufacture method thereof describe.
Figure 42 is the cutaway view that trench gate type transistor that the 4th execution mode of the present invention is related to and manufacture method thereof describe.
Figure 43 is the cutaway view that trench gate type transistor that the 4th execution mode of the present invention is related to and manufacture method thereof describe.
Figure 44 is the cutaway view that trench gate type transistor that the 4th execution mode of the present invention is related to and manufacture method thereof describe.
Figure 45 is the cutaway view that trench gate type transistor that the 4th execution mode of the present invention is related to and manufacture method thereof describe.
Figure 46 is the cutaway view that trench gate type transistor that the 4th execution mode of the present invention is related to and manufacture method thereof describe.
Figure 47 is the cutaway view that trench gate type transistor that the 4th execution mode of the present invention is related to and manufacture method thereof describe.
Figure 48 is the cutaway view that the trench gate type transistor of conventional example and manufacture method thereof are described.
Embodiment
[first execution mode]
With reference to accompanying drawing first execution mode of the present invention is described.Fig. 1 is the vertical view that trench gate type transistor that embodiments of the present invention are related to and manufacture method thereof describe.In addition, (A) of (A)～Figure 11 of Fig. 2 is the cutaway view along the A-A line of Fig. 1, and (B)～Figure 11's (B) of Fig. 2 is cutaway view along the B-B line of Fig. 1.In the following description, trench gate type transistor simply is called transistor.
At first, with reference to Fig. 1 the transistorized summary plan structure that present embodiment relates to is described.Here, only main structural element is described.In this transistor, on P type semiconductor substrate 10, be formed with N+ type semiconductor layer 11, N-type semiconductor layer 12, in the face side of N-type semiconductor layer 12 by being formed with the zone of body layer 19, being formed with a plurality of grooves 14 with minor face and long limit.In each groove 14, be formed with gate electrode 16 across gate insulating film (not shown).Each gate electrode 16 connects at an end of each groove 14, and extends outside groove 14.The gate electrode 16 that extends outside groove 14 is connected with wiring (not shown) by the contact hole H1 that is arranged at interlayer dielectric (not shown).
In addition, can also with this transistor adjacency, on same N-type semiconductor layer 12, form other high withstand voltage mos transistor (not shown).
Below, with reference to accompanying drawing, the trench gate type transistor and the manufacture method thereof of present embodiment described.
As shown in Figure 2, by to the surface doping of P type semiconductor substrate 10 after the N type impurity, make the semiconductor layer epitaxial growth, form N+ type semiconductor layer 11 and N-type semiconductor layer 12.Below, be monocrystalline silicon substrate with semiconductor substrate 10, N+ type semiconductor layer 11 and N-type semiconductor layer 12 describe for the monocrystalline silicon semiconductor layer, but are not limited to this.Then, on N-type semiconductor layer 12, form silicon oxide layer 13 by CVD method or thermal oxidation.And then, on silicon oxide layer 13, form resist layer R1 with peristome M1.Peristome M1 possesses a plurality of rectangles with minor face and long limit.
Then, as shown in Figure 3, be mask with resist layer R1, silicon oxide layer 13 is carried out etching, on silicon oxide layer 13, form peristome 13M.After removing resist layer R1, be hardmask (hard mask) with silicon oxide layer 13, N-type semiconductor layer 12 is carried out etching, form a plurality of grooves 14 accordingly with peristome 13M with minor face and long limit.This etching for example has been to use the dry ecthing of the etching gas that contains SF6.Therefore, bight 14C, the 14D of the bottom of groove 14 have circularity and form.The degree of depth of preferred groove 14 is about 1 μ m, and its long limit is about 50 μ m, and its minor face is about 0.5 μ m.The number of groove 14 is preferably about 10.Then, remove silicon oxide layer 13.
Then, as shown in Figure 4, the N-type semiconductor layer 12 in the groove 14 is carried out thermal oxidation, form silicon oxide layer 15A.The thickness of the silicon oxide layer 15A of preferred this moment is about 100nm.Silicon oxide layer 15A has reflected the bight 14C of the bottom of groove 14, the circularity of 14D, has circularity in this position and forms.
In addition, when forming other high withstand voltage mos transistor on same N-type semiconductor layer 12, silicon oxide layer 15A and this grid oxidation film form simultaneously.In addition, the thickness of silicon oxide layer 15A is based on the voltage endurance of MOS transistor and change.
Then, as shown in Figure 5, on silicon oxide layer 15A, form resist layer R2 with peristome M2.Peristome M2 becomes the regional upper shed in transistorized activate zone in N-type semiconductor layer 12.Here, transistorized activate zone is the zone that forms body layer 19.Below transistorized activate zone simply is called the activate zone.In other words, the resist layer R2 zone (deactivation zone) that do not become the activate zone from N-type semiconductor layer 12 is gone up, is that the bight 14C of the short side direction of groove 14 goes up outside groove 14 and extends.
Then, as shown in Figure 6, be mask with resist layer R2, silicon oxide layer 15A is carried out etching.Thus, formation will become the peristome 15M that expose in the zone of the N-type semiconductor layer 12 in activate zone.Then, remove resist layer R2.
Then, as shown in Figure 7, in groove 14, carry out thermal oxidation, and on this zone, form silicon oxide layer 15B by the N-type semiconductor layer of exposing at peristome 15M place 12 to silicon oxide layer 15A.
Like this, on the zone that becomes the activate zone of N-type semiconductor layer 12, form thin silicon oxide layer 15B (example of first grid dielectric film of the present invention).The thickness of preferred silicon oxide layer 15B is about 10nm.
On the other hand, on the zone that does not become the activate zone (deactivation zone), form the silicon oxide layer 15A thicker (example of second grid dielectric film of the present invention) than silicon oxide layer 15B in remaining mode.The thickness of preferred silicon oxide layer 15A is about 100nm.
Then, as shown in Figure 8, form the polysilicon layer 16P that covers silicon oxide layer 15A and silicon oxide layer 15B, it is carried out the doping of impurity.Preferred this impurity is N type impurity.
Then, as shown in Figure 9, the local overlapping areas of silicon oxide layer 15A on polysilicon layer 16P and thick forms resist layer R3.Then, be mask with resist layer R3, by polysilicon layer 16P is carried out etching, form from each groove 14 and extend to gate electrode 16 on the silicon oxide layer 15A.Join from the extension 16S of groove 14 interior outward extending gate electrodes 16 and thick silicon oxide layer 15A.In addition, each gate electrode 16 interconnects on the silicon oxide layer 15A outside the groove 14.This etching for example is a plasma etching.Then, remove resist layer R3.
Then, as shown in figure 10, in N-type semiconductor layer 12,, form P type body layer 19 by vertically to the injection of the ion on every side p type impurity of each groove 14.This body layer 19 joins with the silicon oxide layer 15B that approaches.And, inject N type impurity by long side direction to the surface ion of body layer 19 along each groove 14, form source layer 21.In addition, in order to adjust the activate and the Impurity Distribution of body layer 19 and source layer 21, preferably heat-treat.
Then, as shown in figure 11, form the interlayer dielectric 24 that covers silicon oxide layer 15A, 15B and gate electrode 16.On interlayer dielectric 24, form the wiring layer 25 that is connected with gate electrode 16 by the contact hole H1 that is arranged at interlayer dielectric 24.In addition, form source electrode 23 on interlayer dielectric 24, described source electrode 23 is connected with source layer 21 by the contact hole H2 that is arranged at silicon oxide layer 15B and interlayer dielectric 24.
In the transistor of so finishing, if apply current potential more than the threshold value from wiring layer 25 to gate electrode 16, then the surface of the body layer 19 of the sidewall of groove 17 is reversed to the N type, forms raceway groove (channel).Thus, can be between N-type semiconductor layer 12 that becomes source electrode 23, drain D and N+ type semiconductor layer 11 streaming current.
And, the silicon oxide layer 15A that joins by the extension 16S with gate electrode 16 is as thick gate insulating film performance function, in the extension 16S of gate electrode 16, gate electrode 16 and the distance of the bight 12C of N-type semiconductor layer 12 can be guaranteed for longer, therefore, the generation of grid leakage current can not only be prevented, and grid capacitance (constituting) can be reduced by gate electrode 16, silicon oxide layer 15A and N-type semiconductor layer 12.
And, formed thin silicon oxide layer 15B as gate insulating film owing to (form the zone of body layer 19) in transistorized activate zone, so, transistor having excellent characteristic (low threshold value, low on-resistance) can be obtained.
In addition, as modified embodiment of the present embodiment, can form drain electrode extension 26 and drain electrode 27 as shown in figure 12.Under this situation, before forming interlayer dielectric 24, on N-type semiconductor layer 12, form peristome 12H, in this peristome 12H, form dielectric film 28 then, bury drain electrode extension 26.Then, form interlayer dielectric 24, and form the through hole H3 that connects interlayer dielectric 24, in this through hole H3, form the drain electrode 27 that is connected with drain electrode extension 26.
In addition, as other variation of present embodiment, gate electrode 16 can be unlike interconnecting in the end of each groove 14 as shown in Figure 1, and shown in the vertical view of Figure 13, by each groove 14 separate, isolated formation.Other formation and Fig. 1 are same.Thus, to polysilicon layer 16P be etched to plasma etching the time because the area of the gate electrode 16 that is made of this polysilicon layer 16P reduces, so, can do one's utmost to suppress plasma damage to gate electrode 16.Thereby, can improve transistorized reliability.
[second execution mode]
With reference to accompanying drawing second execution mode of the present invention is described.Figure 14 is the vertical view that trench gate type transistor that embodiments of the present invention two are related to and manufacture method thereof describe.And (A)～Figure 26 of Figure 15 (A) is the cutaway view along the C-C line of Figure 14, and (B) of (B)～Figure 26 of Figure 15 is the cutaway view along the D-D line of Figure 14.In the following description, trench gate type transistor simply is called transistor.
As Figure 14 and shown in Figure 26, on P type semiconductor substrate 10, stack gradually and form N+ type semiconductor layer 111, N-type semiconductor layer 112, be formed with a plurality of grooves 117 on the surface of N-type semiconductor layer 12.Be that monocrystalline silicon substrate describes with semiconductor substrate 110 below, but be not limited to this.
In groove 117, form grid oxidation film 113B, be formed with groove oxide-film 116 (example of thick insulating film of the present invention) with joining at the end and the grid oxidation film 113B of groove 117.Groove oxide-film 116 has the thickness thicker than grid oxidation film 113B.In groove 117, cover gate oxide-film 113B ground is formed with gate electrode 118.Gate electrode 118 extends on the groove oxide-film 116 from the grid oxidation film 113B of groove 117.The gate electrode 118 that extends outside groove 117 is connected with wiring layer 125 by the contact hole H11 that is arranged at interlayer dielectric 124.And, be formed with body layer 119 and source layer 121 at the grid oxidation film 113B of the sidewall of the surface of N-type semiconductor layer 112 and groove 117 with joining.Source layer 121 is connected with source electrode 123 by the contact hole H12 that is arranged at grid oxidation film 113B and interlayer dielectric 124.
Like this, owing to formed thick groove oxide-film 116 at the extension of the groove 117 of gate electrode 118, so, not only can prevent the generation of grid leakage current, and can reduce grid capacitance.
Below, with reference to accompanying drawing, the transistor and the manufacture method thereof of present embodiment described.
As shown in figure 15, by to the surface doping of P type semiconductor substrate 110 after the N type impurity, make the semiconductor layer epitaxial growth, form N+ type semiconductor layer 111 and N-type semiconductor layer 112.Below, be that monocrystalline silicon substrate, N+ type semiconductor layer 111 and N-type semiconductor layer 112 are that the monocrystalline silicon semiconductor layer describes with semiconductor substrate 110, but be not limited to this.Then, on n type semiconductor layer 112, form silicon oxide layer 113A and silicon nitride film 114 in order.
Then, as shown in figure 16, on silicon nitride film 114, form resist layer R11 with peristome M11.By being mask with this resist layer R11, silicon oxide layer 113A and silicon nitride film 114, N-type semiconductor layer 112 are carried out etching, on N-type semiconductor layer 112, form the recess 115 of channel form.Then, remove resist layer R11.The etching of preferred this moment is the plasma etching that has utilized Cl2 gas.
Then, as shown in figure 17, form silicon oxide layer 116A by the CVD method on the silicon nitride film 114 in comprising recess 115.Then, as shown in figure 18, as the etching stop, silicon oxide layer 116A is carried out CMP (Chemical Mechanical Etching) handle with silicon nitride film 114.Thus, silicon oxide layer 116A is removed up to the surface identical with silicon nitride film 114, and the silicon oxide layer in the only remaining recess 115 becomes groove oxide-film 116.
Then, as shown in figure 19, the groove oxide-films 116 in the recess 115 are carried out wet etching,, preferably remove and go to the surperficial identical of its surface and silicon oxide layer 113A from the angle of planarization.Then, form resist layer R12 with peristome M12.Peristome M12 overlooks down a plurality of rectangles with minor face and long limit.The end of peristome M12 is positioned on the groove oxide-film 116.
Then, as shown in figure 20, be mask with resist layer R12, silicon oxide layer 113A, the silicon nitride film 114 in the peristome M12 removed in etching.Thus, in peristome M12, expose N-type semiconductor layer 112.
Then, as shown in figure 21, be mask with resist layer R12, N-type semiconductor layer 112 is carried out etching, form groove 117 accordingly with peristome M12.The degree of depth of groove 117 is preferably than the depth as shallow of recess 115.
The degree of depth of preferred groove 117 is about 1 μ m, and its long limit is about 50 μ m, and its minor face is about 0.5 μ m.In addition, the vertical direction thickness (being the degree of depth of recess 115) of preferred groove oxide-film 116 is about 1.2 μ m, and groove oxide-film 116 is about 2 μ m along the thickness of the long side direction of groove 117.In addition, the etching that is preferred for forming groove 117 has been to use the plasma etching of SF6 or C12 gas.
Then, after removing resist layer R12, silicon nitride film 114, reaching silicon oxide layer 113A, as shown in figure 22, carry out thermal oxidation, form grid oxidation film 113B on the surface of the N-type semiconductor layer 112 in comprising groove 117.The thickness of the Film Thickness Ratio groove oxide-film 116 of grid oxidation film 113B is thin.The thickness of preferred grid oxidation film 113B is about 20nm.
Then, as shown in figure 23, form the polysilicon layer 118P of cover gate oxide-film 113B and groove oxide-film 116, polysilicon layer 118P is carried out the doping of impurity.Preferred this impurity is N type impurity.
Then, as shown in figure 24, on polysilicon layer 118P, form resist layer R13 with the local overlapping areas of groove oxide-film 116.Then,, polysilicon layer 118P is carried out etching, form from each groove 117 and extend to gate electrode 118 on the groove oxide-film 116 by being mask with resist layer R13.Gate electrode 118 interconnects on the groove oxide-film 116 outside the groove 117.Preferred this etching is the plasma etching that has utilized Cl2 gas.Then, remove resist layer R13.
Then, as shown in figure 25, in N-type semiconductor layer 112,, form P type body layer 19 by vertically to the injection of the ion on every side p type impurity of each groove 17.And, inject N type impurity by long side direction to the surface ion of body layer 119 along each groove 117, form N type source layer 121.In addition, in order to adjust the activate and the Impurity Distribution of body layer 119 and source layer 121, preferably heat-treat.
Then, as shown in figure 26, form the interlayer dielectric 124 of cover gate oxide-film 113B and gate electrode 118.On interlayer dielectric 124, form the wiring layer 125 that is connected with gate electrode 118 by the contact hole H11 that is arranged at interlayer dielectric 124.In addition, on interlayer dielectric 124, form the source electrode 123 that is connected with source layer 121 by the contact hole H12 that is arranged at grid oxidation film 113B and interlayer dielectric 124.
In the transistor of so finishing, if apply current potential more than the threshold value from wiring layer 125 to gate electrode 118, then the surface of the body layer 119 of the sidewall of groove 117 is reversed to the N type, forms raceway groove.Thus, can be between N-type semiconductor layer 112 that becomes source electrode 123, drain D and N+ type semiconductor layer 111 streaming current.
And, by forming groove oxide-film 116, in the extension 118S of gate electrode 118, gate electrode 118 and the distance of the bight 112C of N-type semiconductor layer 112 can be guaranteed for longer, therefore, not only can prevent the generation of grid leakage current, and can reduce grid capacitance (is that upper electrode, grid oxidation film 113B and groove oxide-film 116 are that capacitor insulating film, N-type semiconductor layer 112 are lower electrode with gate electrode 118).
In addition, as modified embodiment of the present embodiment, can form drain electrode extension 126 and drain electrode 127 as shown in figure 27.Under this situation, before forming interlayer dielectric 124, on N-type semiconductor layer 112, form peristome 112H, in this peristome 112H, form dielectric film 128 then, bury drain electrode extension 126.Afterwards, form interlayer dielectric 124, and form the through hole H13 that connects interlayer dielectric 124, in this through hole H13, form the drain electrode 127 that is connected with drain electrode extension 126.
In addition, as other variation of present embodiment, gate electrode 118 can be unlike interconnecting on groove oxide-film 116 as shown in Figure 14, and shown in the vertical view of Figure 28, by each groove 117 separate, isolated formation.Other formation and Figure 14 are same.Thus, to polysilicon layer 118P be etched to plasma etching the time because the area of the gate electrode 118 that is made of this polysilicon layer 118P reduces, so, can suppress plasma damage to gate electrode 118.Thereby, can improve transistorized reliability.
And, in order to improve transistorized reliability, can be on the basis of the structure of Figure 28, as the vertical view of Figure 29, at groove oxide-film 116 also by each groove 117 (i.e. each gate electrode 118 of Fen Liing) separate, isolated formation.Thus, the crystal defect of N-type semiconductor layer 112 takes place in the thermal expansion of groove oxide-film 116 in the time of can suppressing because of heat treatment.
[the 3rd execution mode]
With reference to accompanying drawing the 3rd execution mode of the present invention is described.Figure 30 is the vertical view that transistor that the 3rd execution mode of the present invention is related to and manufacture method thereof describe.And 40 (A) of (A)～figure of Figure 31 are the cutaway views along the E-E line of Figure 30, and (B) of (B)～Figure 40 of Figure 31 is the cutaway view along the F-F line of Figure 30.In Figure 30～Figure 40, given prosign to the structural element identical with Figure 14～Figure 29.In this transistor, as shown in figure 40, become the structure that replaces groove oxide-film 116 and use locos oxide film 133L.Other structures are basic identical with second execution mode.
Below, with reference to accompanying drawing, the transistor and the manufacture method thereof of present embodiment described.
As shown in figure 31, same with second execution mode, on semiconductor substrate 110, form N+ type semiconductor layer 111 and N-type semiconductor layer 112.Then, on N-type semiconductor layer 112, form silicon oxide layer 133A.Then, on silicon oxide layer 133A, form resist layer R14 with peristome M14.
Then, shown in figure 32, be mask with resist layer R14, the silicon oxide layer 133A in the peristome M14 is carried out etching, be removed.Thus, in peristome M14, expose N-type semiconductor layer 112.
Then, as shown in figure 33, be mask with resist layer R14, N-type semiconductor layer 112 is carried out etching, form groove 134.
Then, after removing resist layer R14 and silicon oxide layer 133A, as shown in figure 34,, in groove 134, form grid oxidation film 133B by thermal oxidation.The thickness of preferred grid oxidation film 133B is about 20nm.
Then, as shown in figure 35,, cover silicon oxide layer 133B ground and form silicon nitride film 135, this silicon nitride film 135 is carried out etching by the CVD method.Thus, silicon nitride film 135 is remained on the grid oxidation film 133B of sidewall of groove 134.
Then, as shown in figure 36, by being the thermal oxidation of mask, form the locos oxide film 133L of end in bottom, groove 134 outsides of covering groove 134 with silicon nitride film 135.The thickness of the grid oxidation film 133B that the Film Thickness Ratio of locos oxide film 133L is original is thick.
Then, as shown in figure 37, form the polysilicon layer 136P of cover gate oxide-film 133B and locos oxide film 133L, it is carried out the doping of impurity.Preferred this impurity is N type impurity.
Afterwards, as shown in figure 38, on polysilicon layer 136P, form resist layer R15 with the local overlapping areas of locos oxide film 133L.Then,, polysilicon layer 136P is carried out etching, form from each groove 134 and extend to gate electrode 136 on the locos oxide film 133L outside it by being mask with resist layer R15.Gate electrode 136 interconnects on the locos oxide film 133L outside the groove 134.Then, remove resist layer R15.
Then, as shown in figure 39, similarly form body layer 119 and source layer 121 at the surface and second execution mode of N-type semiconductor layer 112.
Then, as shown in figure 40, form the interlayer dielectric 124 that covers locos oxide film 133L and gate electrode 136.On interlayer dielectric 124, form the wiring layer 125 that is connected with gate electrode 136 by the contact hole H11 that is arranged at interlayer dielectric 124.And, on interlayer insulating film 124, form the source electrode 123 that is connected with source layer 121 by the contact hole H12 that is arranged at interlayer dielectric 124 and locos oxide film 133L.
In the transistor of so finishing, if same, apply current potential more than the threshold value to gate electrode 136 from wiring layer 125 with second execution mode, then the surface of the body layer 119 of the sidewall of groove 134 is reversed to the N type, forms raceway groove.Thus, can be between N-type semiconductor layer 112 that becomes source electrode 123, drain D and N+ type semiconductor layer 111 streaming current.In addition,, can remedy the thickness of grid oxidation film 133B, realize the raising of reliability, but under the situation of the low thresholding of expectation, can remove silicon nitride film 135 by sidewall residual silicon nitride film 135 at groove 134.
And, by forming locos oxide film 133L, in the extension 136S of gate electrode 136, gate electrode 136 and the distance of the bight 112C of N-type semiconductor layer 112 can be guaranteed for longer, therefore, the generation of grid leakage current can not only be prevented, and grid capacitance (is that upper electrode, grid oxidation film 133B and locos oxide film 133L are that capacitor insulating film, N-type semiconductor layer 112 are lower electrode with gate electrode 136) can be reduced.
In addition, as modified embodiment of the present embodiment, can be same with the situation shown in Figure 27 of second execution mode, form drain electrode extension 126 and drain electrode 127.Under this situation, before forming interlayer dielectric 124, on N-type semiconductor layer 112, form peristome 112H, in this peristome 112H, form dielectric film 128 then, bury drain electrode extension 126.Afterwards, form interlayer dielectric 124, and form the through hole H13 that connects interlayer dielectric 124, in this through hole H13, form the drain electrode 127 that is connected with drain electrode extension 126.
In addition, as other variation of present embodiment, gate electrode 136 can be same with the situation shown in Figure 28 of second execution mode, by each groove 134 separate, isolated formation.Under this situation, also can access and the equal effect of second execution mode.
[the 4th execution mode]
With reference to accompanying drawing the 4th execution mode of the present invention is described.It is same with Figure 30 that formation overlooked in this transistorized summary.
With reference to the accompanying drawings, transistor and the manufacture method thereof to present embodiment describes.
47 (A) of (A)～figure of Figure 41 are the cutaway views along the E-E line of Figure 30, and (B) of (B)～Figure 47 of Figure 41 is the cutaway view along the F-F line of Figure 30.In Figure 30, Figure 41～Figure 47, to giving prosign with the same structural element of Figure 30～Figure 40.
As shown in figure 41, similarly on semiconductor substrate 110, form N+ type semiconductor layer 111 and N-type semiconductor layer 112 with second execution mode.On N-type semiconductor layer 112, form silicon oxide layer 141, as hardmask with peristome 141M.The thickness of preferred silicon oxide layer 141 is about 100nm.
Then, silicon oxide layer 141 as mask, is carried out etching to N-type semiconductor layer 112, the corresponding groove 144 that forms with minor face and long limit with peristome 141M.Then, remove silicon oxide layer 141.
Then, as shown in figure 42, thermal oxidation is carried out on the surface of the N-type semiconductor layer 112 in the groove 144, form grid oxidation film 145.The preferred thickness of grid oxidation film 145 at this moment is about 20nm.Then, connect grid oxidation film 145, inject impurity such as argon to N-type semiconductor layer 112 medium dip ions.Inject in this angle-tilt ion,, the horizontal plane of semiconductor substrate 110 is carried out the ion injection with the incidence angles of about 10 degree～45 degree preferably from along the direction on the long limit of groove 144 with along the direction of minor face.More preferably the horizontal plane of the relative semiconductor substrate 10 of this incidence angle is about 30 degree.In addition, be under the situation of argon at impurity, the dosage that preferred ion is injected is 1 * 1016/cm2, acceleration can be about 40KeV.
For such ion injects, for example after the long side direction along groove 144 has carried out the injection of first angle-tilt ion, carry out second angle-tilt ion to direction in contrast and inject.Then, after the short side direction along groove 144 had carried out the injection of the 3rd angle-tilt ion, the direction that Xiang Yuqi is opposite was carried out the 4th angle-tilt ion and is injected.In addition, as the order outside above-mentioned, can carry out any or whole of first～the 4th angle-tilt ion injection simultaneously.
Inject by first and second angle-tilt ion, in the side of groove 144 and the surface formation impurity implanted layer of the N-type semiconductor layer 112 of bottom surface, the N-type semiconductor layer 112 that is connected with groove 144.On the other hand, inject the N-type semiconductor layer 112 above the side of groove 144 and form the impurity implanted layer with the surface of the N-type semiconductor layer 112 of groove 144 adjacency according to the 3rd and the 4th angle-tilt ion.That is, the 3rd and the 4th angle-tilt ion is injected, and does not import impurity to the below and the bottom surface of the side of groove 144.
Then, by carrying out thermal oxidation, form grid oxidation film 145.Here, in operation before, have only ion to inject the zone of impurity by the speedup oxidation.Thus, shown in Figure 43 (A), because in the grid oxidation film 145, the side-walls of the bottom of long side direction, the short side direction in the groove 144 in N-type semiconductor layer 112 lip-deep zones, in the groove 144, fully injected ion, so, thick oxide-film become.
On the other hand, shown in Figure 43 (B), in the grid oxidation film 145, the top along the sidewall of long side direction of groove 144 (be the peristome of groove 144 near), owing to fully injected ion, so become thick oxide-film, but do not become thick oxide-film than its side-walls by the bottom.The thickness in zone that becomes thick oxide film in the grid oxidation film 145 is more about 10%～150% than other regional thickness, preferably approximately more than 30%.
Then, as shown in figure 44, form polysilicon layer 146P, it is carried out the doping of impurity according to the mode of cover gate oxide-film 145.Preferred this impurity is N type impurity.
Then, as shown in figure 45, grid oxidation film 145 local overlapping areas on polysilicon layer 146P and thick form resist layer R16.Then,, polysilicon layer 146P is carried out etching, form from each groove 144 and extend to gate electrode 146 on the grid oxidation film 145 outside it by being mask with resist layer R16.The gate electrode 136 of gate electrode 146 and the 3rd execution mode is same, interconnects on the grid oxidation film outside the groove 144 145.Then, remove resist layer R16.
Then, same with second execution mode as shown in figure 46, in N-type semiconductor layer 112, around each groove 144, form body layer 119 and source layer 121.And, as shown in figure 47, form the interlayer dielectric 124 of cover gate oxide-film 145 and gate electrode 146.On interlayer dielectric 124, form the wiring layer 125 that is connected with gate electrode 146 by the contact hole H11 that is arranged at interlayer dielectric 124.And, on interlayer insulating film 124, form the source electrode 123 that is connected with source layer 121 by the contact hole H12 that is arranged at grid oxidation film 145 and interlayer dielectric 124.
In the transistor of so finishing, if same, apply current potential more than the threshold value to gate electrode 146 from wiring layer 125 with second execution mode, then the surface of the body layer 119 of the sidewall of groove 144 is reversed to the N type, forms raceway groove.Thus, can be between N-type semiconductor layer 112 that becomes source electrode 123, drain D and N+ type semiconductor layer 111 streaming current.
And, because the grid oxidation film 145 on the sidewall of short side direction in the groove 144 becomes thick oxide-film, so, in the extension 146S of gate electrode 146, gate electrode 146 and the distance of the bight 112C of N-type semiconductor layer 112 can be guaranteed for longer, the generation of grid leakage current can not only be prevented, and grid capacitance (constituting) can be reduced by gate electrode 146, grid oxidation film 145 and N-type semiconductor layer 112.Equally, because near the grid oxidation film of locating along the top of the sidewall of the long side direction of groove 144 (be the peristome of groove 144) also becomes thick oxide-film, so, can prevent generation, the reduction grid capacitance of grid leakage current more reliably.
On the other hand, because thinner along the grid oxidation film 145 of the lower sidewall of the long side direction of groove 144, so, transistorized threshold value can be reduced.
In addition, as modified embodiment of the present embodiment, can be same with the situation shown in Figure 27 of second execution mode, form drain electrode extension 126 and drain electrode 127.Under this situation, before forming interlayer dielectric 124, on N-type semiconductor layer 112, form peristome 112H, in this peristome 112H, form dielectric film 128, bury drain electrode extension 126.Afterwards, form interlayer dielectric 124, and form the through hole H13 that connects interlayer dielectric 124, in this through hole H13, form the drain electrode 127 that is connected with drain electrode extension 126.
In addition, as other variation of present embodiment, gate electrode 146 can be same with the situation shown in Figure 28 of second execution mode, by each groove 144 separate, isolated formation.Under this situation, also can access and the equal effect of second execution mode.
In addition, the present invention is not limited to above-mentioned execution mode, can change in the scope that does not break away from its purport certainly.For example, the transistor of N channel-type is illustrated, but changes to opposite conductivity type, also the present invention can be applied in the P channel transistor by conductivity type with source layer, body layer etc.
In addition, the present invention can also be applied to IGBT with trench gate type etc. and buries in the device of gate electrode.
Claims (2)
1. trench gate type transistor is characterized in that possessing:
Semiconductor layer;
The gate insulating film that in being formed at the groove of described semiconductor layer, forms;
Join and form at the end of described groove and described gate insulating film, have thick insulating film than the thickness of described gate insulator thickness;
Cover the described gate insulating film in the described groove and extend to gate electrode on the described thick insulating film;
Be formed on the near surface of described semiconductor layer, the body layer that joins with the described gate insulating film of the sidewall of described groove,
Described thick insulating film is the separatory trench insulating film of element,
Described trench insulating film forms than described ditch groove depth ground.
2. trench gate type transistor according to claim 1 is characterized in that,
Described thick insulating film is a locos oxide film.
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| JP255090/2007 | 2007-09-28 | ||
| JP2007255090A JP4890407B2 (en) | 2007-09-28 | 2007-09-28 | Trench gate type transistor and manufacturing method thereof |
| JP2007255089A JP2009088186A (en) | 2007-09-28 | 2007-09-28 | Trench gate type transistor and manufacturing method thereof |
| JP255089/2007 | 2007-09-28 | ||
| PCT/JP2008/068115 WO2009041742A1 (en) | 2007-09-28 | 2008-09-26 | Trench gate type transistor and method for manufacturing the same |
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| JP6340200B2 (en) * | 2014-01-27 | 2018-06-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US9577073B2 (en) | 2014-12-11 | 2017-02-21 | Infineon Technologies Ag | Method of forming a silicon-carbide device with a shielded gate |
| JP2016162788A (en) | 2015-02-27 | 2016-09-05 | ソニー株式会社 | Imaging device, imaging apparatus, and manufacturing device and method |
| JP7176206B2 (en) * | 2018-03-14 | 2022-11-22 | 富士電機株式会社 | Silicon carbide semiconductor device and silicon carbide semiconductor circuit device |
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| US20020167046A1 (en) * | 2000-01-14 | 2002-11-14 | Takaaki Aoki | Semiconductor device and method for manufacturing the same |
| CN1726587A (en) * | 2002-12-14 | 2006-01-25 | 皇家飞利浦电子股份有限公司 | Manufacture of a trench-gate semiconductor device |
| US20060244053A1 (en) * | 2005-04-28 | 2006-11-02 | Denso Corporation | Trench gate type semiconductor device |
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| JP2001015733A (en) * | 1999-07-02 | 2001-01-19 | Fuji Electric Co Ltd | Semiconductor device and manufacture thereof |
| JP2001358338A (en) * | 2000-06-14 | 2001-12-26 | Fuji Electric Co Ltd | Trench gate type semiconductor device |
| JP4178789B2 (en) * | 2001-12-18 | 2008-11-12 | 富士電機デバイステクノロジー株式会社 | Semiconductor device and manufacturing method thereof |
| JP4219630B2 (en) * | 2002-07-17 | 2009-02-04 | 株式会社豊田中央研究所 | Trench gate type semiconductor device and manufacturing method thereof |
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| US20020167046A1 (en) * | 2000-01-14 | 2002-11-14 | Takaaki Aoki | Semiconductor device and method for manufacturing the same |
| CN1726587A (en) * | 2002-12-14 | 2006-01-25 | 皇家飞利浦电子股份有限公司 | Manufacture of a trench-gate semiconductor device |
| US20060244053A1 (en) * | 2005-04-28 | 2006-11-02 | Denso Corporation | Trench gate type semiconductor device |
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