JP4219630B2 - Trench gate type semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a trench gate type semiconductor device and a manufacturing method thereof.
[0002]
[Prior art and problems to be solved by the invention]
First Prior Art FIG. 26 is a plan view of a semiconductor device that is substantially the same as the trench gate type semiconductor device described in Japanese Patent Application Laid-Open No. 2001-15733. FIG. 27 is a sectional view taken along line AA in FIG. FIG. 28 is a cross-sectional view taken along line BB in FIG. FIG. 29 is a perspective view of the configuration near the range L in FIG. 26 in the semiconductor device. In this perspective view, the wiring layer and the gate insulating film are not shown.
[0003]
In this specification, for the sake of clarity, the vertical direction in FIG. 26 is referred to as “depth direction”, the vertical direction is referred to as “width direction”, and the horizontal direction is referred to as “depth direction”. Further, two ends (end surfaces) in the depth direction of the trench gate electrode 224 or the trench 223 are “upper end (upper surface)” and “lower end (lower surface)”, and two ends (end surfaces) in the width direction are “right end (right side surface)”. “Left end (left side surface)”, and two ends (end surfaces) in the depth direction are referred to as “front end (front side surface)” and “rear end (rear side surface)”.
[0004]
27 and 28, the semiconductor device includes a semiconductor layer 220 in which a trench 223 is formed, gate insulating films 230a and 230b formed along the wall surface of the trench 223, and a predetermined height inside the trench. A trench gate electrode 224 buried through the gate insulating films 230a and 230b, gate lead portions 228a and 228b connected to the trench gate electrode 224, and a wiring layer 222 in contact with the gate lead portion 228b are provided.
[0005]
Here, the gate lead-out portion 228a inside the trench is provided at an end portion (front end portion) in the trench depth direction as well shown in FIGS. 27 to 29, particularly FIG. 29 which is a perspective view. It is in contact with the trench side surface (right side surface, left side surface, front side surface) that divides the portion. The gate lead-out portion 228b outside the trench is formed so as to extend in the width direction on the gate lead-out portion 228a inside the trench and above the top surface of the semiconductor layer 220.
Therefore, the trench upper corner portion 270 extending in the trench depth direction and the trench upper corner portion 271 extending in the trench width direction serve as a boundary between the top surfaces of the semiconductor layer 220 on which the gate lead portion 228b is located, It is in a state of being covered in contact with the portions 228a and 228b.
[0006]
In a trench gate type semiconductor device, generally, an insulating film covering the upper and lower corner portions of the trench is thinner than an insulating film covering the bottom and side surfaces of the trench. This is because there are a plurality of plane orientations in the upper corner and lower corner of the trench, and the deposition rate of the insulating film becomes slower than the insulating film covering the bottom and side surfaces of the trench. . In particular, since the upper corner portion of the trench is an acute corner, the electric field concentration is remarkable.
Therefore, as described above, when the trench upper corner portions 270 and 271 are covered with the gate lead portions 228a and 228b, due to the influence of the voltage applied to the gate lead portions 228a and 228b through the wiring layer 222, There is a problem in that electric field concentration occurs in a portion of the thin insulating film covering the upper corner portions 270 and 271 of the trench, and dielectric breakdown is likely to occur.
[0007]
Therefore, in the semiconductor device described in the above publication, as shown in FIG. 27, the insulating films 230b and 231 covering the trench upper corner portions 270 and 271 are intentionally formed as compared with the gate insulating film 230a covering the bottom surface of the trench 223. By forming it thickly, it is going to make it hard to produce the dielectric breakdown in the location of the insulating films 230b and 231.
[0008]
In order to manufacture the semiconductor device of the first prior art described above, there is a problem that high technology is required. That is, in order to make the thicknesses of the gate insulating film 230a covering the bottom surface of the trench 223 and the insulating films 230b and 231 covering the trench upper corner portions 270 and 271 different as in this semiconductor device, the bottom surface of the trench 223 is formed. It is considered that a process of etching only the gate insulating film 230a to be covered, or a process of arranging a mask so as not to etch only the gate insulating film 230a is necessary. However, advanced techniques are required to appropriately perform operations such as etching, mask arrangement, and photosensitive material application in the photolithography process as described above near the bottom surface of the deep and narrow trench 223.
[0009]
In addition, in order to manufacture the semiconductor device of the first prior art, there is a problem that the manufacturing process becomes complicated. In the publication of the first prior art, in order to make the thicknesses of the gate insulating film 230a covering the bottom surface of the trench 223 and the insulating films 230b and 231 covering the trench upper corner portions 270 and 271 different, , Formation of a polysilicon layer for an etching mask, local etching of the polysilicon layer, removal of the polysilicon layer, local etching of the first insulating film, formation of the second insulating film, etc. A process is disclosed. Even if the manufacturing process can be further simplified, it is considered that a plurality of processes need to be performed after the gate insulating film is first formed.
[0010]
(Second Prior Art) FIG. 31 is a cross-sectional view of a trench gate type semiconductor device described in JP-A-7-326738. Although not disclosed in the above publication, it is assumed that the cross-sectional view of FIG. 31 is a cross-sectional view taken along line AA of the semiconductor device as shown in FIG.
In this semiconductor device, the width of the electrode layer 334 located at substantially the same height as the trench upper corner portion 370 is made smaller than the width of the trench 323 so that the trench upper corner portion 370 is not covered with the electrode layer 334. As a result, it is difficult to cause dielectric breakdown at the location of the insulating film 330 covering the upper corner portion 370 of the trench. In FIG. 29, reference numeral 320 denotes a semiconductor layer, and reference numeral 326 denotes an interlayer insulating film.
[0011]
According to the structure of the semiconductor device of the second prior art, the contact area between the electrode layer 334 and the wiring layer 322 is narrower than the width of the trench 323 as shown in FIG. Is small. Therefore, there is a problem that the contact resistance between the electrode layer 334 and the wiring layer 322 becomes high.
[0012]
The first object of the present invention is to realize a trench gate type semiconductor device in which the contact resistance between the gate lead-out portion and the wiring layer is small and the dielectric breakdown at the upper corner portion of the trench hardly occurs.
It is a second object of the present invention to realize a trench gate type semiconductor device that can be manufactured relatively easily while preventing dielectric breakdown at the upper corner of the trench.
The present invention seeks to achieve at least one of the above objects.
[0013]
[Means for solving the problem, operation and effect]
[1] A trench gate type semiconductor device according to one aspect embodying the present invention includes:pluralA semiconductor layer in which a trench is formed, a gate insulating film formed along the trench wall surface, a trench gate electrode embedded through the gate insulating film up to a predetermined height inside the trench,An insulating portion covering one first trench upper corner portion of the trench upper corner portion extending in the trench depth direction;1st trench upper cornerPartDistanceBeenAndIt is connected to both of the adjacent trench gate electrodes, covers the other second trench upper corner portion of the trench upper corner portion extending in the trench depth direction, and covers the top surface of the semiconductor layer located between the two adjacent trenches. TheWiring that is in contact with the gate lead-out portion and at least the gate lead-out portion above the top surface of the semiconductor layerLayerI have.
[0014]
[2] Another embodiment of the trench gate type semiconductor device embodying the present invention is the insulating partCovers the end portion on the first trench upper corner portion side of the trench upper corner portion extending in the trench width direction. The gate lead-out portion covers an end portion of the second trench upper corner portion of the trench upper corner portion extending in the trench width direction.
[0016]
  In the semiconductor device of [1], the gate lead-out portion is a trench upper corner portion extending in the trench depth direction.OneAway fromIsing. Therefore, the electric field concentration part can be reduced as compared with the structure in which the trench upper corner portion extending in the trench depth direction is covered in contact with the gate lead-out portion as in the first prior art.
  In the semiconductor device of [2], the gate lead-out portion isExtends in the trench width directionTrench upper cornerOf the first trench upper corner portion side endAway fromHas been.Therefore, like the first prior art,Extends in the trench width directionCompared with the structure in which the upper corner portion of the trench is covered in contact with the gate lead-out portion, the electric field concentration site can be reduced.
  For this reason, according to the semiconductor device of [1] or [2], the upper corner portion of the trench is covered.InsulationIt is possible to make it difficult for dielectric breakdown to occur. Therefore, the reliability of the gate insulating film can be improved.
[0017]
In the semiconductor devices [1] and [2], the wiring layer is in contact with at least the gate lead-out portion above the top surface of the semiconductor layer. For this reason, since the wiring layer and the gate lead portion can be brought into contact with each other in a wide area above the top surface of the semiconductor layer, the width of the contact area between the electrode layer and the wiring layer as in the second prior art described above can be reduced. Compared with the structure narrower than the trench width, the contact area between the wiring layer and the gate lead-out part is large.
Thus, it is easy to reduce the contact resistance.
[0018]
Therefore, according to the invention described in [1] or [2], it is possible to realize a trench gate type semiconductor device in which the reliability of the gate insulating film is improved while reducing the contact resistance between the gate lead portion and the wiring layer. Can do.
[0019]
[3] In the above [1] or [2],InsulationIs formed from above the top surface of the semiconductor layer to above the trench gate electrode so as to cover at least a part of the upper corner portion of the first trench.ingIt is preferable.
[0020]
The insulating film formed integrally with the gate oxide film along the top surface of the semiconductor layer and the side surface of the trench covers the trench upper corner portion first, and further covers with the insulating portion described above, the insulation at the trench upper corner portion is obtained. Destruction can be made more difficult to occur. Therefore, the reliability of the gate insulating film can be further improved. Of course, when there is no insulating film formed integrally with such a gate insulating film, the upper corner portion of the trench may be covered with the insulating portion alone. Also in this case, it is possible to sufficiently prevent dielectric breakdown.
[0021]
The insulating portion is formed from above the top surface of the semiconductor layer to above the trench gate electrode so as to cover at least a part of the upper corner portion of the trench. That is, after the trench gate electrode is formed inside the trench, the insulating portion is formed from the upper surface of the semiconductor layer to the upper portion of the trench gate electrode. Therefore, an insulating portion can be formed from above the top surface of the semiconductor layer, which is a wide region with few steps, above the trench gate electrode. For this reason, unlike the first prior art described above, it is not necessary to perform work requiring advanced techniques such as etching and mask arrangement in the vicinity of the bottom of a generally deep and narrow trench. Thus, it is possible to realize a structure that hardly causes dielectric breakdown at the upper corner portion of the trench.
[0022]
[4] In the above [1] to [3], the insulating portion is preferably formed integrally with an interlayer insulating film located between the semiconductor layer and the wiring layer.
In the case of manufacturing this structure, since the insulating portion can be formed accompanying the formation of the interlayer insulating film, the manufacturing process is greatly simplified compared to the complicated manufacturing method of the first prior art described above, It is possible to realize a structure that makes it difficult for dielectric breakdown to occur in the upper corner portion of the trench. Moreover, the effect that it can implement | achieve more favorable insulation is also acquired by forming integrally with an interlayer insulation film.
[0023]
[5] In the above [1] to [4], it is preferable that the insulating portion is formed thicker than the gate insulating film.
In this case, dielectric breakdown at the upper corner portion of the trench can be made less likely to occur. Therefore, the reliability of the gate insulating film can be further improved.
[0024]
Up[1]-[5]Of semiconductor devicesIn the semiconductor layer, a plurality of trenches are formed, and the gate lead portion is adjacent to each other.2Are commonly connected to trench gate electrodes embedded in two trenches.The GetSince the gate lead portion can be effectively used, it is easy to realize a structure in which the contact area between the gate lead portion and the wiring layer is increased.
[0025]
Up[1]-[5]Of semiconductor devicesIn the semiconductor layer, a plurality of trenches are formed, and the gate lead portion is adjacent to each other.2Between the two trenches.The next toTogether2Since the gate lead portion and the wiring layer can be brought into contact with each other in a wide region above the semiconductor layer between the two trenches, the contact area can be sufficiently increased and the contact resistance can be sufficiently reduced.
[0026]
  Further, the claims embodying the present invention6~9According to the method for manufacturing a trench gate type semiconductor device described in the above, a trench gate type semiconductor device in which the contact resistance between the gate lead portion and the wiring layer is small and the reliability of the gate insulating film is improved by a relatively simple manufacturing process. can do.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
First Embodiment FIG. 1 is a plan view of a trench gate type semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. FIG. 3 is a cross-sectional view taken along line BB in FIG. FIG. 4 shows a cross-sectional view taken along line CC in FIG. FIG. 5 is a cross-sectional view taken along the line DD in FIG. 6 to 8 are perspective views of the configuration in the vicinity of the range L in FIG. FIG. 6 is a perspective view after the trench gate electrode 24 and the gate lead portions 28a and 28b are formed. FIG. 7 shows a perspective view after the interlayer insulating film 26 is formed. FIG. 8 is a perspective view after the wiring layer 22 is formed (completed state).
[0028]
As shown in the perspective view of FIG. 8, this semiconductor device includes a semiconductor layer 20. The semiconductor layer 20 is formed with a part of a structure for operating the semiconductor device as, for example, a MOSFET, IGBT, MOS gate type thyristor, or the like. If this semiconductor device is a power MOSFET, for example, a drain region, a drift region, a body region, a source region, and the like are formed in the semiconductor layer 20.
[0029]
As shown in FIG. 1 and the like, a plurality of trenches 23 that are elongated in the depth direction are formed in the semiconductor layer 20 so as to be arranged in the width direction at a predetermined interval. The trench 23 is formed from the top surface of the semiconductor layer 20 to a position reaching a predetermined depth in the depth direction, as shown in FIG.
In the trench 23, as shown in FIG. 4 and the like, a gate insulating film 30 made of a silicon oxide film is formed along the trench wall surface (bottom surface and side surface). The gate insulating film 30 is connected to an insulating film 31 formed along the top surface of the semiconductor layer 20 (hereinafter referred to as “top surface insulating film” as appropriate). That is, the insulating films 30 and 31 are formed over the top surface of the semiconductor layer 20 and the entire wall surface of the trench 23. In addition, illustration of these insulating films 30 and 31 is abbreviate | omitted in the perspective view of FIGS.
Further, as shown in FIG. 4 and FIG. 8 and the like, the trench gate electrode 24 is buried in the trench 23 up to a predetermined height via the gate insulating film 30. The trench gate electrode 24 is made of polysilicon.
[0030]
As shown in FIG. 2 which is a cross-sectional view along the depth direction of the trench gate electrode 24, gate lead portions 28 a and 28 b are connected to the end portions (front end portion and rear end portion) of the trench gate electrode 24 in the depth direction. ing. This structure can also be seen from FIG. 5 which is a cross-sectional view at the end of the trench gate electrode 24 in the depth direction, or FIG. 6 which is a perspective view. Similarly to the trench gate electrode 24, the gate lead portion 28 is made of polysilicon.
[0031]
As shown in FIGS. 2, 5, and 6, the gate lead portion 28 includes a gate lead portion 28 a inside the trench 23 (hereinafter referred to as “internal lead portion” as appropriate) and a gate lead portion 28 b outside the trench 23 ( (Hereinafter referred to as “external drawer portion”). As shown in FIG. 6, the internal lead portion 28 a extends locally from the trench gate electrode 24, specifically, from the end in the depth direction of the electrode 24 toward the outside of the trench 23. . More specifically, the trench gate electrode 24 also extends locally from the top surface at the end in the depth direction.
[0032]
More specifically, in FIG. 6, when one of the internal drawer portions 28 a located near the upper end of the trench is taken as an example, the internal drawer portion K is spaced from the trench upper corner portion 70 b extending in the depth direction. It is placed and placed. Therefore, the trench upper corner portion 70b is not covered with the inner lead portion K. Along with this, the trench upper corner portion 71 extending in the width direction is not covered by the inner lead portion K. This is different from the structure shown in FIG. 29 as the first prior art (a structure in which the gate lead-out portion 228 covers the entire trench upper corner portions 270 and 271). According to the structure of the present embodiment, the electric field concentration site can be reduced as compared with the structure of the first prior art.
[0033]
As shown in FIG. 6 and the like, the external lead portion 28b is connected to the internal lead portion 28a and extends in a flat plate shape onto the semiconductor layer 20 (specifically, the top surface insulating film).
Further, the gate lead-out portion 28 is commonly connected to the trench gate electrode 24 embedded in the two adjacent trenches 23. In addition, the semiconductor layer 20 is disposed across two adjacent trenches 23. The gate lead-out portions 28a and 28b are substantially U-shaped when viewed in the cross section of FIG. 5, and cover the two adjacent trench upper corner portions 70c and 70d.
[0034]
As described above, since the gate lead portion 28 is commonly connected to the two trench gate electrodes 24, the gate lead portion 28 can be effectively used. Further, the gate lead portion 28 is disposed across the semiconductor layer 20 located between two adjacent trenches 23, and a flat plate-like external lead portion 28b located above the top surface of the semiconductor layer 20 and a wiring described later. Since the layers can be brought into contact with a sufficiently large area, the contact resistance can be sufficiently lowered.
[0035]
As shown in FIG. 7 and the like, an interlayer insulating film 26 is stacked on the semiconductor layer 20 (specifically, the top surface insulating film) and the trench gate electrode 24. 2 to 5 also show this structure. However, as shown in FIG. 7, the interlayer insulating film 26 is not laminated on the top surface of the flat lead-out portion 28b, and a contact hole 27 is formed.
[0036]
As shown in FIG. 5, the insulating portion 26a constituting a part of the interlayer insulating film 26 covers the trench upper corner portions 70a and 70b extending in the depth direction at a position separated from the inner lead portion 28a. These trench upper corner portions 70 a and 70 b are corner portions formed at the boundary between the right side surface or the left side surface of the trench 23 and the top surface of the semiconductor layer 20. The insulating portion 26 a is stacked on the semiconductor layer 20 (specifically, the top surface insulating film 31) and the trench gate electrode 24. The insulating portion 26a is substantially U-shaped when viewed in the cross section of FIG.
As shown in FIG. 3, the insulating portion 26 a also covers the trench upper corner portion 71 formed at the boundary between the end surface (front side surface and rear side surface) of the trench 23 in the depth direction and the top surface of the semiconductor layer 20. .
In this embodiment, the corner insulating layer is formed by the gate insulating film 30 and the top surface insulating film 31 covering the upper corner portion of the trench and the insulating portion 26a. However, the corner insulating layer is formed only by the insulating layer 26a. May be.
[0037]
Thus, when the semiconductor device of the first embodiment is viewed in the cross section of FIG. 5, the trench upper corner portion 70 extending in the depth direction formed side by side in the width direction has two trench upper corner portions (70c) adjacent to each other. , 70d) or (70a, 70b) as a set, each of which is alternately covered with gate lead portions 28a, 28b having a substantially U-shaped cross section and insulating portions 26a having a substantially U-shaped cross section.
[0038]
Thus, in the semiconductor device of the first embodiment, the trench upper corner portions 70 and 71 are covered with the insulating portion 26a. As can be seen from FIG. 5, the insulating portion 26a is an insulator having a block-like film thickness with respect to the thin-film insulating films 30 and 31 that initially cover the trench upper corner portions 70 and 71. Dielectric breakdown in the trench upper corner portions 70 and 71 is strongly prevented. Therefore, the reliability of the gate insulating film can be greatly improved.
[0039]
As shown in FIG. 8 and the like, the wiring layer 22 is laminated on the interlayer insulating film 26. The wiring layer 22 is formed of a metal material such as aluminum. Further, as shown in FIG. 5 and the like, the wiring layer 22 is a flat plate extending to the semiconductor layer 20 (specifically, the top surface insulating film 31) through a contact hole 27 (see FIG. 7) formed in the interlayer insulating film 26. In contact with the externally drawn portion 28b.
As described above, the contact area between the flat lead-out portion 28b and the wiring layer 22 is sufficiently large, so that the contact resistance is sufficiently low.
[0040]
Next, a preferred example of the manufacturing method of the trench gate type semiconductor device according to the first embodiment will be described with reference to FIGS. FIG. 9A to FIG. 15A are views showing the manufacturing process of the semiconductor device in the cross section taken along the line AA of FIG. FIG. 9B to FIG. 15B are diagrams showing the manufacturing process of the semiconductor device in the section taken along the line DD in FIG.
[0041]
As shown in FIGS. 9A and 9B, a resist (not shown) formed in a predetermined pattern on the semiconductor layer 20 is used as a mask, for example, by anisotropic etching (RIE (Reactive Ion Etching) or the like). A trench 23 is formed. Thereafter, as shown in FIGS. 10A and 10B, the wall surface (bottom surface and side surface) of the trench 23 and the entire top surface of the semiconductor layer 20 are respectively formed by, for example, thermal oxidation or CVD (Chemical Vapor Deposition). Then, insulating films 30 and 31 made of a silicon oxide film are formed.
[0042]
After that, as shown in FIGS. 11A and 11B, the electrode material layer 32 made of polysilicon is covered with the gate insulating film 30 covering the wall surface of the trench 23 and the top surface of the semiconductor layer 20 by, for example, the CVD method. Laminated on the top insulating film 31.
Thereafter, as shown in FIGS. 12A and 12B, the electrode material layer 32 is patterned by, for example, anisotropic etching, and the trench gate electrode 24 buried to a predetermined height in the trench 23 is formed. The gate lead portions 28a and 28b extending to the semiconductor layer 20 (specifically, the top surface insulating film 31) are formed apart from the trench upper corner portions 70a and 70b extending in the trench depth direction. FIG. 6 shows the state at this point in three dimensions.
[0043]
Thereafter, as shown in FIGS. 13A and 13B, an interlayer insulating film 26 made of a silicon oxide film is formed by, for example, a CVD method, the semiconductor layer 20 (specifically, the top surface insulating film 31), the trench gate electrode 24, And formed over the gate lead-out portion 28.
Thereafter, as shown in FIGS. 14A and 14B, the portion of the interlayer insulating film 26 on the external flat lead-out portion 28b is removed by, for example, anisotropic etching. As a result, a contact hole 27 with a wiring layer, which will be described later, is formed, and the external flat lead portion 28b is exposed. FIG. 7 shows the state at this point in three dimensions. Accompanying the formation of the interlayer insulating film 26, as shown in FIG. 14, an insulating portion 26a that covers the trench upper corner portions 70a and 70b located at a position separated from the inner lead portion 28a is integrally formed. The insulating portion 26 a is stacked over the semiconductor layer 20 (specifically, the top surface insulating film 31) and the trench gate electrode 24.
[0044]
Thereafter, as shown in FIGS. 15A and 15B, a wiring layer 22 made of a metal material such as aluminum is laminated on the exposed external flat lead portion 28b and the interlayer insulating film 26 by, for example, sputtering. To do.
Thereafter, when a part of the wiring layer 22 located on the interlayer insulating film 26 is removed by, for example, etching, a trench gate type semiconductor device as shown in FIGS. 2 and 5 corresponding to FIGS. 15A and 15B, respectively. Is manufactured.
[0045]
In the above manufacturing method, as shown in FIG. 14B and the like, the insulating portion 26 a is formed on the semiconductor layer 20 (specifically, the top insulating film 31) after the trench gate electrode 24 is formed inside the trench 23. 14 to the trench gate electrode 24, the cross section of FIG. As described above, in this embodiment, the insulating portion 26a can be formed from the semiconductor layer 20 which is a wide region with few steps to the trench gate electrode 24. For this reason, as in the first prior art described above, it is necessary to perform operations requiring advanced techniques such as etching near the bottom surface of the deep and narrow trench 23, mask arrangement, and photosensitive material application in the photolithography process. Therefore, the manufacturing process can be simplified.
[0046]
Moreover, the insulating portion 26a is formed integrally with the interlayer insulating film 26 as shown in the manufacturing method. That is, since the insulating portion 26a can be formed in association with the formation of the interlayer insulating film 26 that is generally formed for insulation between the wiring layer 22 and the semiconductor layer 20, the number of manufacturing steps of the first prior art described above. Compared with a manufacturing method with a large amount, the number of manufacturing steps can be greatly reduced, and a structure that makes it difficult to cause dielectric breakdown at the upper corner of the trench can be realized.
[0047]
(No.See 1Example)See 1The top view of an example trench gate type semiconductor device is shown. FIG. 17 is a sectional view taken along line AA in FIG. 18 is a cross-sectional view taken along line BB in FIG. Further, the structure in the cross-sectional view taken along the line CC of FIG. 16 is the same as that shown in FIG. The structure in the sectional view taken along the line DD of FIG. 16 is the same as that shown in FIG.
  16 to 18 shown in FIG.See 1In the example trench gate type semiconductor device, the wiring layer 22 is formed on the central portion of the trench gate electrode 24 extending in the depth direction. Accordingly, a gate lead portion 28 that connects the wiring layer 22 and the trench gate electrode 24 is also formed on the central portion of the trench gate electrode 24. These are different from the semiconductor device of the first embodiment in which the wiring layer 22 and the gate lead-out portion 28 are formed on the end portions (front end portion and rear end portion) of the trench gate electrode 24 in the depth direction.
[0048]
  FirstSee 1The same effect as that of the semiconductor device of the first embodiment can be obtained by the semiconductor device of the example.
[0049]
(No.See 2Example)See 2A sectional view of an example trench gate type semiconductor device is shown. This cross-sectional view corresponds to the cross-sectional view (FIG. 5) taken along the line DD in FIG.
  In this semiconductor device, the first gate lead portion 46 and the second gate lead portion 48 constitute the entire gate lead portion 50. The gate lead-out portion 50 is located at a position separated from both of the trench upper corner portions 72 extending in the trench depth direction. Further, the second gate lead portion 48 extends to the semiconductor layer 20 (specifically, the top surface insulating film 31) with the separated trench upper corner portion 72 as a boundary. Then, all of the trench upper corner portion 72 located away from the gate lead-out portion 50 is covered with the insulating portion 52. The flat plate-like second gate lead portion 48 is commonly connected to all the trench gate electrodes 24 through the first gate lead portion 46. The entire top surface of the second gate lead portion 48 is in contact with the entire bottom surface of the wiring layer 54. These points are different from the semiconductor device of the first embodiment.
[0050]
  FirstSee 2According to the example semiconductor device, the gate lead-out portion 50 is separated from both the trench upper corner portion 72 extending in the trench depth direction, and all the separated trench upper corner portions 72 are covered with the insulating layer. Insulation breakdown is strongly prevented,A highly reliable structure of the gate insulating film can be realized.
  Further, since the gate lead portion 50 is commonly connected to all the trench gate electrodes 24, the gate lead portion 50 can be used more effectively.
  Further, the entire top surface of the second gate lead portion 48 formed on the top surface of the insulating portion 52, the top surface of the first gate lead portion 46 and having a large top surface area, and the entire bottom surface of the wiring layer 54. Since they are in contact, the contact resistance between them can also be made very small.
[0051]
  NextSee 2A preferred manufacturing method of the example trench gate type semiconductor device will be described with reference to FIGS.
  The state up to the state of FIG. 11B is the same as that of the semiconductor device manufacturing method of the first embodiment.
  After that, as shown in FIG. 20, the first electrode material layer 32 is patterned by anisotropic etching, for example, and the trench gate electrode 24 buried to a predetermined height inside the trench 23 is connected to the trench gate electrode 24. A first gate lead portion 46 is formed that is separated from both of the trench upper corner portions 72 extending in the trench depth direction.
  Thereafter, as shown in FIG. 21, an insulating portion 52 made of a silicon oxide film is formed, for example, by the CVD method so as to have the same height as the top surface of the first gate lead portion 46. Since the insulating portion 52 is formed integrally with the interlayer insulating film as in the first embodiment, the interlayer insulating film is also formed in this step.
[0052]
  After that, as shown in FIG. 22, a second electrode material layer 48 that becomes a second gate lead portion made of polysilicon is laminated over the first gate lead portion 46 and the insulating portion 52 by, for example, the CVD method. The insulating part 52 is located above the top surface of the semiconductor layer 20 with the trench upper corner part 72 separated from the first gate lead part 46 as a boundary.
  After that, as shown in FIG. 19, when the wiring layer 54 made of a metal material such as aluminum is formed over the entire top surface of the second gate lead portion 48 by, for example, sputtering,See 2An example trench gate type semiconductor device is manufactured.
[0053]
  FirstSee 2When the semiconductor device of the example is manufactured in this way, the semiconductor device of the first embodiment is less likely to cause dielectric breakdown and the contact resistance between the gate lead portion 50 and the wiring layer 54 is very small. Basically, it is only necessary to add the step of laminating the second electrode material layer 48 to be the second gate lead portion as described above, and the manufacturing method shown in FIG. be able to.
[0054]
(No.See 3Example)See 3A sectional view of an example trench gate type semiconductor device is shown. This cross-sectional view corresponds to the cross-sectional view (FIG. 5) taken along the line DD in FIG.
  In this semiconductor device, the first gate lead portion 46 and the second gate lead portion 56 constitute an entire gate lead portion 58. The gate drawer 58 isSee 2Similar to the example, it is located away from both of the trench upper corner portions 72 extending in the trench depth direction. Further, the second gate lead-out portion 56 extends to the semiconductor layer 20 (specifically, the top surface insulating film 31) with the separated trench upper corner portion 72 as a boundary. All of the trench upper corner portion 72 located at a position separated from the gate lead-out portion 58 is covered with the insulating portion 53. FirstSee 3In the example, there are two types of insulating portions 53, and the two types of insulating layers 53a and 53b alternately cover two adjacent trench upper corner portions 72. One insulating part 53a is shorter than the other insulating part 53b. A second gate lead-out portion 56 is interposed between the shorter insulating portion 53 a and the wiring layer 60. The top surface of the taller insulating portion 53 b is in contact with the wiring layer 60. These points are different from the semiconductor device of the first embodiment.
[0055]
  FirstSee 3According to the example semiconductor deviceSee 2Similar to the example, it is possible to make dielectric breakdown more difficult to occur. Nevertheless, since the top surface of the second gate lead-out portion 56 formed on the shorter insulating portion 53a is in contact with the bottom surface of the wiring layer 60 over a wide area, the contact resistance between them is also small. can do.
[0056]
  NextSee 3A method for manufacturing an example trench gate type semiconductor device will be described with reference to FIGS.
  Until the state of FIG.See 2This is the same as the manufacturing method of the example semiconductor device.
  Thereafter, the upper portions of the U-shaped insulating portions 53 arranged side by side in the width direction in the cross section of FIG. 24 are removed every other depth to a predetermined depth, for example, by anisotropic etching. As a result, the insulating portion 53 is of two types, an etched short insulating portion 53a and an unetched tall insulating portion 53b.
  Thereafter, as shown in FIG. 25, a second electrode material layer 56 to be a second gate lead portion made of polysilicon is laminated on the short insulating portion 53a by, for example, a CVD method. The insulating portion 53a is located above the top surface of the semiconductor layer 20 with the trench upper corner portion 72 separated from the first gate lead portion 46 as a boundary.
  Thereafter, as shown in FIG. 23, when the wiring layer 60 made of a metal material such as aluminum is formed on the second gate lead-out portion 56 and the tall insulating portion 53b by sputtering, for example,See 3An example trench gate type semiconductor device is manufactured.
[0057]
  FirstSee 3When the semiconductor device of the example is manufactured in this way, the semiconductor device of the first embodiment is shown although the dielectric breakdown is less likely to occur and the contact resistance between the gate lead portion 50 and the wiring layer 60 is small. Basically, it is only necessary to add a step of removing a part of the insulating portion 53 and a step of laminating the second electrode material layer 56 to be the second gate lead portion as described above. It can be manufactured by a relatively simple manufacturing process.
[0058]
Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
[0059]
(1) In the above embodiment, for example, as shown in FIG. 6 showing the first embodiment, the gate lead-out portion 28 is separated from the trench upper corner portion 70b extending in the trench depth direction, and the gate lead-out portion 28 Has a structure extending up to the top of the top surface of the semiconductor layer 20 with the separated trench upper corner portion 70b as a boundary, and the trench upper corner portion 70b is covered with an insulating portion 26a (see FIG. 5). This has been described as an example. However, the top surface of the semiconductor layer is separated from the trench upper corner portion (for example, reference numeral 71 in FIG. 6) extending in the trench width direction, and the gate lead portion is bordered by the separated trench upper corner portion. A structure extending upward and a structure in which an upper corner portion of the trench is covered with an insulating portion are also included in the scope of application of the present invention.
[0060]
(2) There are no particular limitations on the material of the trench gate electrode, the gate lead portion, and the wiring layer. In the above embodiment, the trench gate electrode and the gate lead portion are formed of polysilicon. However, they may be formed of metal materials such as aluminum, copper, and alloys thereof, or other materials. The wiring layer is not necessarily limited to metal materials such as aluminum, copper, and alloys thereof, and may be formed of other materials. The material of the gate insulating film, top surface insulating film, interlayer insulating film, and insulating portion may be any insulating material, and may be formed of, for example, a silicon nitride film.
[0061]
(3) In the semiconductor device of the first embodiment, as shown in FIG. 5 and the like, the trench upper corner portion 70 and the like are first covered with the insulating films 30 and 31 and then further covered with the insulating portion 26a. However, the trench upper corner portion 70 may be directly covered with the insulating portion 26a without being covered with the insulating films 30 and 31.
[0062]
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.
[Brief description of the drawings]
FIG. 1 is a plan view of a trench gate type semiconductor device according to a first embodiment.
FIG. 2 is a cross-sectional view taken along line AA in FIG.
FIG. 3 is a cross-sectional view taken along line BB in FIG.
4 shows a cross-sectional view taken along line CC in FIG. 1. FIG.
FIG. 5 is a cross-sectional view taken along line DD in FIG.
FIG. 6 shows a perspective view of the trench gate type semiconductor device of the first embodiment (1).
FIG. 7 is a perspective view of the trench gate type semiconductor device of the first embodiment (2).
FIG. 8 is a perspective view of the trench gate type semiconductor device of the first embodiment (3).
FIG. 9 shows a part of the manufacturing process of the trench gate type semiconductor device of the first embodiment (1).
FIG. 10 shows a part of the manufacturing process of the trench gate type semiconductor device according to the first embodiment (2).
FIG. 11 shows a part of the manufacturing process of the trench gate type semiconductor device according to the first embodiment (3).
FIG. 12 shows a part of the manufacturing process of the trench gate type semiconductor device according to the first embodiment (4).
FIG. 13 shows a part of the manufacturing process of the trench gate type semiconductor device according to the first embodiment (5).
FIG. 14 shows a part of the manufacturing process of the trench gate type semiconductor device according to the first embodiment (6).
FIG. 15 shows a part of the manufacturing process of the trench gate type semiconductor device according to the first embodiment (7).
FIG. 16See 1The top view of an example trench gate type semiconductor device is shown.
FIG. 17 is a cross-sectional view taken along line AA in FIG.
18 is a cross-sectional view taken along line BB in FIG.
FIG. 19See 2The top view of an example trench gate type semiconductor device is shown.
FIG. 20See 2A part of manufacturing process of the example trench gate type semiconductor device is shown (1).
FIG. 21See 2A part of manufacturing process of the example trench gate type semiconductor device is shown (2).
FIG. 22See 2A part of manufacturing process of the example trench gate type semiconductor device is shown (3).
FIG. 23See 3The top view of an example trench gate type semiconductor device is shown.
FIG. 24See 3A part of manufacturing process of the example trench gate type semiconductor device is shown (1).
FIG. 25See 3A part of manufacturing process of the example trench gate type semiconductor device is shown (2).
FIG. 26 is a plan view of a first conventional trench gate type semiconductor device.
FIG. 27 is a cross-sectional view taken along line AA in FIG.
FIG. 28 is a cross-sectional view taken along line BB in FIG.
FIG. 29 is a perspective view of a trench gate type semiconductor device according to the first prior art.
FIG. 30 is a plan view of a second conventional trench gate type semiconductor device.
FIG. 31 is a cross-sectional view taken along line AA in FIG.
[Explanation of symbols]
20: Semiconductor layer
22: Wiring layer
23: Trench
24: Trench gate electrode
26: Interlayer insulating film, 26a: Insulating part
28a, 28b: Gate drawer part
30: Gate insulating film
31: Top surface insulating film
70: Trench upper corner

Claims (9)

A semiconductor layer in which a plurality of trenches are formed;
A gate insulating film formed along the trench wall;
A trench gate electrode embedded through a gate insulating film to a predetermined height inside the trench;
An insulating portion covering one first trench upper corner portion of the trench upper corner portion extending in the trench depth direction;
The first being spaced trench upper corners or al, is connected to both the adjacent trench gate electrode covers the second trench upper corner portion other the trench upper corner portion extending in the trench depth direction, next A gate lead portion covering the top surface of the semiconductor layer located between two matching trenches ;
At least the semiconductor layer top surface upper wiring layer in contact with the gate lead-out portion of the trench gate type semiconductor device having a. The insulating portion covers an end portion on the first trench upper corner portion side of the trench upper corner portion extending in the trench width direction;
2. The trench gate type semiconductor device according to claim 1, wherein the gate lead portion covers an end portion on the second trench upper corner portion side of the trench upper corner portion extending in the trench width direction . The insulating unit of claim 1 or 2, characterized in that it is formed over the upper trench gate electrode from the semiconductor layer top face upward so as to cover at least a portion of the first trench upper corner Trench gate type semiconductor device.   4. The trench gate type semiconductor device according to claim 1, wherein the insulating portion is formed integrally with an interlayer insulating film located between the semiconductor layer and the wiring layer.   The trench gate type semiconductor device according to claim 1, wherein the insulating portion is formed thicker than the gate insulating film. Forming a trench in the semiconductor layer;
Forming a gate insulating film along the trench wall;
Forming an electrode material layer over the top surface of the semiconductor layer outside the trench from inside the trench;
The electrode material layer is patterned so as to be separated from at least one of the trench gate electrode embedded up to a predetermined height inside the trench and the upper corner portion of the trench connected to the trench gate electrode and extending in the depth direction of the trench. Forming a gate lead portion extending to above the top surface of the layer;
Forming an insulating portion from above the top surface of the semiconductor layer to above the trench gate electrode so as to cover at least part of the upper corner portion of the trench that is separated from the gate lead portion;
A method of manufacturing a trench gate type semiconductor device comprising a step of forming a wiring layer in contact with a gate lead-out portion. Forming a trench in the semiconductor layer;
Forming a gate insulating film along the trench wall;
Forming a first electrode material layer at least inside the trench;
A trench gate electrode that is patterned to a predetermined height inside the trench to pattern the first electrode material layer, and a first gate lead portion that is connected to the trench gate electrode and is separated from at least one of the upper corner portions of the trench Forming a step;
Forming an insulating portion from above the top surface of the semiconductor layer to above the trench gate electrode so as to cover at least a part of the upper corner portion of the trench that is separated from the first gate lead portion;
Forming a second electrode material layer serving as a second gate lead portion above the top surface of the semiconductor layer with the trench upper corner portion separated from the first gate lead portion as a boundary from the first gate lead portion;
A method for manufacturing a trench gate type semiconductor device, comprising a step of forming a wiring layer in contact with a second gate lead portion. Further comprising forming an interlayer insulating film above the top surface of the semiconductor layer;
In the step of forming the wiring layer, the manufacturing method of the trench gate type semiconductor device according to claim 6 or 7, characterized in that together with contact with the gate lead-out portion to form a wiring layer so as to be positioned in the interlayer insulating film above . The insulating portion and the step of forming is performed the interlayer insulating film collectively forming a, the interlayer insulating film and the insulating portion to any one of claims 6-8, characterized in that integrally formed A method for manufacturing the trench gate type semiconductor device described.

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