CN101577420B - 一种限制耦合变压器推拉式功率转换电路的漏源电压的装置和方法 - Google Patents

一种限制耦合变压器推拉式功率转换电路的漏源电压的装置和方法 Download PDF

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CN101577420B
CN101577420B CN2009101390174A CN200910139017A CN101577420B CN 101577420 B CN101577420 B CN 101577420B CN 2009101390174 A CN2009101390174 A CN 2009101390174A CN 200910139017 A CN200910139017 A CN 200910139017A CN 101577420 B CN101577420 B CN 101577420B
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圣杰·哈佛纳
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Abstract

一种用于限制耦合变压器推拉式整流器的开关场效应晶体管(Field-Effect Transistorswitching，switching FET)的最大漏源电压(drain-source voltage，简写VDS)的电路，该整流器具有一个最大DC供应电压VIN_MAX。所述VDS被推拉式晶体管和整流器电路的漏电感加强。所述限制电路桥连接开关晶体管的漏极并进一步包括一系列的相互连接的两个对立的稳压二极管(Zener diode)，所述每一个稳压二极管都具有一个稳压电压Vzx(Zener voltage)。本发明适用于N沟槽场效应晶体管和P沟槽场效应晶体管。设定Vzx略微大于或等于2×VIN_MAX，因此两个对立的稳压二极管把最大VDS钳位在大约VIN_MAX+1/2Vzx的数值处。所述具有完整VDS钳位的功率开关装置包括：一个开关晶体管，所述开关晶体管具有一个源极引线、一个漏极引线和一个栅极引线；一个稳压二极管，所述稳压二极管具有一个稳压电压Vzx并且具有第一引线和第二引线，所述稳压二极管的第二引线进一步连接所述漏极引线。

Description

一种限制耦合变压器推拉式功率转换电路的漏源电压的装置和方法
技术领域
本发明属于功率电子技术领域，具体涉及在功率开关电路中对电压过冲的控制和抑制。 
背景技术
功率转换电路目前正被普遍的应用于电子领域，例如开关电源、直流电-直流电(DC-DC)电压转换及直流电-交流电(DC-AC)电压转换。 
在操作这种转换电路时，经常遇到的一种情况是：当功率转换装置，例如关闭MOSFET(金属氧化物场效应晶体管，Metal-Oxide-Semiconductor Field-EffectTransistor)防止非钳位或部分钳位电感负载，在关闭时，由于功率MOSFET装置的栅极驱动器，负载电流变化的高比率(简写di/dt)通常被电感负载所影响。这通常导致相应过冲电压和振荡，这是因为储存在非钳位电路电感中的漏电感能量在减弱消失前与寄生电路电容发生共振。过度的振荡可能导致功率损耗，过冲电压的过度峰值电压可能导致功率MOSFET装置雪崩击穿并产生永久性的装置故障。此外，过冲电压和共振还可能导致高强度的EMI/RFI(电磁干扰/射频干扰)控制和/或辐射，从而导致对邻近的其他敏感电子系统的操作产生不利干扰。 
现在已经对过冲电压和共振现行进行了诸多研究，以尽可能减少其不利影响。其解决方案包括增加MOSFET的缓冲、通过减少栅极关闭电流以减小关闭速度等等。上述解决方案通常需要许多额外的组件和/或效率很低。因此现在需要有效降低由高比率的负载电流变化di/dt所导致的过冲电压和共振。以下是本发明的参考文献： 
1、F Merienne，J Roudet，J.L Schanen，“Switching disturbance due to sourceinductance for a power MOSFET：analysis and solutions”，IEEE Power Electronics Specialists Conference，PESC 1996年第20卷第1743～1747页； 
2、G Nobauer，D Ahlers和J Ruiz-Sevillano，“A method to determine parasiticinductances in Buck Converter topologies”，Infineon Application Note，2004年6月； 
3、Qun Zhao，Goran Stojcic，“Characterization of Cdv/dt induced power loss inSynchronous Buck DC-DC converters”，IEEE Applied Power Electronics Conference，APEC，2004年第1卷第292～297页； 
4、Bo Yang，Jason Zhang“Effect and Utilization of Common Source Inductancein Synchronous Rectification”，IEEE Applied Power Electronics Conference，APEC2005，1996年第3卷第1449～1453页； 
5、W Teulings，J.L.Schanen，J Roudet，“MOSFET switching behavior underinfluence of PCB stray inductance”，IEEE Industry Applications Conference，1996年第3卷第1449～1453页。 
发明内容
本发明公开了一种用于限制耦合变压器推拉式整流器的开关场效应晶体管(Field-Effect Transistor switching，switching FET)的最大漏源电压(drain-sourcevoltage，简写VDS)的电路，该整流器具有一个最大DC供应电压VIN_MAX。所述VDS被推拉式晶体管和整流器电路的漏电感加强。所述限制电路桥连接开关晶体管的漏极并进一步包括一系列的相互连接的两个对立的稳压二极管(Zener diode)，所述每一个稳压二极管都具有一个稳压电压Vzx(Zener voltage)。本发明适用于N沟槽场效应晶体管和P沟槽场效应晶体管。 
在一些具体实施例中，设定Vzx略微大于或等于2×VIN_MAX，因此两个对立的稳压二极管把最大VDS钳位在大约VIN_MAX+1/2Vzx的数值处。 
在另一个实施例中，具有完整VDS钳位的功率开关装置包括： 
一个开关晶体管，所述开关晶体管具有一个源极引线、一个漏极引线和一个栅极引线； 
一个稳压二极管，所述稳压二极管具有一个稳压电压Vzx并且具有第一引线和第二引线，所述稳压二极管的第二引线进一步连接所述漏极引线。 
连接具有完整VDS钳位的功率开关装置中的两个，作为一个耦合变压器推拉式整流器的一对开关场效应晶体管，其中所述耦合变压器推拉式整流器具有一个最大DC供应电压VIN_MAX，所述两个稳压二极管的第一引线相互连接，从而使得所述两个具有完整VDS钳位的功率开关装置在最大VDS被钳位在大约VIN_MAX+1/2Vzx的情况下，执行推拉式功率开关的相应任务。 
在一个进一步实施例中，所述开关FET是一个N沟槽FET并且所述稳压二极管的第二引线是其负极。 
在一个可选实施例中，所述开关FET是一个P沟槽FET并且所述稳压二极管的第二引线是其正极。 
在一个具有N沟槽开关FET的实施例中，所述开关FET是一个底部漏极沟槽FET，所述稳压二极管是一个底部负极装置，并且共享他们的相应底部漏极和底部负极，在一个单一晶片上形成所述开关FET和稳压二极管，所述晶片具有普通的位于晶片基底顶部的N层(N-layer)。 
本发明公开了一种用于限制耦合变压器推拉式整流器的开关场效应晶体管(Field-Effect Transistor switching，switching FET)的最大漏源电压(drain-sourcevoltage，简写VDS)的方法，该整流器具有一个最大DC供应电压VIN_MAX。所述VDS被推拉式晶体管和整流器电路的漏电感加强。该方法包括基于所述VDS超过VDS最大值(VDSmax)的倾向，自动生成一个内部漏极电流，所述内部漏极电路在开关FET的漏极间流动并具有相应的电能损耗，因此限制了最大VDS。 
在一个进一步实施例中，自动生成内部漏极电流的过程进一步包括提供一个电路以桥连接开关FET的各漏极。所述桥连接电路具有一种基于任一开关FET的VDS超过一个预先确定限制值的倾向的非破坏性击穿。 
在一个进一步实施例中，提供桥连接电路的过程进一步包括提供一系列的相互连接的两个对立的稳压二极管，所述每一个稳压二极管都具有一个稳压电压Vzx，该Vzx被设定略微大于或等于2×VIN_MAX，因此最大VDS的值大约为VIN_MAX+1/2Vzx。
本发明的以上各方面以及其众多的实施例将在下文中进一步叙述，以便于本领域技术人员对其的理解。 
附图说明
为了更全面的描述本发明的众多实施例，参考以下附图做进一步说明。然而，这些附图仅用于描述，并不用于限定本发明的保护范围。 
图1A和1B描述了现有技术的一种耦合变压器推拉式整流器电路及其内信号波形。 
图2A和2B描述了本发明的一种耦合变压器推拉式整流器电路及其内信号波形。 
图3A、3B和3C描述了现有技术的开关N沟槽FET及其相应半导体晶片结构的顶视图。 
图4A和4B描述了本发明的一种使用N沟槽FET且具有完整VDS钳位的功率开关装置以及其相应半导体晶片结构的顶视图。 
图4C描述了本发明的一种使用N沟槽FET且具有完整VDS钳位的功率开关装置的相应半导体晶片结构的截面视图。 
图5A描述了本发明的采用P沟槽FET的具有完整VDS钳位的一个桥连接电路，该电路用于限制耦合变压器推拉式整流器的一个开关FET的最大VDS。 
图5B描述了本发明的采用P沟槽FET的具有完整VDS钳位的功率开关装置的相应半导体晶片的截面视图。 
图6描述了两个堆叠半导体晶片的顶视图，所述每一半导体晶片具有本发明的具有完整VDS钳位的功率开关装置。 
具体实施方式
以上和以下的描述连同附图仅仅描述了本发明的部分较佳实施例以及可选实施例。该描述及附图仅用于阐述，并不用于限制本发明。因此，本领域技术人员一旦理解本发明就会得出本发明实施例的变形、修改及可选方式，然而对本发明的任何变形、修改和可选实施方式都仍未脱离本发明的保护范围。 
图1A和1B描述了现有技术的一种耦合变压器推拉式整流器电路及其内信号波形。一对开关FET Q1 10和开关FET Q2 20轮流开关高边缘荷载电流，首先通过具有电压Vin的DC电源6供电，相应地通过一个推拉式晶体管4地初级线圈PMW-1和PMW-2。相应开关功率磁耦合第二线圈SCW-1和SCW-2，以转移一个外荷载(图中未示出)。所述开关FET Q1 10和Q2 20的轮流开关顺序 
控制信号波形栅极源极电压VG1-S1(在开关FET Q1 10的栅极G1和源极S1中使用，所述开关FET Q1 10同样具有一个嵌入式体二极管BD1和漏极D1)并且栅极源极电压VG2-S2(在开关FET Q2 20的栅极G2和源极S2中使用，所述开关FET Q2 20同样具有一个嵌入式体二极管BD2和漏极D2)。现有技术的推拉式整流器电路1具有多个沿负载电路路径的漏电感。如图所示，所述漏电感包括所述初级线圈PMW-1的一个初级漏电感LPRI1、所述初级线圈PMW-2的一个初级漏电感LPRI2和一个印刷电路板(PCB)电路路径的相应路径电感LPCB，从而组成负载电流路径。对于本领域技术人员，当所述开关FETQ1 10的开关突然关闭，变压器储存磁能的浪费和漏电感将会导致其漏源电压VD1-S1的出现尖峰并与一个峰值漏源电压Max VD1-S1振荡。如前所述，开关FET Q1 10突然关闭并导致栅极源极电压VG1-S1向下转变。应当注意，所述耦合变压器推拉式整流器电路的内在操作(即便具有的电压峰值钳位)将导致漏源电压VD1-S1变至2×Vin。然而，FET Q1 10的突然关闭诱导了一个电压峰值，其形成所述最大漏源电压Max VD1-S1，比两倍的最高DC电源电压VIN_MAX高的多。所述漏源电压VD1-S1的尖峰和振荡是不利的，因为其导致了EMI/RFI，当振幅过大时候，将会导致所述开关FET Q1 10的漏极-源极(D1-S1)的雪崩击穿。同样地，所述开关FET Q2 20的开关突然关闭，变压器储存磁能的浪费和漏电感将会导致其漏源电压VD2-S2的出现尖峰并与一个峰值漏源电压Max VD2-S2振荡。为了确保安全运行，必须设定所述FET具有比2×VIN_MAX高的多的损坏额定电压，这种方式低效并需要更高的电阻(Rdson)和/或成本。 
图2A和2B描述了本发明的一种用于限制最大开关FET的VDS的耦合变压器推拉式整流器电路100及其内信号波形。使用一个桥连接电路110，桥连接开关FET Q1 10和Q2 20。所述桥连接电路110进一步包括一系列的相互连接的两个对立的稳压二极管 Z1 112和Z2 114，所述每一个稳压二极管都具有一个稳压电压Vzx(Zener voltage)。 
一个稳压二极管，所述稳压二极管具有一个稳压电压Vzx并且具有第一引线和第二引线，所述稳压二极管的第二引线进一步连接所述漏极引线。稳压二极管Z1 112的第一引线112a连接稳压二极管Z2 114的第一引线114a。稳压二极管Z1 112的第二引线112b连接开关FET Q1 10的漏极D1。稳压二极管Z2 114的第二引线114b连接开关FET Q220的漏极D2。包括开关FET Q1 10和Q2 20、桥连接电路110的桥连接的FET电路101可以与转换电路110分开制造。 
基于所述VDS超过一个预定最大VDS最大值(VDSmax)的倾向，所述桥连接电路110自动产生一个内部漏极电流，所述内部漏极电路在主开关FET Q1 10和Q2 20的相应漏极D1和D2之间流动。因此根据稳压电压Vzx的设定，当漏源电压VD1-S1超过VDSmax时，VD1-S1将会导致一个稳压二极管Z1 112的击穿，并伴随漏电感储存磁能的释放，因此限制了最大VD1-S1至VDSmax。所述桥连接电路110限制最大开关FETVDS的能力可以清楚的看到，通过对比图1B和图2B中关闭时的VD1-S1的波形。需要指出的是，由于两个对立的稳压二极管Z1 112和Z2 114的自身电压的限制，桥连接电路110展现了一种基于稳压二极管Z1 112的稳压电压的非破坏性击穿。需要进一步指出的是，由于VDS保持在VDSmax之下，所述稳压二极管Z1 112相反向下偏离稳压电压Vzx，因此实质保持绝缘。因此，桥连接电路110也实质保持绝缘，故其不干涉本发明推拉式整流器电路100的其他操作。作为一个列举参数的本发明实施例，所述DC电源6被限制至一个最大值VIN_MAX，稳压二极管电压Vzx被设定略微大于或等于2×VIN_MAX，因此最大VDS的值大约为VIN_MAX+1/2Vzx。这比现有技术低了很多。因此，FET具有一个较现有技术低的多的击穿额定电压，允许更好的效率和较低的电阻Rdson和/或成本。所述稳压二极管Z2 114和FETQ2 20采用同样的方式工作，当FETQ2被突然关闭时并具有一个突然下降的栅极源极电压VG2-S2。对于本领域技术人员而言，现在可以清楚的了解，由于稳压二极管Z1 112和Z2 114相对反极性的连接在桥连接电路110上。换而言之，稳压二极管Z1 112和Z2 114的几项可以同时反置，而不影响桥连接电路110的任何功能(然而，如果稳压二极管112时和FETQ1 110在同一晶片上时，如图4A～4C所述，二极管极性不应反转)。进一步而言，如图2A所示，可以采用N沟槽开关FETQ1 10和Q2 20，本发明可以经过相应修改，使用P沟槽FET，正如前文所述。 
为了从半导体晶片水平描述本发明，图3A～3C描述了现有技术的N沟槽FET11及其相应半导体晶片结构的顶视图。图3A时一个具有源极S1、栅极G1、漏极D1和内置体二极管BD1的N沟槽FET11电路简图。图3B是一个除去顶部钝化层12k以暴露两个钝化窗口12g和12h的相应N沟槽FET晶片12的顶视图，其还具有一个源极金属12a被一个栅极金属12d所环绕，后者具有一个栅极衬垫12e用于进行外部电连接。所述源极金属12a和栅极金属12d被一个金属缺口12f相互分隔。源极金属12a下面的区域包含有效区域，晶体管位于该区域。在表面之下，栅极滑道沟槽12b及其两个末端栅极滑道金属连接点12c在源极金属下面并从栅极金属12d处向有效区域的晶体管栅极提供电连接。所述栅极结构具有多个相对平行的栅极滑道沟槽，以相应增加电流容量，为避免过于繁琐，此处图中仅仅示出一条滑道沟槽。所述N沟槽FET11的漏极D1位于N沟槽FET晶片12底部，因此顶视图中未示出。图3C是相应N沟槽FET晶片12的顶视图，其具有一个有钝化窗口12g和12h的钝化层12k。 
图4A和4B描述了本发明具有完整VDS钳位115的具有主开关N沟槽FET11以及稳压二极管Z1 112的功率开关装置，以及其相应半导体晶片116的顶视图。所述N沟槽FET11具有一个源极S1、一个漏极D1和一个栅极G1。所述稳压二极管Z1 112具有一个第一引线112a作为其正极、一个第二引线112b作为其负极。稳压二极管Z1 112的第二引线112b连接N沟槽FET11的漏极D1。参考图2A本发明的推拉式功率整流器电路100，两个功率开关装置连接完整VDS钳位115作为耦合变压器推拉式整流器的一对主开关FET，该整流器具有一个最大DC供应电压VIN_MAX，并且两个功率开关装置的第一引线112a相互连接，具有完整VDS钳位115的两个功率开关装置一起操作相应推拉式功率开关，以把最大VDS钳位至大于VIN_MAX+1/2Vzx(其中设定Vzx略微大于或等于2×VIN_MAX)。在图4B中，稳压二极管Z1 112的稳压二极管正极金属116p通过钝化层12k从源极金属12a处孤立，然而稳压二极管金属在底表面连接漏极D1，此处图中未示出。 
图4C描述图4B沿B-B方向的一个截面视图，其描述了本发明具有完整VDS钳位115的开关装置的一个具有完整VDS钳位的半导体晶片116的FET。为了便于描述，等效电路图用虚线绘于半导体晶片结构上。具有完整VDS钳位晶片116的FET具有一个N+基底12n，其位于底部漏极金属12m顶部。一个普通N层，一个用于设置各种装置元件的N-外延层12p位于N+基底12n的顶部。未避免不需要的细节，只绘出两个平行的源极金属12a，两个平行的沟槽栅极116c和三个平行的稳压二极管Z1 112。因此，比如， 两个源极金属12a通过一个三维(3D)源极金属连接件116a相互连接。两个沟槽栅极116c通过一个3D栅极连接件116d相互连接。然而三个平行的稳压二极管Z1 112的正极金属统一连接到一个稳压电阻正极金属116p。应该可以理解，实际操作中，大量平行的沟槽栅极和稳压电阻中的任一个可以被具有完整VDS钳位晶片116的FET执行。多种平行沟槽栅极116c和平行稳压电阻Z1112进一步从场氧化物去116q上分别相对孤立。因此，开关FET位于底部漏极沟槽FET中、稳压二极管表现为底部负极、所述FET和稳压二极管在同一单一晶片116上形成，通过与N-外延层12p和N+基底12n，共享他们的相应底部漏极和底部负极。 
如前所述，本发明可以改进适用于P沟槽FET。为此，图5A展示了本发明稳压钳位P沟槽开关装置130的一个电路图，其用于限制开关P沟槽FETQ1 132和Q2 134的最大VDS，当其被用于耦合变压器推拉式整流器中。注意，稳压电极Z1 112的第一引线112a为其正极，并与P沟槽FET Q1 132漏极D1相连，等等。图5B描述了，相对应具有P沟槽FET的稳压钳位P沟槽开关装置130的，具有完整VDS钳位晶片136的FET的截面视图。所述P沟槽FET Q1 132和稳压二极管Z1 112位于P-外延层136p中，后者位于P+基底136n顶部，并具有一个漏极金属连接点12m。图5B中的元件通图4C中一致，除了极性相反以外。 
进一步介绍本发明优选实施例，图6描述了一个两个联合封装N沟槽FET晶片系统的顶视图，二者分别具有完整VDS钳位140。该封装的FET晶片是具有完整VDS钳位晶片-1 142a的FET和具有完整VDS钳位晶片-2 142b的FET，二者相应焊接至传导引线架衬垫146。传导引线架衬垫146进一步位于绝缘平台148顶部并具有大量引线架引线引脚150外延出其边缘。连接现144用于相互连接两个FET晶片和连接两个联合封装FET晶片至引线架引脚150。最后，两个封装FET晶片系统被环氧材料152封装，并提供引线架引脚150的位置。 

Claims (7)

1.一种用于限制耦合变压器推拉式整流器的主开关场效应晶体管（switching FET）的最大漏源电压（VDS）的电路，所述整流器具有一个最大DC供应电压VIN_MAX，所述最大漏源电压（VDS）被推拉式晶体管和整流器电路的漏电感加强，用于限制最大漏源电压的所述电路包括一个桥连接电路连接在一对主开关场效应晶体管各自的漏极之间，其特征在于，所述桥连接电路进一步包括一系列的相互连接的两个对立的稳压二极管（Zenerdiode），每一个所述稳压二极管都具有一个稳压电压Vzx（Zener voltage），其中，所述主开关场效应晶体管是N沟槽FET，两个所述稳压二极管各自的负极分别与一对主开关场效应晶体管各自的漏极连接。
2.一种用于限制耦合变压器推拉式整流器的主开关场效应晶体管（switching FET）的最大漏源电压（VDS）的电路，所述整流器具有一个最大DC供应电压VIN_MAX，所述最大漏源电压（VDS）被推拉式晶体管和整流器电路的漏电感加强，用于限制最大漏源电压的所述电路包括一个桥连接电路连接在一对主开关场效应晶体管各自的漏极之间，其特征在于，所述桥连接电路进一步包括一系列的相互连接的两个对立的稳压二极管（Zenerdiode），每一个所述稳压二极管都具有一个稳压电压Vzx（Zener voltage），其中，所述主开关场效应晶体管是P沟槽FET，两个所述稳压二极管各自的正极分别与一对主开关场效应晶体管各自的漏极连接。
3.一种用于限制耦合变压器推拉式整流器的主开关场效应晶体管的最大漏源电压的电路，其特征在于，包括：
两个具有完整VDS钳位的功率开关装置；
每个具有完整VDS钳位的功率开关装置包含一个开关晶体管和一个稳压二极管，所述开关晶体管具有一个源极引线、一个漏极引线和一个栅极引线；
所述稳压二极管具有一个稳压电压Vzx并且具有第一引线和第二引线，所述稳压二极管的第二引线进一步连接所述漏极引线；
其中，连接两个具有完整VDS钳位的功率开关装置，作为一个耦合变压器推拉式整流器的一对主开关场效应晶体管，其中所述耦合变压器推拉式整流器具有一个最大DC供应电压VIN_MAX，两个所述稳压二极管的第一引线相互连接，从而使得所述两个具有完整VDS钳位的功率开关装置在最大漏源电压被钳位在大约VIN_MAX＋1/2Vzx的情况下，执行推拉式功率开关的相应任务，并且所述主开关场效应晶体管是一个N沟槽FET，所述稳压二极管的第二引线是其负极。
4.如权利要求3所述的用于限制耦合变压器推拉式整流器的主开关场效应晶体管的最大漏源电压的电路，其特征在于，所述主开关场效应晶体管是一个底部漏极沟槽FET，所述稳压二极管是一个底部负极装置，并且二者共享其相应底部漏极和底部负极，在一个单一晶片上形成所述开关FET和稳压二极管，所述晶片具有普通的位于晶片基底顶部的N层（N-layer）。
5.如权利要求4所述的用于限制耦合变压器推拉式整流器的主开关场效应晶体管的最大漏源电压的电路，其特征在于，所述N层是一个N外延层。
6.一种用于限制耦合变压器推拉式整流器的主开关场效应晶体管的最大漏源电压的电路，其特征在于，包括：
两个具有完整VDS钳位的功率开关装置；
每个具有完整VDS钳位的功率开关装置包含一个开关晶体管和一个稳压二极管，所述开关晶体管具有一个源极引线、一个漏极引线和一个栅极引线；
所述稳压二极管具有一个稳压电压Vzx并且具有第一引线和第二引线，所述稳压二极管的第二引线进一步连接所述漏极引线；
其中，连接两个具有完整VDS钳位的功率开关装置，作为一个耦合变压器推拉式整流器的一对主开关场效应晶体管，其中所述耦合变压器推拉式整流器具有一个最大DC供应电压VIN_MAX，两个所述稳压二极管的第一引线相互连接，从而使得所述两个具有完整VDS钳位的功率开关装置在最大漏源电压被钳位在大约VIN_MAX＋1/2Vzx的情况下，执行推拉式功率开关的相应任务，并且所述主开关场效应晶体管是一个P沟槽FET，所述稳压二极管的第二引线是其正极。
7.一种用于限制耦合变压器推拉式整流器的主开关场效应晶体管（switching FET）的最大漏源电压（VDS）的方法，所述整流器具有一个最大DC供应电压VIN_MAX，所述最大漏源电压（VDS）被推拉式晶体管和整流器电路的漏电感加强，其特征在于，该方法包括基于所述最大漏源电压（VDS）超过漏源电压最大值（VDSmax）的倾向，自动生成一个内部漏极电流，所述内部漏极电流在一对主开关场效应晶体管的漏极间流动并具有相应的电能损耗，因此限制了最大漏源电压；
其中，自动生成内部漏极电流的过程进一步包括提供一个桥连接电路以连接在一对主开关场效应晶体管的各漏极之间；
提供桥连接电路的过程进一步包括提供一系列的相互连接的两个对立的稳压二极管，每一个所述稳压二极管都具有一个稳压电压Vzx，该Vzx被设定略微大于或等于2×VIN_MAX，因此最大漏源电压的值大约为VIN_MAX＋1/2Vzx；
所述桥连接电路具有一种任一主开关场效应晶体管的漏源电压超过所述最大漏源电压（VDS）的倾向的非破坏性击穿。
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