CN101567318A

CN101567318A - Production method of transistor

Info

Publication number: CN101567318A
Application number: CNA2008100366563A
Authority: CN
Inventors: 赵猛
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2008-04-25
Filing date: 2008-04-25
Publication date: 2009-10-28

Abstract

The invention relates to a production method of a transistor, comprising the following steps: providing a semiconductor substrate; injecting a blocking layer on the surface of the semiconductor substrate to define a source electrode area and a drain electrode area; injecting doped ions and carbon ions into the source electrode area and the drain electrode area of the semiconductor substrate; and carrying out annealing treatment to the semiconductor substrate. The invention has the advantages of enhancing the carrier mobility of a source electrode and a drain electrode so as to improve the saturation current of the transistor, such as MOSFET.

Description

Transistorized manufacture method

[technical field]

The present invention relates to method for manufacturing integrated circuit, relate in particular to the carrier mobility that improves in the conducting channel, thereby improve the transistor fabrication process of transistor saturation current value.

[background technology]

Transistor, especially " metal-semiconductor-oxide " field-effect transistor (MOSFET) are one of most common components in the integrated circuit.The saturation current value is to weigh the important indicator of MOSFET performance.The saturation current value is high more to show that the driving force of MOSFET is strong more.

In the prior art,, be a kind of effective ways that can improve the transistor saturation current value by in Semiconductor substrate, introducing the carrier mobility that stress material improves conducting channel.For example, for typical MOSFET structure, the charge carrier that constitutes saturation current is to enter drain electrode or source electrode from the source electrode of MOSFET or drain electrode through conducting channel, the carrier mobility that improves conducting channel has been equivalent to reduce the resistance of carrier flow on the path, therefore can improve the saturation current of MOSFET.Application number is the manufacture method of a kind of MOSFET of disclosing in the United States Patent (USP) of US6492216, in the manufacturing process of MOSFET, the compound-material that epitaxial growth one deck is made of silicon, germanium and carbon with stress, with this material as conducting channel, can improve the carrier mobility in the conducting channel, reach the purpose that improves MOSFET saturation current value.

In the prior art, generally the method for Cai Yonging be have stress in semiconductor substrate surface growth material as conducting channel, realize improving the technique effect of transistor saturation current value.These class methods have mainly improved the carrier mobility of conducting channel, and do not change the carrier mobility of source electrode and drain electrode.Yet, source electrode and drain electrode also are to constitute the part of carrier flow through passage, under the identical situation of other technologies in manufacture process, if can improve the carrier mobility of source electrode or drain electrode, then can further improve the saturation current of transistor such as MOSFET, make it better electrology characteristic.

[summary of the invention]

Technical problem to be solved by this invention is that the transistor source of the saturation current that can improve MOSFET and the manufacture method of drain electrode are provided.

In order to address the above problem, the invention provides a kind of transistorized manufacture method, comprise the steps: to provide Semiconductor substrate; Make the injection barrier layer at semiconductor substrate surface, define source electrode and drain region; Source electrode and drain region with dopant ion and carbon ion injection Semiconductor substrate; Semiconductor substrate is carried out annealing in process.

In the technique scheme, can earlier dopant ion be injected the source electrode and the drain region of Semiconductor substrate, again carbon ion be injected the source electrode and the drain region of Semiconductor substrate; Also can earlier carbon ion be injected the source electrode and the drain region of Semiconductor substrate, again dopant ion be injected the source electrode and the drain region of Semiconductor substrate.

Described Semiconductor substrate is the p type single crystal silicon substrate.

Described dopant ion is a N type dopant ion.

Described N type dopant ion is arsenic, phosphorus or both combinations.

Described carbon ion is injected the injection energy that Semiconductor substrate adopts is 2.5keV～30keV, and implantation dosage is 1 * 10 ¹⁵Cm ^-2～1 * 10 ¹⁶Cm ^-2

Described annealing in process comprises rapid thermal annealing, and temperature is 950 ℃～1000 ℃, and the time is 30 seconds～300 seconds.

Described annealing is carried out pulse annealing before further being included in rapid thermal annealing.

The temperature of described pulse annealing is 1000 ℃～1050 ℃, and pulse number is 120 times～250 times, and each annealing time is no more than 1 second.

The invention has the advantages that the carrier mobility that can improve source electrode and drain electrode, thereby improve the saturation current of MOSFET.

[description of drawings]

Accompanying drawing 1 is the process chart of transistorized manufacture method embodiment provided by the present invention;

Accompanying drawing 2 is the implementation step schematic diagram of transistorized manufacture method embodiment provided by the present invention to accompanying drawing 5.

[embodiment]

Below in conjunction with accompanying drawing transistorized manufacture method provided by the present invention is described in detail.

Accompanying drawing 1 is the process chart of transistorized manufacture method embodiment provided by the present invention.Step S10 provides Semiconductor substrate; Step S11 makes the injection barrier layer at semiconductor substrate surface, defines source electrode and drain region; Step S12 injects dopant ion the source electrode and the drain region of Semiconductor substrate; Step S13 injects carbon ion the source electrode and the drain region of Semiconductor substrate; Step S14 carries out annealing in process to Semiconductor substrate.

Further specify the specific embodiment of the present invention hereinafter with reference to accompanying drawing 2 to accompanying drawing 5.Accompanying drawing 2 is the implementation step schematic diagram of transistorized manufacture method embodiment provided by the present invention to accompanying drawing 5.

Shown in the accompanying drawing 2, refer step S10 provides Semiconductor substrate 100.In this embodiment, described Semiconductor substrate 100 is the p type single crystal silicon substrate.As shown in the figure, on the surface of Semiconductor substrate 100, made grid stacked structure 101.In actual applications, described Semiconductor substrate 100 can be the various semi-conducting materials that the semiconductor applications technical staff knows, and comprises silicon, silicon-on-insulator (SOI) of polycrystalline structure etc.

Shown in the accompanying drawing 3, refer step S11 makes barrier layer 102 on Semiconductor substrate 100 surfaces.Barrier layer 102 will be positioned at the zone that need inject grid stacked structure 101 both sides comes out, and area exposed is transistorized source electrode and drain region.Grid stacked structure 101 also plays the effect that stops injection at this.Do not need to carry out the making barrier layer 102, position that ion injects on Semiconductor substrate 100 surfaces, can in ion implantation process, play the effect of injecting ion that stops.Common barrier material is silicon dioxide, silicon nitride or silicon oxynitride.Can adopt methods such as chemical deposition, physical deposition, thermal oxidation on the superficial growth barrier layer of Semiconductor substrate 100, and in the barrier layer, make figure to define source electrode and drain region.Graphic making can adopt known photoetching process of those skilled in that art or electron beam exposure technology etc.

Shown in the accompanying drawing 4, refer step S12 injects Semiconductor substrate 100 with dopant ion.Dopant ion will inject source electrode and the drain region that Semiconductor substrate 100 is defined by grid stacked structure 101 and barrier layer 102, after dopant ion injects, form source dopant zone 103 and drain doping region territory 104 in Semiconductor substrate.For the p type single crystal silicon substrate, the dopant ion that is adopted is a N type dopant ion, for example arsenic, phosphorus or both combinations.The implantation dosage of N type dopant ion is 1 * 10 ¹⁵Cm ^-2～1 * 10 ¹⁶Cm ^-2, the injection energy is 10keV～40keV.

Shown in the accompanying drawing 5, refer step S13 injects Semiconductor substrate with carbon ion.Carbon ion will inject source dopant zone 103 and the drain doping region territory 104 that Semiconductor substrate 100 is defined by grid stacked structure 101 and barrier layer 102.It is that 2.5keV～30keV, implantation dosage are 1 * 10 that carbon ion injects the injection energy that is adopted ¹⁵Cm ^-2～1 * 10 ¹⁶Cm ^-2Because carbon and silicon belong to IV family element together in the periodic table of elements, the carbon ion of injection can influence the lattice of source dopant zone 103 and drain doping region territory 104 monocrystalline silicon arranges, and produces stress at intracell.According to the knowledge of Semiconductor Physics, when intracell produces stress, can have influence on the symmetry status of lattice, thereby have influence on the migration of charge carrier in lattice.Inject the source dopant zone 103 and the drain doping region territory 104 of Semiconductor substrate 100 under with above-mentioned energy and dosage condition at carbon ion, can improve the migration rate of charge carrier in lattice.Therefore, carbon ion is injected source electrode can improve the carrier mobility of source electrode and drain electrode, improve the saturation current of MOSFET with drain electrode.Experiment showed, that under the identical situation of other conditions the method that adopts carbon ion to inject can be increased to the saturation current value of MOSFET more than the 600 μ A/ μ m from 500 μ A/ μ m, increase rate surpasses 20%.

Present embodiment adopts and injects N type dopant ion earlier, and the method for back injection carbon ion is carried out the doping of source electrode and drain electrode.Also can adopt and inject earlier carbon ion, the method for N type dopant ion is injected in the back, i.e. implementation step S13 at first, and implementation step S12 again, the method is compared with this embodiment and indistinction.

Step S14 carries out annealing in process to Semiconductor substrate 100.

Because the carbon ion that injects can cause the leakage current between source dopant zone 103 and the drain doping region territory 104 to increase in the inner defective cluster that forms of semiconductor, therefore need carry out annealing in process after injecting.Described annealing in process comprises rapid thermal annealing (RTA).The temperature of rapid thermal annealing is 950 ℃～1000 ℃; Time is 30 seconds～300 seconds.Rapid thermal annealing helps to eliminate the defective cluster, thereby reduces leakage current.Experiment shows, under the identical situation of other conditions, carries out rapid thermal annealing and can make leakage current be reduced to 0.07nA/ μ m from 0.01nA/ μ m, and the reduction amplitude is about 30%.

Before carrying out rapid thermal annealing, can also carry out pulse annealing, the pulse number of pulse annealing is 120 times～250 times, and each annealing time is no more than 1 second, and temperature is 1000 ℃～1050 ℃.Pulse annealing is annealing process commonly used in the prior art, and main effect is to promote dopant ion to form source electrode and drain electrode.Owing to adopted rapid thermal anneal process, so pulse annealing can be omitted.

Provide the embodiment of the manufacture method of transistor source of the present invention and drain electrode below:

The first step provides the p type single crystal silicon substrate, and substrate surface has the grid stacked structure;

In second step, make silicon dioxide on the surface of p type single crystal silicon substrate and inject the barrier layer, in order to define source electrode and drain region;

The 3rd step, phosphonium ion is injected source electrode and the drain region that the p type single crystal silicon substrate is defined by the silicon dioxide barrier layer, form source electrode and drain doping region territory, the implantation dosage of phosphonium ion is 6 * 10 ¹⁵Cm ^-2, the injection energy is 25keV;

The 4th step, carbon ion is injected the source electrode and the drain region of p type single crystal silicon substrate, implantation dosage is 4 * 10 ¹⁵Cm ^-2, the injection energy is 15keV;

The 5th step, the p type single crystal silicon substrate is carried out quick thermal annealing process, temperature is 1000 ℃, annealing time is 150 seconds.

The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims

1. a transistorized manufacture method is characterized in that, comprises the steps:

Semiconductor substrate is provided;

Make the injection barrier layer at semiconductor substrate surface, define source electrode and drain region;

Source electrode and drain region with dopant ion and carbon ion injection Semiconductor substrate;

Semiconductor substrate is carried out annealing in process.

2. transistorized manufacture method according to claim 1 is characterized in that, earlier dopant ion is injected the source electrode and the drain region of Semiconductor substrate, carbon ion is injected the source electrode and the drain region of Semiconductor substrate again.

3. transistorized manufacture method according to claim 1 is characterized in that, earlier carbon ion is injected the source electrode and the drain region of Semiconductor substrate, dopant ion is injected the source electrode and the drain region of Semiconductor substrate again.

4. transistorized manufacture method according to claim 1 is characterized in that, described Semiconductor substrate is the p type single crystal silicon substrate.

5. transistorized manufacture method according to claim 4 is characterized in that, described dopant ion is a N type dopant ion.

6. transistorized manufacture method according to claim 5 is characterized in that, described N type dopant ion is arsenic, phosphorus or both combinations.

7. transistorized manufacture method according to claim 1 is characterized in that, it is 2.5keV～30keV that carbon ion is injected the injection energy that Semiconductor substrate adopts.

8. transistorized manufacture method according to claim 1 is characterized in that, it is 1 * 10 that carbon ion is injected the implantation dosage that Semiconductor substrate adopts ¹⁵Cm ^-2～1 * 10 ¹⁶Cm ^-2

9. transistorized manufacture method according to claim 1 is characterized in that described annealing in process comprises rapid thermal annealing.

10. transistorized manufacture method according to claim 9 is characterized in that, the temperature of described rapid thermal annealing is 950 ℃～1000 ℃.

11. transistorized manufacture method according to claim 9 is characterized in that, the time of described rapid thermal annealing is 30 seconds～300 seconds.

12. transistorized manufacture method according to claim 9 is characterized in that, described annealing is carried out pulse annealing before further being included in rapid thermal annealing.

13. transistorized manufacture method according to claim 12 is characterized in that, the temperature of described pulse annealing is 1000 ℃～1050 ℃, and pulse number is 120 times～250 times, and each annealing time is no more than 1 second.