CN101540321B - Semiconductor device - Google Patents
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- CN101540321B CN101540321B CN 200910138719 CN200910138719A CN101540321B CN 101540321 B CN101540321 B CN 101540321B CN 200910138719 CN200910138719 CN 200910138719 CN 200910138719 A CN200910138719 A CN 200910138719A CN 101540321 B CN101540321 B CN 101540321B
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Abstract
A surface structure of the primary semiconductor element and a first P well 24b are provided in a principal surface of the N<-> drift layer 23. The temperature detecting diode 22 is constituted by a P<+> anode region 26 in a N well 25 in the first P well 24b and a N<+> cathode region 27 in the P<+> anode region 26, and separated from the primary semiconductor element by a PN junction. The first Pwell 24b is sufficiently high in concentration and sufficiently deep to prevent latch-up breakdown due to a parasitic thyristor. The P<+> anode region 26 and the N well 25 are short-circuited to prevent latch-up breakdown due to a parasitic thyristor as well. A temperature detecting diode 22 ' is located in a N well 25' in a first P well 24b' on the first principal surface of a N<-> drift layer 23'. The primary semiconductor element is provided in the N<-> drift layer 23'. A temperature detecting diode 22' is separated from the primary semiconductor element by a PN junction. The first P well 24b' is sufficiently high in concentration and sufficiently deep to prevent latch-up breakdown due to a parasitic thyristor. A side of the N well 25' is surrounded by a P<+> high-concentration region 28' which is higher in concentration than the first P well 24b', so that activation of an NPN transistor formed in the transverse direction can be suppressed. As a result, a semiconductor device equipped with a primary semiconductor element and a temperature detecting element is provided, wherein temperature characteristic is irrelevant to the state of the primary semiconductor and kept constant, high latch-up tolerance and high temperature detection accuracy are obtained.
Description
Background of invention
1. invention field
The present invention relates to a kind of semiconductor device that is equipped with main semiconductor element and detector unit.
2. Description of Related Art
People wish to have the thermal breakdown of overheat protective function to prevent that semiconductor device from causing owing to overload current for the semiconductor device of power switch.Use diode to be commonly referred to as overheat protective function according to the function of temperature generation forward and reverse characteristic variation.For example, the forward voltage of diode changes according to temperature linearity basically.Therefore, when semiconductor device and diode were used separately as main element (hereinafter referred to as making main semiconductor element) and detector unit, the temperature of main semiconductor element can be detected (for example referring to patent documentation 1,2 and 3) by the forward voltage that the diode of constant current is wherein flow through in monitoring.Gate voltage by reducing main semiconductor element in response to the condition of high temperature that detects main semiconductor element is to limit the electric current in the main semiconductor element, and main semiconductor element can be protected, is unlikely to puncture owing to overheated.
The sectional view of Figure 11 has shown the structure according to the semiconductor device of correlation technique.As shown in figure 11, the semiconductor device according to correlation technique has N
-Surface texture and the temperature detection diode 2 of drift layer 3, main semiconductor element 1.The surface texture of main semiconductor element 1 and the first first type surface that temperature detection diode 2 is arranged in N-drift layer 3.The surface texture of main semiconductor element 1 has P base 4a, N
+Emission (source) district 5, gate insulating film 6, gate electrode 7 and emission (source) electrode 8.Detector unit 2 has p type anode district (P base 4b and P
+District 9), N
+ Cathodic region 10, anode electrode (not shown) and cathode electrode (not shown).
On the other hand, the semiconductor device that have main semiconductor element 1, is formed on the dielectric film 11 on first first type surface of composition semiconductor device of main semiconductor element 1 and is formed on the temperature detection diode 2 on the dielectric film 11 is used as the representative (for example referring to patent documentation 4) of semiconductor device shown in Figure 12 usually.In addition, the thermistor of the heat of sending for detection of switching circuit and rectification circuit in power model is placed near switching circuit and the rectification circuit, this be known (for example referring to patent documentation 5).In this specification and accompanying drawing, represent respectively wherein that with the floor of N or P prefix or district electronics or hole are majority carriers.In addition, with "+" that append to N or P or "-" upper target floor distinguish presentation layer respectively or the ratio of the impurity concentration in district with any N of appending to or P "+" or "-" upper target floor or distinguish higher or lower.
" patent documentation 1 " JP-A-1-157573 (US 4903106 A)
" patent documentation 2 " JP-A-2006-302977 (US 2006255361 A1)
" patent documentation 3 " Japan Patent No.3538505
" patent documentation 4 " JP-A-6-117942
" patent documentation 5 " JP-A-2005-286270
In semiconductor device shown in Figure 11, yet by anode region and the N of temperature detection diode
-Drift layer forms parasitic diode.When raceway groove was formed in the main semiconductor element, the electric current in the raceway groove also flow through parasitic diode.For this reason, occur a problem here, namely the forward voltage of temperature detection diode is in opening or closed condition along with main semiconductor element and changes.
In addition, when main semiconductor element was IGBT (insulated gate bipolar transistor), parasitic thyristor (thyristor) was by P current collection layer, N in the second first type surface
-P type anode district and the N of drift layer and temperature detection diode
+The cathodic region forms.When this IGBT is closed, risk can occur: the fault of parasitic thyristor will cause that breech lock punctures because as the hole of majority carrier by from N
-Drift layer injects the anode region.
Disclosed in the patent documentation 3 that main semiconductor element and temperature detection diode are mentioned in front by the structure of electric insulation and isolation.In this structure, yet form parasitic thyristor by main semiconductor element and temperature detection diode.For this reason, a problem appears here, namely when switch voltage change (dV/dt) when large and when current value is large parasitic thyristor can cause the breech lock puncture.
On the other hand, in semiconductor device shown in Figure 12, because the temperature detection diode is formed by polysilicon (polycrystal silicon), the forward voltage of temperature detection diode can change.In addition because leakage current is large in the extreme, the temperature correlation sexual deviation of cut-in voltage theoretical curve.Owing to these reasons, the low problem of precision of the temperature detection of main semiconductor element can appear here.In addition, because it is little to be formed on the size of the temperature detection diode on the dielectric film, the low problem of the static tolerance limit of temperature detection diode and main semiconductor element can appear to the slow problem of the response speed of variations in temperature here.The remarkable problem that rises of quantity that can occur in addition, manufacturing step here.Especially, when main semiconductor element is trench gate type element, can not detect diode with the doped polycrystalline silicon formation temperature, although doped polycrystalline silicon generally is used for gate electrode.That is to say, can occur the problem that the quantity of manufacturing step further rises here because need to by with gate electrode dividually stacked polysilicon go formation temperature to detect diode.
People wish that further the semiconductor device that is used for power switch has the thermal breakdown of overheat protective function to prevent that semiconductor device from causing owing to overload current.Use diode to be commonly referred to as overheat protective function according to the function of temperature generation forward and reverse characteristic variation.For example, the saturation voltage of diode changes according to temperature linearity basically.Therefore, when semiconductor device and diode were used separately as main element (hereinafter referred to as making main semiconductor element) and detector unit, the temperature of main semiconductor element can be detected (for example referring to patent documentation 1,2,3 and 4) by the saturation voltage of monitor diode.Limit electric current in the main semiconductor element by the gate voltage that reduces main semiconductor element in response to the condition of high temperature that detects main semiconductor element, main semiconductor element can be protected, is unlikely to puncture owing to overheated.
The sectional view of Figure 21 has shown the structure according to the semiconductor device of correlation technique.As shown in figure 21, the semiconductor device according to correlation technique has N
-Drift layer 3 ', main semiconductor element 1 ' surface texture and temperature detection diode 2 '.Main semiconductor element 1 ' surface texture and temperature detection diode 2 ' be positioned at N-drift layer 3 ' the first first type surface on.Main semiconductor element 1 ' surface texture have P base 4a ', N
+The emission (source) district 5 ', gate insulating film 6 ', gate electrode 7 ' and the emission (source) electrode 8 '.Detector unit 2 ' have p type anode district (P base 4b ' and P
+The district 9 '), N
+Cathodic region 10 ', anode electrode (not shown) and cathode electrode (not shown).
On the other hand, have main semiconductor element 1 ', be formed on main semiconductor element 1 ' the first first type surface of composition semiconductor device on dielectric film 11 ' and be formed on dielectric film 11 ' on temperature detection diode 2 ' semiconductor device usually be used as the representative (for example referring to patent documentation 5) of semiconductor device shown in Figure 22.In this specification and accompanying drawing, represent respectively wherein that with the floor of N or P prefix or district electronics or hole are majority carriers.In addition, with "+" that append to N or P or "-" upper target floor distinguish presentation layer respectively or the ratio of the impurity concentration in district with any N of appending to or P "+" or "-" upper target floor or distinguish higher or lower.
" patent documentation 1 " JP-A-1-157573 (US 4903106 A)
" patent documentation 2 " JP-A-2006-324412
" patent documentation 3 " Japan Patent No.3538505
" patent documentation 4 " JP-A-2006-302977 (US 2006255361 A1)
" patent documentation 5 " JP-A-6-117942
In semiconductor device shown in Figure 21, yet by anode region and the N of temperature detection diode
-Drift layer forms parasitic diode.When raceway groove is formed in the main semiconductor element, the electric current in the raceway groove also flows through parasitic diode.For this reason, occur a problem here, namely the saturation voltage of temperature detection diode is in opening or closed condition along with main semiconductor element and changes.In addition, when main semiconductor element was IGBT, parasitic thyristor was by P current collection layer, N in the second first type surface
-P type anode district and the N of drift layer and temperature detection diode
+The cathodic region forms.When IGBT is closed, risk can occur: the fault of parasitic thyristor will cause that breech lock punctures because as the hole of majority carrier by from N
-Drift layer injects the anode region.
On the other hand, in semiconductor device shown in Figure 22, because the temperature detection diode is formed by polysilicon (polycrystal silicon), so the saturation voltage of temperature detection diode can change.In addition because leakage current is large in the extreme, the temperature correlation sexual deviation of cut-in voltage theoretical curve.Owing to these reasons, the low problem of precision of the temperature detection of main semiconductor element can appear here.In addition, because it is little to be formed on the size of the temperature detection diode on the dielectric film, the low problem of the static tolerance limit of temperature detection diode and main semiconductor element can appear to the slow problem of the response speed of variations in temperature here.The remarkable problem that rises of quantity that can occur in addition, manufacturing step here.Especially, when main semiconductor element is trench gate type element, can not detect diode with the doped polycrystalline silicon formation temperature, although doped polycrystalline silicon generally is used for gate electrode.That is to say, can occur the problem that the quantity of manufacturing step further rises here because need to by with gate electrode dividually stacked polysilicon go formation temperature to detect diode.
Brief summary of the invention
In order to solve the problems referred to above of correlation technique, the purpose of this invention is to provide a kind of semiconductor device that has with the detector unit of the irrelevant steady temperature characteristic of the state of main semiconductor element that is equipped with.
Another object of the present invention provides a kind of semiconductor device of high breech lock tolerance limit.
A further purpose of the present invention provides a kind of semiconductor device of high-temperature accuracy of detection.
In order to address the above problem and to reach these purposes, semiconductor device according to the invention is equipped with main semiconductor element and for detection of the detector unit of main semiconductor element temperature.The surface texture of main semiconductor element is arranged in the first type surface of the first semiconductor layer with first conduction type.The second semiconductor region with second conduction type and the surface texture of main semiconductor element separate and optionally are arranged in the first type surface of the first semiconductor layer.The 3rd semiconductor region with first conduction type is positioned at the second semiconductor region.The 4th semiconductor region with second conduction type is arranged in the 3rd semiconductor region.The 5th semiconductor region with first conduction type is arranged in the 4th semiconductor region.The 3rd semiconductor region and the 4th semiconductor region are electrically connected.Detector unit forms diode, this diode with the 4th semiconductor region as one in anode and the negative electrode, and with the 5th semiconductor region as in anode and the negative electrode another.
The second semiconductor region can or be connected to the grounding electrode of main semiconductor element with the electrode electric insulation of main semiconductor element.The second semiconductor region can be centered on by groove.
According to the present invention, even when raceway groove is formed in the main semiconductor element, the electric current in the raceway groove is not affected by the temperature characterisitic of detector unit yet, because detector unit is by knot and main semiconductor element isolation.In addition, the second semiconductor region can suppress the activation of parasitic thyristor.The electrical connection of the 3rd semiconductor region and the 4th semiconductor region can suppress the activation of parasitic thyristor.The transistorized activation of npn that is formed on the direction (as laterally) of intersecting with depth direction can be stoped by groove, so that the activation of parasitic thyristor can be prevented from.By form main semiconductor element and temperature element (TE in the first semiconductor layer, the temperature of main semiconductor element can accurately be detected.
Semiconductor device according to the invention has an effect: a kind of semiconductor device that has with the detector unit of the irrelevant steady temperature characteristic of the state of main semiconductor element that is equipped with can be provided.Another effect is: the semiconductor device that a kind of high breech lock tolerance limit can be provided.Another effect is: the semiconductor device that a kind of high-temperature accuracy of detection is provided.
Description of drawings
The sectional view of Fig. 1 has shown the structure according to the semiconductor device of the embodiment of the invention 1;
The vertical view of Fig. 2 has shown an example according to the semiconductor device plane layout of the embodiment of the invention 1;
The vertical view of Fig. 3 has shown another example according to the semiconductor device plane layout of the embodiment of the invention 1;
The sectional view of Fig. 4 has shown the structure according to the semiconductor device of the embodiment of the invention 2;
The sectional view of Fig. 5 has shown the structure according to the semiconductor device of the embodiment of the invention 3;
The vertical view of Fig. 6 has shown an example according to the semiconductor device plane layout of the embodiment of the invention 3;
The sectional view of Fig. 7 has shown the structure according to the semiconductor device of the embodiment of the invention 4;
The sectional view of Fig. 8 has shown the structure according to the semiconductor device of the embodiment of the invention 5;
The sectional view of Fig. 9 has shown the structure according to the semiconductor device of the embodiment of the invention 6;
The vertical view of Figure 10 has shown an example according to the semiconductor device plane layout of the embodiment of the invention 6;
The sectional view of Figure 11 has shown an example according to the semiconductor device structure of correlation technique; And
The sectional view of Figure 12 has shown another example according to the semiconductor device structure of correlation technique;
The sectional view of Figure 13 has shown the structure according to the semiconductor device of the embodiment of the invention 7;
The sectional view of Figure 14 has shown the structure according to the semiconductor device of the embodiment of the invention 8;
The sectional view of Figure 15 has shown the structure according to the semiconductor device of the embodiment of the invention 9;
The sectional view of Figure 16 has shown the structure according to the semiconductor device of the embodiment of the invention 10;
The sectional view of Figure 17 has shown the structure according to the semiconductor device of the embodiment of the invention 11;
The vertical view of Figure 18 has shown an example according to the semiconductor device plane layout of the embodiment of the invention 11;
The vertical view of Figure 19 has shown another example according to the semiconductor device plane layout of the embodiment of the invention 11;
The sectional view of Figure 20 has shown the structure according to the semiconductor device of the embodiment of the invention 12;
The sectional view of Figure 21 has shown an example according to the semiconductor device structure of correlation technique; And
The sectional view of Figure 22 has shown another example according to the semiconductor device structure of correlation technique;
Detailed description of preferred embodiment
Describe below with reference to the accompanying drawings the present invention in detail about the preferred embodiment of semiconductor device.In the following description of embodiment and accompanying drawing, identical structure is used identical Reference numeral or symbolic representation, and the description that repeats will be omitted.
Embodiment 1
The sectional view of Fig. 1 has shown the structure according to the semiconductor device of the embodiment of the invention 1.As shown in Figure 1, semiconductor device 100 has a P trap 24b, and it is as the first semiconductor layer N
-The second semiconductor region in the first first type surface of drift layer 23.The 3rd semiconductor region N trap 25 is arranged in a P trap 24b.Temperature detection diode (detector unit) 22 is arranged in N trap 25.
That is to say high concentration P
+Anode region 26 is arranged in N trap 25 as the 4th semiconductor region.High concentration N
+ Negative contact zone 27 is positioned at P as the 5th semiconductor region
+In the anode region 26.Anode electrode (A) 28 and P
+Anode region 26 and 25 contacts of N trap.That is to say P
+Anode region 26 and N trap 25 are by anode electrode 28 short circuits.Cathode electrode (K) 29 and N
+ Negative contact zone 27 contacts.
The one P trap 24b has sufficiently high concentration to stop the breech lock that is caused by parasitic thyristor to puncture.In addition, a P trap 24b is enough deeply to stop the breech lock that is caused by parasitic thyristor to puncture.For example, a P trap 24b is insulated film 30 coverings and electricity is floated.That is to say that semiconductor device 100 further is equipped with main semiconductor element, wherein this main semiconductor element is not shown but by N
-Drift layer 23 forms.For example, a P trap 24b is free of attachment to any electrode of main semiconductor element.Temperature detection diode 22 is by the PN junction between a P trap 24b and the N trap 25 and unshowned main semiconductor element isolation.
At N
-The first first type surface of drift layer 23, the 2nd P trap 24c are positioned at the outside of a P trap 24b in order to isolate with a P trap 24b.For example, the 2nd P trap 24c forms shunt (diverter) to extract the hole.In this case, for example, the hole is extracted electrode 31 and is contacted with the 2nd P trap 24c.The electromotive force identical with emitter (source electrode) electromotive force of unshowned main semiconductor element extracts electrode 31 by the hole and is applied to the 2nd P trap 24c.
When main semiconductor element was vertical IGBT, P collector region 36 and collector electrode 37 were positioned at N
-In the second first type surface of drift layer 23.When main semiconductor element was vertical MOSFET (mos field effect transistor), N drain region 38 and drain electrode 39 were positioned at N
-In the second first type surface of drift layer 23.
The vertical view of Fig. 2 has shown an example according to the semiconductor device plane layout of the embodiment of the invention 1.As shown in Figure 2, the plane layout of semiconductor device 100 has with N
+Cathodic region 27 is the concentrically ringed shape at its center.Fig. 3 has shown the plane layout of the situation that a plurality of temperature detection diodes 22 are provided, and for example, can provide three temperature detection diodes 22 although the quantity of temperature detection diode 22 is not specifically limited.As shown in Figure 3, three temperature detection diodes 22 are arranged and the 2nd P trap 24c is provided to around three temperature detection diodes 22 abreast.
For the manufacturing of semiconductor device shown in Figure 1 100, a P trap 24b can form in the P type field limiting ring of the compression-resistant structure part that forms unshowned main semiconductor element or P type RESURF layer.Like this, the manufacturing process of semiconductor device 100 can be simplified, and does not form a P trap 24b because do not need to separate with main semiconductor element.In addition, P
+Anode region 26 can be at the P that forms main semiconductor element
+Form in the time of the tagma.In addition, N
+ Negative contact zone 27 can be at the N that forms main semiconductor element
+Emission (source) formed in the time of the district.Like this, the manufacturing process of semiconductor device 100 can further be simplified, and does not form P because do not need to separate with main semiconductor element
+Anode region 26 and N
+ Negative contact zone 27.
In addition, a P trap 24b and N trap 25 can form when forming P type field limiting ring or P type RESURF layer.Formation and P when a P trap 24b and N trap 25
+ Anode region 26 and N
+When the formation of negative contact zone 27 was used to the manufacturing of semiconductor device 100, temperature detection diode 22 can be manufactured in the manufacturing process of main semiconductor element, and do not need additional any special technique.Therefore, the manufacturing that in contrast to the semiconductor device of correlation technique shown in Figure 12 of described manufacturing process can be simplified significantly.Under these circumstances, need to select the different ionic species of diffusion coefficient, be used to form p type island region and N-type district.For example, boron can be used as the ionic species that forms p type island region, and arsenic can be as the ionic species that forms the N-type district.
According to embodiment 1, even be formed in the main semiconductor element and electric current when in raceway groove, flowing when raceway groove, also can not have influence on the forward voltage of temperature detection diode 22, because temperature detection diode 22 and main semiconductor element are by the knot isolation.That is to say, can make a kind of temperature detection diode 22 that has with the irrelevant constant forward voltage of the state of main semiconductor element, because the forward voltage that can prevent temperature detection diode 22 changes with the state of main semiconductor element.In addition, can make a kind of semiconductor device 100 that is equipped with this temperature detection diode 22.
In addition, the activation of parasitic thyristor can be suppressed by a P trap 24b.In addition, the activation of the parasitic thyristor temperature detection diode 22 that can be centered on the 2nd P trap 24c as hole extraction district suppresses.In addition, the activation of parasitic thyristor can be by N trap 25 and P
+Short circuit between the anode region 26 suppresses.Thereby it is possible that the breech lock that the inhibition parasitic thyristor brings punctures, and is possible thereby make the semiconductor device 100 with high breech lock tolerance limit.In addition, in contrast to the simply structure of electric insulation and isolation of temperature detection diode 22 and main semiconductor element, main semiconductor element can more stably move.In addition, it is possible obtaining the high-temperature accuracy of detection, because in contrast to the device of the temperature detection diode that being equipped with of correlation technique form by polysilicon on the dielectric film, the variation of forward voltage is low and leakage current is little.In addition, main semiconductor element is high to the response speed of variations in temperature.
The sectional view of Fig. 4 has shown the structure according to the semiconductor device of the embodiment of the invention 2.As shown in Figure 4, except the P type channel region of a P trap 24b and unshowned main semiconductor element forms simultaneously, semiconductor device 200 with same way as configuration according to the semiconductor device 100 among the embodiment shown in Figure 11.The 2nd P trap 24c forms simultaneously with the P type channel region of main semiconductor element.Therefore, the degree of depth of the degree of depth of a P trap 24b and the 2nd P trap 24c is not to equate mutually all the time in embodiment 1.Although the degree of depth of the degree of depth of a P trap 24b and the 2nd P trap 24c is not particularly limited, the P trap 24b in example shown in Figure 1 is more shallow than the 2nd P trap 24c.On the other hand, the P trap 24b among the embodiment 2 shown in Figure 4 has the identical degree of depth with the 2nd P trap 24c.Identical among other structure and the embodiment 1.
The sectional view of Fig. 5 has shown the structure according to the semiconductor device of the embodiment of the invention 3.The vertical view of Fig. 6 has shown an example according to the semiconductor device plane layout of the embodiment of the invention 3.As illustrated in Figures 5 and 6, except a side of N trap 25 was centered on by trench gate structure 41, semiconductor device 300 was to form with same way as according to the semiconductor device 100 among the embodiment shown in Figure 11.In addition, transversely the generation of breech lock can be suppressed, because the transistorized activation of npn that is formed on transversely can be suppressed by trench gate structure 41.
Embodiment 4
The sectional view of Fig. 7 has shown the structure according to the semiconductor device of the embodiment of the invention 4.As shown in Figure 7, except the side of a P trap 24b was centered on by trench gate structure 41, semiconductor device 400 was to form with same way as according to the semiconductor device 100 among the embodiment shown in Figure 11.In addition, transversely the generation of breech lock can be suppressed, because the transistorized activation of npn that is formed on transversely can fully be suppressed by trench gate structure 41.Trench gate structure 41 is identical with embodiment 3.Identical among other structure and the embodiment 1.
The sectional view of Fig. 8 has shown the structure according to the semiconductor device of the embodiment of the invention 5.As shown in Figure 8, except electrode 32 and P trap 24b contact and the electromotive force identical with emitter (source electrode) electromotive force of unshowned main semiconductor element are applied to the P trap 24b by electrode 32, semiconductor device 500 is to form with same way as according to the semiconductor device 100 among the embodiment shown in Figure 11.That is to say that a P trap 24b is electrically connected to emission (source) electrode as the grounding electrode of main semiconductor element.Like this, the generation of the breech lock that is caused by high dV/dt can be suppressed, because change in voltage (dV/dt) becomes mild during switch.Identical among other structure and the embodiment 1.Incidentally, a P trap 24b also can be connected to the grounding electrode of main semiconductor element in the corresponding construction of embodiment 2 to 4.
The sectional view of Fig. 9 has shown the structure according to the semiconductor device of the embodiment of the invention 6.As shown in Figure 9, semiconductor device 600 comprises the temperature detection diode 22 of as shown in Figure 1 configuration and its peripheral structure.The 2nd P trap 24c consists of the extraction district, hole of shunt 51.Main semiconductor element 21 comprises P channel region 61, p
+Tagma 62, n
+Emission (source) district 63, gate insulating film 64, gate electrode 65 and emission (source) electrode 66.In example shown in Figure 9, it is integrated and use an identical pattern formation with emission (source) electrode 66 is the same that electrode 31 and emission (source) electrode 66 are extracted in the hole.
The vertical view of Figure 10 has shown an example of the plane layout of whole semiconductor device.As shown in figure 10, the active area 71 of main semiconductor element is centered on by compression-resistant structure part 72.Temperature detection diode 22 is arranged in active area 71.Anode weld pad 73, negative electrode weld pad 74 and grid weld pad 75 are positioned on the active area 71.Anode weld pad 73 and negative electrode weld pad 74 are connected to temperature detection diode 22 by anode tap 76 and cathode leg 77 respectively.P type field limiting ring or the P type RESURF layer described among the embodiment 1 are arranged in compression-resistant structure part 72.Incidentally, the structure of appropriate section that is arranged in the active area 71 of main semiconductor element is omitted at Figure 10, and is complicated to avoid figure.
In above description, the present invention is not restricted to above-described embodiment but various variations can be arranged.For example, the grid structure of main semiconductor element can be trench gate structure.In addition, be that N-type and the second conduction type are the P types although each embodiment is described to the first conduction type, when the first conduction type is P type and the second conduction type when being N-type, the present invention also can realize.
As mentioned above, semiconductor device according to the invention is useful for the semiconductor device that is equipped with for the detector unit of overtemperature protection purposes, and is particularly suitable for power semiconductor, such as IGBT or MOSFET.
The sectional view of Figure 13 has shown the structure according to the semiconductor device of the embodiment of the invention 7.As shown in figure 13, semiconductor device 100 ' have is positioned at the first semiconductor layer N
-Drift layer 23 ' the first first type surface in the second semiconductor region the one P trap 24b '.The 3rd semiconductor region N trap 25 ' be arranged in a P trap 24b '.Temperature detection diode (detector unit) 22 ' be arranged in N trap 25 '.
That is to say high concentration P
+Anode region 26 ' as the 4th semiconductor region and high concentration N
+ Negative contact zone 27 be arranged in N trap 25 '.Anode electrode (A) is connected to P
+Anode region 26 '.Cathode electrode (K) is connected to N
+ Negative contact zone 27 '.N
+Negative contact zone 27 ' be used for cathode electrode is contacted with N trap 25 ' low-resistance, this N trap 25 ' as cathode zone.The main semiconductor element of semiconductor device 100 ' further be equipped with, this main semiconductor element is not shown but by N
-Drift layer 23 ' formation.Temperature detection diode 22 ' and unshowned main semiconductor element by a P trap 24b ' and N trap 25 ' between PN junction isolate.
The one P trap 24b ' has sufficiently high concentration to stop the breech lock that is caused by parasitic thyristor to puncture.In addition, a P trap 24b ' enough deeply to stop the breech lock that is caused by parasitic thyristor to puncture.N trap 25 ' a side be used as the P of the 5th semiconductor region
+High concentration region 28 ' center on.P
+High concentration region 28 ' the have higher concentration than a P trap 24b '.P
+High concentration region 28 ' be insulated film 29 ' covering.The one P trap 24b ' and P
+High concentration region 28 ' floated by electricity.
At N
-Drift layer 23 ' the first first type surface in, the 2nd P trap 24c be positioned at a P trap 24b ' the outside in case with a P trap 24b ' isolation.For example, the 2nd P trap 24c ' is set to have the electromotive force identical with emitter (source electrode) electromotive force of unshowned main semiconductor element, thereby the 2nd P trap 24c ' is formed for extracting the shunt in hole.For example, semiconductor device 100 ' plane layout do not show, but have with P
+Anode region 26 ' be the concentrically ringed shape at its center.
For semiconductor device shown in Figure 13 100 ' manufacturing, a P trap 24b ' can form when forming unshowned guard ring.In addition, P
+Anode region 26 ' can be formed for so that there is the P of low resistance contact in the P type semiconductor district of electrode and main semiconductor device
+Form in the time of the contact zone.In addition, N
+Negative contact zone 27 ' can be formed for so that there is the N of low resistance contact in the N type semiconductor district of electrode and main semiconductor element
+Contact zone or N
+Emission (source) formed in the time of the district.Like this, semiconductor device 100 ' manufacturing process can be simplified.When these three steps all be used for semiconductor device 100 ' manufacturing the time, in contrast to the manufacturing of the semiconductor device of correlation technique shown in Figure 22, described manufacturing process can be simplified significantly because only have need to form N trap 25 ' additional process.
According to embodiment 7, even be formed in the main semiconductor element and electric current when in raceway groove, flowing when raceway groove, can not have influence on yet temperature detection diode 22 ' saturation voltage because temperature detection diode 22 ' isolate by knot with main semiconductor element.That is to say, can make a kind of have with the temperature detection diode 22 of the irrelevant constant saturation voltage of the state of main semiconductor element ', because can prevent temperature detection diode 22 ' saturation voltage change with the state of main semiconductor element.In addition, can make a kind of be equipped with this temperature detection diode 22 ' semiconductor device 100 '.
In addition, because the activation of parasitic thyristor can be by a P trap 24b ' inhibition, so the breech lock that parasitic thyristor brings puncture can be suppressed.In addition, the transistorized activation of npn on (direction of intersecting with depth direction) can be by P owing to be formed on laterally
+High concentration region 28 ' inhibition is so transversely the generation of breech lock can be suppressed.Therefore, make semiconductor device 100 with high breech lock tolerance limit ' be possible.In addition, it is possible obtaining the high-temperature accuracy of detection, because in contrast to the device of the temperature detection diode that being equipped with of correlation technique form by polysilicon on the dielectric film, the variation of saturation voltage is low and leakage current is little.In addition, main semiconductor element is high to the response speed of variations in temperature.Incidentally, P
+Anode region 26 ' and N
+Negative contact zone 27 ' can contact with each other.Like this, the variation of cut-in voltage can reduce.
The sectional view of Figure 14 has shown the structure according to the semiconductor device of the embodiment of the invention 8.As shown in figure 14, except N trap 25 ' a side by trench gate structure 31 ' rather than P
+High concentration region 28 ' outside centering on, semiconductor device 200 ' with according to the semiconductor device 100 among the embodiment shown in Figure 13 7 ' same way as form.Transversely the generation of breech lock can be prevented from, because laterally the transistorized activation of npn can be by trench gate structure 31 ' fully prevention.
The N trap 25 of trench gate structure 31 ' be arranged in a P trap 24b ' ' the end.Trench gate structure 31 ' expand than N trap 25 ' darker.Dielectric film 32 such as oxide-film ' be arranged in and trench gate structure 31 ' the part that contacts of semiconductor, namely be arranged in the inner circumferential surface of groove.Dielectric film 32 ' inside be filled with as polysilicon 33 ' conductor.Preferably, polysilicon 33 ' be set to have identical electromotive force with negative electrode.For example when the grid structure of main semiconductor element is trench gate structure, trench gate structure 31 ' can when forming the trench gate structure of main semiconductor element, form simultaneously.Identical among other structure and the embodiment 7.
The sectional view of Figure 15 has shown the structure according to the semiconductor device of the embodiment of the invention 9.As shown in figure 15, semiconductor device 300 ' the comprise temperature detection diode 22 of configuration ' and its peripheral structure as shown in figure 13.Yet the P trap 24b ' in the embodiment 7, a P trap 24b ' further extend in the horizontal so that a P trap 24b ' formation shunt 41 ' extraction district, hole 42 '.High concentration P
+Contact zone 43 ' be arranged in form shunt 41 ' the front surface of a part of a P trap 24b '.Extraction district, hole 42 ' be arranged to have with main semiconductor element 21 ' the identical electromotive force of emitter (source electrode) electromotive force.Have such structure, a P trap 24b ' has the electromotive force identical with emitter (source electrode) electromotive force.As a result, the generation of the breech lock that is caused by high dV/dt can be suppressed, because change in voltage (dV/dt) becomes mild during switch.
Alternatively, hole extraction district 42 ' can be formed by another P trap with a P trap 24b ' isolation.Like this, with embodiment 7 in same way as, form extraction district, hole 42 ' the P trap can be set to have with main semiconductor element 21 ' identical electromotive force and the P trap 24b ' of emitter (source electrode) electromotive force can float by electricity.Alternatively, hole extraction district 42 ' can be by forming with the P base of main semiconductor element 21 ' identical and the P base can be arranged to have the electromotive force identical with emitter (source electrode) electromotive force.
Although main semiconductor element 21 ' specifically do not limited, main semiconductor element 21 ' example comprise the vertical IGBT (insulated gate bipolar transistor) with planar gate structure, the vertical MOSFET (mos field effect transistor) with planar gate structure etc.When main semiconductor element 21 ' when being IGBT, P collector region 46 ' and collector electrode 47 ' be positioned at N
-Drift layer 23 ' the second first type surface in.When main semiconductor element 21 ' when being MOSFET, N drain region 48 ' and drain electrode 49 ' be positioned at N
-Drift layer 23 ' the second first type surface in.N
-Drift layer 23 ' the second main surface side structure also be applied among the embodiment 10 to 12.
The sectional view of Figure 16 has shown the structure according to the semiconductor device of the embodiment of the invention 10.As shown in figure 16, semiconductor device 400 ' the comprise temperature detection diode 22 of structure ' and its peripheral structure as shown in figure 14.As shown in figure 14 the main semiconductor element 21 of temperature detection diode 22 ' be suitable for of structure ' the grid structure be trench gate structure 51 ' situation because trench gate structure 31 ' be positioned at N trap 25 ' the end.Like this, temperature detection diode 22 ' trench gate structure 31 ' can form main semiconductor element 21 ' trench gate structure 51 ' in form.
In addition, shunt 41 ' extraction district, hole 42 ' formed by the P base.Extraction district, hole 42 ' have high concentration P at its front surface
+Contact zone 43 ' and be set to have with main semiconductor element 21 ' the identical electromotive force of the electromotive force of emitter (source electrode).Incidentally, a P trap 24b ' can electricity float and can be set to have with main semiconductor element 21 ' the identical electromotive force of the electromotive force of emitter (source electrode).
Embodiment 11
The sectional view of Figure 17 has shown the structure according to the semiconductor device of the embodiment of the invention 11.The vertical view of Figure 18 has shown an example according to the semiconductor device plane layout of the embodiment of the invention 11.As shown in figure 17, except shunt 41 ' extraction district, hole 42 ' by another P trap that arranges with a P trap 24b ' isolation form, semiconductor device 500 ' with according to the semiconductor device 400 among the embodiment shown in Figure 16 10 ' the same way as configuration.Like this, high concentration P
+Contact zone 43 be arranged in as hole extraction district 42 ' the front surface of P trap and hole extraction district 42 ' be set to have with main semiconductor element 21 ' the identical electromotive force of emitter (source electrode) electromotive force.The one P trap 24b ' can electricity float and can be set to have with main semiconductor element 21 ' the identical electromotive force of emitter (source electrode) electromotive force.
The vertical view of Figure 19 has shown another example according to the semiconductor device plane layout of the embodiment of the invention 11.Have in the semiconductor device plane layout that Figure 19 shows a plurality of temperature detection diodes 22 ', for example, although temperature detection diode 22 ' quantity be not specifically limited can provide four temperature detection diodes 22 '.As shown in figure 19, the extraction district, hole 42 of four temperature detection diodes 22 ' arrange abreast and shunt ' be configured to around four temperature detection diodes 22 '.
The sectional view of Figure 20 has shown the structure according to the semiconductor device of the embodiment of the invention 12.As shown in figure 20, except a P trap 24b ' extend in the horizontal with the mode identical with embodiment 9 form shunt 41 ' extraction district, hole 42 ', semiconductor device 600 ' with according to the semiconductor device 500 among the embodiment shown in Figure 17 11 ' the same way as configuration.This be equivalent to use one and identical pattern form a P trap 24b ' and extraction district, hole 42 '.Incidentally,---for example as shown in figure 13 the temperature detection diode 22 of configuration '---can be combined among the embodiment 10 to 12 to have the main semiconductor element of trench gate structure and do not have the temperature detection diode of any trench gate structure.
In above description, the present invention is not restricted to above-described embodiment but various variations can be arranged.For example, be that N-type and the second conduction type are the P types although each embodiment is described to the first conduction type, when the first conduction type is P type and the second conduction type when being N-type, the present invention also can realize.
As mentioned above, semiconductor device according to the invention is useful for the semiconductor device that is equipped with for the detector unit of overtemperature protection purposes, and is particularly suitable for power semiconductor, such as IGBT or MOSFET.
Claims (11)
1. semiconductor device, it is equipped with main semiconductor element and for detection of the detector unit of the temperature of described main semiconductor element, comprises:
The first semiconductor layer of the first conduction type, it has to provide the first type surface of the surface texture of described main semiconductor element;
The second semiconductor region of the second conduction type, the surface texture of itself and described main semiconductor element separates and optionally is arranged in the first type surface of described the first semiconductor layer;
The 3rd semiconductor region of the first conduction type, it is arranged in described the second semiconductor region;
The 4th semiconductor region of the second conduction type, it is arranged in described the 3rd semiconductor region; And
The 5th semiconductor region of the first conduction type, it is arranged in described the 4th semiconductor region; Wherein:
Described the 3rd semiconductor region is electrically connected with described the 4th semiconductor region; And
Described temperature detecting unit forms diode, and it as one in anode and the negative electrode, and will described the 5th semiconductor region be used as in described anode and the negative electrode another with described the 4th semiconductor region.
2. semiconductor device according to claim 1 is characterized in that, the electrode electric insulation of described the second semiconductor region and described main semiconductor element.
3. semiconductor device according to claim 1 is characterized in that, described the second semiconductor region is connected to the grounding electrode of described main semiconductor element.
4. the described semiconductor device of any one in 3 according to claim 1 is characterized in that described the second semiconductor region is centered on by groove.
5. semiconductor device, it is equipped with main semiconductor element and for detection of the detector unit of the temperature of described main semiconductor element, comprises:
The first semiconductor layer of the first conduction type, it forms described main semiconductor element;
The second semiconductor region of the second conduction type, it is arranged in described the first semiconductor layer;
The 3rd semiconductor region of the first conduction type, it is arranged in described the second semiconductor region; And
The 4th semiconductor region of the second conduction type, it is arranged in described the 3rd semiconductor region; Wherein:
Temperature detecting unit is arranged in a district by PN junction and the isolation of described the first semiconductor layer; And
Described temperature detecting unit forms diode, and it as one in negative electrode and the anode, and will described the 4th semiconductor region be used as in described negative electrode and the anode another with described the 3rd semiconductor region.
6. semiconductor device according to claim 5 is characterized in that, described the second semiconductor region electricity is floated.
7. semiconductor device according to claim 6 is characterized in that, further comprises: the 5th semiconductor region of the second conduction type, it centers on a side of described the 3rd semiconductor region and has the concentration higher than the second semiconductor region.
8. semiconductor device according to claim 5 is characterized in that, described the second semiconductor region has the electromotive force identical with one electromotive force in described main semiconductor element emitter and the source electrode.
9. semiconductor device according to claim 5 is characterized in that, described the 3rd semiconductor region is centered on than the darker groove of described the 3rd semiconductor region.
10. semiconductor device according to claim 9 is characterized in that, conductor dbus is crossed dielectric film and embedded in the groove, so that described conductor has the electromotive force identical with described negative electrode.
11. the described semiconductor device of any one in 10 is characterized in that described anode and negative electrode are centered on by hole extraction district according to claim 5.
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| JP2008-026412 | 2008-02-06 | ||
| JP2008026412A JP2009188178A (en) | 2008-02-06 | 2008-02-06 | Semiconductor device |
| JP2008026412 | 2008-02-06 | ||
| JP2008-029256 | 2008-02-08 | ||
| JP2008029256 | 2008-02-08 | ||
| JP2008029256A JP5365019B2 (en) | 2008-02-08 | 2008-02-08 | Semiconductor device |
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| CN101540321B true CN101540321B (en) | 2013-03-27 |
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| JP5990437B2 (en) * | 2012-09-10 | 2016-09-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| JP6117602B2 (en) * | 2013-04-25 | 2017-04-19 | トヨタ自動車株式会社 | Semiconductor device |
| US9728580B2 (en) * | 2013-05-13 | 2017-08-08 | Infineon Technologies Ag | Power transistor with integrated temperature sensor element, power transistor circuit, method for operating a power transistor, and method for operating a power transistor circuit |
| JP2016025155A (en) * | 2014-07-17 | 2016-02-08 | 株式会社東芝 | Semiconductor device |
| CN105206683B (en) * | 2015-10-15 | 2018-07-10 | 苏州汉克山姆照明科技有限公司 | A kind of current regulator diode structure |
| CN106098780B (en) * | 2016-07-27 | 2019-04-12 | 电子科技大学 | Silicon carbide VDMOS device of integrated temperature sensor and preparation method thereof |
| CN108417536B (en) * | 2017-02-10 | 2020-11-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method and working method thereof |
| WO2019080618A1 (en) * | 2017-10-24 | 2019-05-02 | 全球能源互联网研究院有限公司 | Insulated gate bipolar transistor structure and manufacturing method therefor |
| JP7206652B2 (en) * | 2018-03-30 | 2023-01-18 | 富士電機株式会社 | Semiconductor devices, semiconductor packages, semiconductor modules, and semiconductor circuit devices |
| CN110323273A (en) | 2018-03-30 | 2019-10-11 | 富士电机株式会社 | Semiconductor device, semiconductor packages, semiconductor module and semiconductor circuit arrangement |
| JP7113386B2 (en) * | 2018-12-17 | 2022-08-05 | パナソニックＩｐマネジメント株式会社 | semiconductor equipment |
| JP7260153B2 (en) * | 2019-03-29 | 2023-04-18 | ラピスセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
| CN112946450A (en) * | 2021-01-29 | 2021-06-11 | 陕西半导体先导技术中心有限公司 | Power semiconductor device convenient for junction temperature detection and junction temperature measuring method thereof |
| CN113745318B (en) * | 2021-09-03 | 2022-05-03 | 深圳市响河测控技术有限公司 | Power supply overheating protection circuit and calibration method thereof |
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| CN1622305A (en) * | 2003-11-27 | 2005-06-01 | 因芬尼昂技术股份公司 | Device and method for detecting the overheating of a semiconductor device |
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| JPS6089960A (en) * | 1984-08-06 | 1985-05-20 | Nec Corp | Semiconductor integrated circuit device |
| JPH0936356A (en) * | 1995-07-18 | 1997-02-07 | Fuji Electric Co Ltd | Application of bipolar semiconductor element comprising temperature detector |
| JP3538505B2 (en) * | 1996-05-22 | 2004-06-14 | 富士電機デバイステクノロジー株式会社 | Bipolar semiconductor device with built-in temperature detection unit and method of manufacturing the same |
| JP2001257366A (en) * | 2000-03-10 | 2001-09-21 | Toshiba Corp | Semiconductor device |
| JP4136372B2 (en) * | 2002-01-04 | 2008-08-20 | 富士電機デバイステクノロジー株式会社 | Semiconductor device |
| JP5028748B2 (en) * | 2005-04-15 | 2012-09-19 | 富士電機株式会社 | Temperature measurement device for power semiconductor devices |
| JP2006324412A (en) * | 2005-05-18 | 2006-11-30 | Renesas Technology Corp | Semiconductor device |
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| JP特开2006-324412A 2006.11.30 |
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| JP2009188178A (en) | 2009-08-20 |
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