CN101533814A - 芯片级倒装芯片封装构造 - Google Patents

芯片级倒装芯片封装构造 Download PDF

Info

Publication number
CN101533814A
CN101533814A CN200910132695A CN200910132695A CN101533814A CN 101533814 A CN101533814 A CN 101533814A CN 200910132695 A CN200910132695 A CN 200910132695A CN 200910132695 A CN200910132695 A CN 200910132695A CN 101533814 A CN101533814 A CN 101533814A
Authority
CN
China
Prior art keywords
metal
crystal grain
chip
level
package structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN200910132695A
Other languages
English (en)
Other versions
CN101533814B (zh
Inventor
资重兴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiequn Electronic Technology (Dongguan) Co., Ltd.
Original Assignee
PINESTAR CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PINESTAR CO Ltd filed Critical PINESTAR CO Ltd
Publication of CN101533814A publication Critical patent/CN101533814A/zh
Application granted granted Critical
Publication of CN101533814B publication Critical patent/CN101533814B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73255—Bump and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/842—Applying energy for connecting
    • H01L2224/84201—Compression bonding
    • H01L2224/84205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H01L2224/85207—Thermosonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/858—Bonding techniques
    • H01L2224/85895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明涉及一种芯片级倒装芯片封装构造，尤其涉及一种具有高散热及电性效能的芯片级倒装芯片封装构造。其主要构造包含一晶粒、一基板及一金属带。其中晶粒包含一背金属层及数个接合垫，并以数个凸块与基板接合。金属带是以金属扩散接合的方式与背金属层接合。利用本发明的封装构造，可提供半导体元件高散热能力及电性效能。

Description

芯片级倒装芯片封装构造
技术领域
本发明涉及一种芯片级倒装芯片封装构造，尤其涉及一种具有高散热及电性效能的芯片级倒装芯片封装构造。
背景技术
图1所示为现有技术中一功率晶体管(power transistor)倒装芯片(flip-chip)封装构造的剖面示意图。功率晶体管10的典型封装构造包含有一晶粒(die)14、一基板或导线架(lead-frame)12，及一金属盖(metal cap)16。
该晶粒14包含有数个接合垫(bond pad)141，形成于其下表面；一背金属层(back-side metal)143，形成于其上表面。数个凸块(bump)145分别形成于接合垫141上。该晶粒14是以其凸块145接合至基板或导线架12。
金属盖16的一端161连接至背金属层143，另一端163连接至基板或导线架12。两端161、163分别以焊锡(solder)或导电接合剂(conductive adhesive)147、167接合至背金属层及基板或导电架12。
然而，在将金属盖16与背金属层143或基板12接合时，以及以封装材料(molding compound)18进行封装时，经常会在焊锡或导电接合剂147、167中产生空洞或裂隙。而焊锡或导电接合剂147、167中的空洞或裂隙将会降低半导体元件的散热效率及电性效能。
图2所示为现有技术中功率晶体管方形扁平无引脚(quad flat no-lead；QFN)封装构造的剖面示意图。功率晶体管20的典型QFN封装构造包含有一晶粒24及一具有数个脚垫(lead)221、223、225的导线架22。
该晶粒24以一接合物质227(例如焊锡)接合至导线架22的脚垫223。晶粒24的上表面设有接合垫241及243。接合导线261及263的两端分别连接至接合垫241、243及导线架22的脚垫221、225。而后导线架22、晶粒24及接合导线261、263皆以一封装材料28加以封装。
此QFN封装构造由于晶粒24与导线架22具有较大的接触面积，故可提供较好的散热效果。但QFN封装构造的电性表现则因接合导线261、263狭小的截面积及较长的传导路径而受到限制。
发明内容
本发明的主要目的，在于提供一种芯片级倒装芯片封装构造，尤指一种具有高散热及电性效能的芯片级倒装芯片封装构造。
本发明的次要目的，在于提供一种芯片级倒装芯片封装构造，其中背金属层以一金属带连接至基板或导线架，可提供大的接触面积及大的传导截面积。
本发明的又一目的，在于提供一种芯片级倒装芯片封装构造，其中金属带以金属扩散接合方式接合至晶粒的背金属层，可防止金属带与背金属层间产生空洞或裂隙。
本发明的又一目的，在于提供一种芯片级倒装芯片封装构造，其中金属带以金属扩散接合方式接合至基板或导线架，可防止金属带与基板或导线架间产生空洞或裂隙。
本发明的又一目的，在于提供一种芯片级倒装芯片封装构造，还包含有一金属盖，接合至金属带及晶粒的背金属层，可提供较高的散热效能。
为达成上述目的，本发明提供一种芯片级倒装芯片封装构造，包含有一晶粒，包含有一第一表面及一第二表面；数个接合垫，形成于该晶粒的第二表面；数个凸块，分别形成于该数个接合垫上；一基板，以该数个凸块与该晶粒接合；一背金属层，形成于该晶粒的第一表面；及一金属带，包含有一第一端及一第二端，其中该第一端设置于该背金属层上，该第二端设置于该基板上。
本发明还提供一种芯片封装构造，包含有一基板；一晶粒，包含有一第一表面及一第二表面；数个接合垫，形成于该晶粒的第二表面，并有数个凸块形成于该数个接合垫与该基板间；一背金属层，形成于该晶粒的第一表面；一金属带，包含有一第一端及一第二端，其中该第一端以电性及热导性连接至该背金属层，该第二端以电性及热导性连接至该基板；及一金属盖，热导性连接至该金属带的第一端。
本发明的有益效果在于：利用本发明的封装构造，可提供半导体元件高散热能力及电性效能。
附图说明
图1为现有技术的功率晶体管倒装芯片封装构造的剖面示意图；
图2为现有技术的功率晶体管QFN封装构造的剖面示意图；
图3为本发明一较佳实施例的芯片级倒装芯片封装构造剖面示意图；
图4为本发明另一实施例的芯片级倒装芯片封装构造剖面示意图；
图5为本发明又一实施例的芯片级倒装芯片封装构造剖面示意图；
图6为本发明又一实施例的芯片级倒装芯片封装构造剖面示意图。
附图标记说明：10-功率晶体管；12-基板或导线架；14-晶粒；141-接合垫；143-背金属层；145-凸块；147-焊锡或导电接合剂；16-金属盖；161-一端；163-另一端；167-焊锡或导电接合剂；18-封装材料；20-功率晶体管；22-导线架；221-脚垫；223-脚垫；225-脚垫；24-晶粒；241-接合垫；243-接合垫；261-接合导线；263-接合导线；28-封装材料；30-半导体元件；32-基板；34-晶粒；341-接合垫；343-背金属层；345-凸块；36-金属带；361-一端；363-另一端；38-封装材料；40-半导体元件；42-基板；44-晶粒；441-接合垫；443-背金属层；445-大型凸块；46-金属带；461-一端；463-另一端；48-封装材料；50-半导体元件；52-金属盖；60-半导体元件；62-金属盖。
具体实施方式
以下结合附图，对本发明上述的和另外的技术特征和优点作更详细的说明。
图3所示为本发明一较佳实施例的芯片级(chip-scale)倒装芯片(flip-chip)封装构造剖面示意图。其中，半导体元件30，例如一功率晶体管(power transistor)，包含有一晶粒(die)34、一基板(substrate)32及一金属带(metal ribbon)36。
该晶粒34包含有一第一表面及一第二表面，例如一上表面及一下表面。该晶粒34的下表面形成有数个接合垫(bond pad)341。另有数个凸块(bump)345以金属扩散接合(metal diffusion bonding)的方式形成于该数个接合垫341上，无需于凸块345与接合垫341之间使用凸块底层金属(under bump metallurgy；UBM)。该晶粒34是以凸块345接合至该基板32，借以形成一倒装芯片接合。
晶粒34的上表面形成有一背金属层(back-side metal)343。该金属带36的一端361以金属扩散接合的方式接合至晶粒34的背金属层343，金属带36的另一端363亦以金属扩散接合的方式接合至基板32，借以建立晶粒34的背金属层343与基板32间的电性连结。当该电性连结被建立时，其热导性连结也同时被建立。最后，再以一封装材料(molding compound)38，例如一环氧树脂(epoxycompound)，将晶粒34、金属带36及基板32加以封装。
因为金属带36与晶粒34的背金属层343间具有大的接触面积与金属带36的大传导截面积，该半导体元件30的电性效能将会比现有技术的QFN封装构造元件优异。同时，晶粒34所产生的热量也较容易经由金属带36传递至基板32，再进一步传递到系统电路板。
在本发明中，该金属带36是以金属扩散接合的方式接合至晶粒34的背金属层343。如此，可防止金属带36与背金属层343的间产生空洞或裂隙。故本发明的半导体元件30的电性效能会比现有的倒装芯片封装构造的功率晶体管优秀许多。
在本发明的另一实施例中，半导体元件30的基板32可以用导线架取代，也可提供与前一实施例同样的散热效率与电性效能。
图4为本发明另一实施例的芯片级倒装芯片封装构造剖面示意图。半导体元件40，例如一功率晶体管，包含有一晶粒44、一基板42及一金属带46。
该晶粒44包含有一第一表面及一第二表面，例如一上表面及一下表面。数个接合垫441形成于该晶粒44的下表面。数个大型凸块(block bump)445以金属扩散接合的方式形成于该数个接合垫441上，无需在大型凸块445与接合垫441间使用UBM。该晶粒44以大型凸块445接合至基板42上，借以形成一倒装芯片接合。
一背金属层443形成于晶粒44的上表面。该金属带46的一端461设置于该晶粒44的背金属层443；金属带46的另一端则设置于基板42上，借以建立晶粒44的背金属层443与基板42的电性连结。当该电性连结被建立时，热导性连结也同时被建立。再以一封装材料48，例如环氧树脂，将晶粒44、金属带46及基板42加以封装。
由于金属带46与晶粒44的背金属层443具有大的接触面积及大的传导截面积，该半导体元件40的电性效能将会比现有的QFN封装构造的功率晶体管优异。同时，晶粒44所产生的热量也较容易经由金属带46传递至基板42，再进一步传递至系统电路板。
此外，在本实施例中，该大型凸块445可提供晶粒44与基板42之间的大接触面积，亦有利于提升半导体元件40的电性表现及散热效能。
在本发明中，该金属带46是以金属扩散接合的方式接合至晶粒44的背金属层343。如此，可防止金属带46与背金属层343之间产生空洞或裂隙。故本发明的半导体元件40的电性效能会比现有的倒装芯片封装构造的功率晶体管优秀许多。
在本发明的另一实施例中，半导体元件40的基板42可以用导线架取代，也可提供与前一实施例同样的散热效率与电性效能。
图5为本发明又一实施例的芯片级倒装芯片封装构造剖面示意图。如图所示，该半导体元件50的构造与图3所示实施例大致相同，包含有一晶粒34、一基板32及一金属带36，另外包含有一金属盖52。
该金属盖52是设置于该金属带36与背金属层343上，用以提供更高的散热效率。本实施例的封装构造是为散热需求更高的元件而提供。
由于金属盖52与元件的电性表现无关，故该金属盖52可以金属扩散接合、热声波接合(thermal-sonic bonding)、超音波压缩接合(ultrasonic-compressbonding)、热压缩接合(thermal-compress bonding)或焊接(soldering)的方式接合至金属带36与背金属层343。
图6为本发明又一实施例的芯片级倒装芯片封装构造剖面示意图。如图所示，该半导体元件60的构造与图4所示实施例大致相同，包含有一晶粒44、一基板42及一金属带46，另外包含有一金属盖62。
该金属盖62是设置于该金属带46与背金属层443上，用以提供更高的散热效率。本实施例的封装构造是为散热需求更高的元件而提供。
由于金属盖62与元件的电性表现无关，故该金属盖62可以金属扩散接合、热声波接合、超音波压缩接合、热压缩接合或焊接的方式接合至金属带46与背金属层443。
以上所述仅为本发明的较佳实施例，对本发明而言仅仅是说明性的，而非限制性的。本专业技术人员理解，在本发明权利要求所限定的精神和范围内可对其进行许多改变，修改，甚至等效，但都将落入本发明的保护范围内。

Claims (13)

1.一种芯片级倒装芯片封装构造，其特征在于包含有：
一晶粒，包含有一第一表面及一第二表面；
数个接合垫，形成于该晶粒的该第二表面；
数个凸块，形成于该数个接合垫上；
一基板，以该数个凸块与该晶粒接合；
一背金属层，形成于该晶粒的该第一表面；及
一金属带，包含有一第一端及一第二端，其中该第一端设置于该背金属层上，该第二端设置于该基板上。
2.如权利要求1所述的芯片级倒装芯片封装构造，其特征在于该金属带的第一端以金属扩散接合的方式接合至该背金属层。
3.如权利要求1所述的芯片级倒装芯片封装构造，其特征在于该金属带的第二端以金属扩散接合的方式接合至该基板。
4.如权利要求1所述的芯片级倒装芯片封装构造，其特征在于还包含有一封装材料，用以封装该晶粒及该金属带。
5.如权利要求1所述的芯片级倒装芯片封装构造，其特征在于还包含有一金属盖，设置于该金属带的第一端上。
6.如权利要求5所述的芯片级倒装芯片封装构造，其特征在于该金属盖以金属扩散接合的方式接合至该金属带的第一端。
7.如权利要求5所述的芯片级倒装芯片封装构造，其特征在于该金属盖以焊接的方式接合至该金属带的第一端。
8.如权利要求1所述的芯片级倒装芯片封装构造，其特征在于该数个凸块为数个球形凸块或数个大型方形凸块的其中之一，以金属扩散接合的方式直接形成于该数个接合垫上。
9.一种芯片封装构造，其特征在于包含有：
一基板；
一晶粒，包含有一第一表面及一第二表面，数个接合垫形成于该晶粒的第二表面，数个凸块形成于该数个接合垫及该基板之间；
一背金属层，形成于该晶粒的第一表面；
一带体，包含有一第一端及一第二端，其中该第一端以电性及热导性连接至该背金属层，该第二端以电性及热导性连接至该基板；及
一盖体，热导性连接至该带体的第一端。
10.如权利要求9所述的芯片封装构造，其特征在于该带体为一金属带，该金属带的第一端以金属扩散接合的方式电性及热导性连接至该背金属层。
11.如权利要求9所述的芯片封装构造，其特征在于该盖体为一金属盖，该金属盖以金属扩散接合的方式电性连接至该带体的第一端。
12.如权利要求9所述的芯片封装构造，其特征在于该盖体以焊接的方式热导性连接至该带体的第一端。
13.如权利要求9所述的芯片封装构造，其特征在于该数个凸块为数个金属球形凸块或金属大型方形凸块的其中之一，以金属扩散接合的方式直接形成于该数个接合垫上。
CN2009101326958A 2008-11-17 2009-04-07 芯片级倒装芯片封装构造 Active CN101533814B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11551908P 2008-11-17 2008-11-17
US61/115,519 2008-11-17

Publications (2)

Publication Number Publication Date
CN101533814A true CN101533814A (zh) 2009-09-16
CN101533814B CN101533814B (zh) 2011-10-12

Family

ID=41104319

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009101326958A Active CN101533814B (zh) 2008-11-17 2009-04-07 芯片级倒装芯片封装构造

Country Status (3)

Country Link
US (1) US20100123243A1 (zh)
CN (1) CN101533814B (zh)
TW (1) TW201021179A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102856273A (zh) * 2012-09-06 2013-01-02 日月光半导体制造股份有限公司 具有散热片的半导体组装构造及其组装方法
CN114024134A (zh) * 2021-10-26 2022-02-08 安徽蓝讯无线通信有限公司 一种用于通讯天线的ltcc封装结构

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI557813B (zh) * 2015-07-02 2016-11-11 萬國半導體（開曼）股份有限公司 超薄芯片的雙面暴露封裝結構及其製造方法
US9437528B1 (en) 2015-09-22 2016-09-06 Alpha And Omega Semiconductor (Cayman) Ltd. Dual-side exposed semiconductor package with ultra-thin die and manufacturing method thereof
JP2017112241A (ja) * 2015-12-17 2017-06-22 ルネサスエレクトロニクス株式会社 半導体装置
US10892210B2 (en) 2016-10-03 2021-01-12 Delta Electronics, Inc. Package structures
JP7054429B2 (ja) * 2019-03-13 2022-04-14 日亜化学工業株式会社 発光装置、発光モジュール及びその製造方法
DE102020204119A1 (de) * 2020-03-30 2021-09-30 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung eingetragener Verein Verfahren zur Verbindung von Komponenten bei der Herstellung leistungselektronischer Module oder Baugruppen

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005011986A (ja) * 2003-06-19 2005-01-13 Sanyo Electric Co Ltd 半導体装置
US20050121776A1 (en) * 2003-12-05 2005-06-09 Deppisch Carl L. Integrated solder and heat spreader fabrication
US7259028B2 (en) * 2005-12-29 2007-08-21 Sandisk Corporation Test pads on flash memory cards
US7569920B2 (en) * 2006-05-10 2009-08-04 Infineon Technologies Ag Electronic component having at least one vertical semiconductor power transistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102856273A (zh) * 2012-09-06 2013-01-02 日月光半导体制造股份有限公司 具有散热片的半导体组装构造及其组装方法
CN114024134A (zh) * 2021-10-26 2022-02-08 安徽蓝讯无线通信有限公司 一种用于通讯天线的ltcc封装结构
CN114024134B (zh) * 2021-10-26 2024-02-06 安徽蓝讯无线通信有限公司 一种用于通讯天线的ltcc封装结构

Also Published As

Publication number Publication date
CN101533814B (zh) 2011-10-12
TW201021179A (en) 2010-06-01
US20100123243A1 (en) 2010-05-20

Similar Documents

Publication Publication Date Title
CN101533814B (zh) 芯片级倒装芯片封装构造
US7691681B2 (en) Chip scale package having flip chip interconnect on die paddle
TWI429050B (zh) 堆疊式晶片封裝
TWI235469B (en) Thermally enhanced semiconductor package with EMI shielding
US10879203B2 (en) Stud bump structure for semiconductor package assemblies
US20120280404A1 (en) Stack packages having fastening element and halogen-free inter-package connector
TW201250885A (en) QFN package and manufacturing process thereof
US8022558B2 (en) Semiconductor package with ribbon with metal layers
KR20170086828A (ko) 메탈범프를 이용한 클립 본딩 반도체 칩 패키지
CN105789154A (zh) 一种倒装芯片模组
TW546792B (en) Manufacturing method of multi-chip stack and its package
TW200531188A (en) Land grid array packaged device and method of forming same
WO2006106569A1 (ja) 積層型半導体装置及びその製造方法
TWI278079B (en) Pillar grid array package
US7642639B2 (en) COB type IC package to enhanced bondibility of bumps embedded in substrate and method for fabricating the same
CN105206594B (zh) 单面蚀刻水滴凸点式封装结构及其工艺方法
CN203839371U (zh) 一种dram双芯片堆叠封装结构
CN101527285A (zh) 具有区域凸块的覆晶封装结构及其楔形接合方法
CN205542749U (zh) 一种倒装芯片模组
CN110970374A (zh) 一种倒装功率器件封装结构
CN210925986U (zh) 一种倒装功率器件封装结构
CN208806250U (zh) 一种半导体封装密封结构
JP2012146882A (ja) 半導体装置
TWI226117B (en) Flip chip on chip package with improving bonding property of wire-connecting pads
CN113707633A (zh) 光电传感器及其制备方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee

Owner name: JIEQUN SCI. + TECH. CO., LTD.

Free format text: FORMER NAME: PINESTAR CO., LTD.

CP01 Change in the name or title of a patent holder

Address after: The British Virgin Islands Tortora Island

Patentee after: Jiequn Technology Co., Ltd.

Address before: The British Virgin Islands Tortora Island

Patentee before: Pinestar Co., Ltd.

TR01 Transfer of patent right

Effective date of registration: 20191108

Address after: Buildings a and B, Jingcheng Science Park, Yuyuan Industrial Zone, Huangjiang Town, Dongguan City, Guangdong Province

Patentee after: Jiequn Electronic Technology (Dongguan) Co., Ltd.

Address before: The British Virgin Islands Tortora Island

Patentee before: Jiequn Technology Co., Ltd.

TR01 Transfer of patent right