CN101527285A - 具有区域凸块的覆晶封装结构及其楔形接合方法 - Google Patents
具有区域凸块的覆晶封装结构及其楔形接合方法 Download PDFInfo
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- CN101527285A CN101527285A CN200910132697A CN200910132697A CN101527285A CN 101527285 A CN101527285 A CN 101527285A CN 200910132697 A CN200910132697 A CN 200910132697A CN 200910132697 A CN200910132697 A CN 200910132697A CN 101527285 A CN101527285 A CN 101527285A
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Abstract
本发明涉及一种具有区域凸块的覆晶封装结构,其结构包括有一芯片、一基板、一第一区域凸块及一第二区域凸块;其中芯片包括有一主动面及一背面,一第一芯片接合垫及一第二芯片接合垫设置在主动面上,而一电极层设置在背面上;第一芯片接合垫及第二芯片接合垫分别透过第一区域凸块及第二区域凸块以电性连接至基板所布局的图样面上;此外,第一区域凸块及第二区域凸块借由一楔形接合方法所制作而成,如此将可轻易制作出较大尺寸的区域凸块,则芯片及基板间将因此具有一较低阻值的接触电阻及一较大的接触面积,进而提升覆晶封装结构的导电效率及散热效率。
Description
技术领域
本发明涉及一种具有区域凸块的覆晶封装结构及其楔形接合方法,可轻易制作出较大尺寸的区域凸块,借此以提升覆晶封装结构的导电效率及散热效率。
背景技术
覆晶接合技术目前广泛应用于半导体封装领域上,具有缩小封装尺寸及缩短讯号传导路径的优点,另外,常见应用覆晶接合技术的芯片封装结构包括有覆晶球格阵列(FCBGA)与覆晶针格阵列(FCPGA)。
图1A及图1B为现有的具有线柱形凸块的芯片俯视立体图及覆晶封装结构的结构示意图。
覆晶封装结构100包括有一芯片11、一基板13及数个线柱形凸块15。其中芯片11包括有一芯片接合垫111及一主动面112,并且该芯片接合垫111设置在芯片11的主动面112上。
基板13包括一图样面132,该图样面132具有数个导线布局的图样。此外,线柱形凸块15电性连接于芯片接合垫111与图样面132间,致使芯片11所产生的讯号将透过线柱形凸块15电性传导至基板13上。
就现有的覆晶封装结构100而言,芯片11的芯片接合垫111是透过线柱形凸块15电性连接至基板13上。由于,线柱形凸块15是经由一金线热声波接合技术(gold wire thermal-sonic bonding technology)所制作而成,其制作价格比一般晶圆凸块技术(wafer bumping technology)还要低。然而,线柱形凸块15是采用线球形接合技术(wire ball bonding technology)制作凸块的形状及尺寸,因此线柱形凸块15只能被制作为圆形态样,并且无法制作出较大尺寸的凸块。如此,当覆晶封装结构100需要一较低阻值的接触电阻及更佳的散热效率时,这受限形状的线柱形凸块15将会因此限制到覆晶封装结构100对于导电效率及散热效率提升的目的。
发明内容
本发明的主要目的,在于提供一种具有区域凸块的覆晶封装结构及其楔形接合方法,其可依照芯片特殊的电性需求,而将区域凸块设计成任何所需的矩形凸块尺寸。
本发明的次要目的,在于提供一种具有区域凸块的覆晶封装结构及其楔形接合方法,其区域凸块容易形成较大的尺寸面积,致使减少芯片及基板间的接触电阻以及增加芯片及基板间的接触面积,借此以提升覆晶封装结构的导电效率及散热效率。
为达成上述目的,本发明提供一种具有区域凸块的覆晶封装结构,其结构包括有:一基板,包括一图样面;一芯片,包括有一主动面及一背面,一第一芯片接合垫及一第二芯片接合垫设置在主动面上;一第一区域凸块,连接第一芯片接合垫及图样面;及一第二区域凸块,连接第二芯片接合垫及图样面。
本发明另提供一种具有区域凸块的覆晶封装结构,其结构包括有:一基板,包括一图样面;一芯片,包括有一主动面及一背面,一芯片接合垫设置在主动面上;及一区域凸块,电性连接芯片接合垫及图样面;其中,区域凸块是楔形接合的。
本发明还提供一种在芯片上形成区域凸块的楔形接合方法,其步骤包括有:提供一金属线;利用楔形的方式结合该金属线在一芯片的一芯片接合垫上,借此以形成一楔形接合;及切断该金属线与该楔形接合间的连接以形成一区域凸块。
本发明还提供所述的具有区域凸块的覆晶封装结构在功率晶体管上的应用。
附图说明
图1A为现有的具有线柱形凸块的芯片俯视立体图;
图1B为现有的覆晶封装结构的结构示意图;
图2A为本发明一较佳实施例的具有区域凸块的芯片俯视立体图;
图2B为本发明一较佳实施例的覆晶封装结构的结构示意图;
图3A为本发明另一实施例的具有区域凸块的芯片俯视立体图;
图3B为本发明另一实施例的覆晶封装结构的结构示意图;
图4为本发明一楔形接合方法的楔形结合装置的结构示意图;
图5A至图5B为本发明一楔形接合方法的接合处理的步骤流程图。
附图标记说明:100-覆晶封装结构;11-芯片;111-芯片接合垫;112-主动面;13-基板;132-图样面;15-线柱形凸块;200-覆晶封装结构;21-芯片;211-芯片接合垫;212-主动面;23-基板;232-图样面;25-区域凸块;300-覆晶封装结构;31-芯片;311-第一芯片接合垫;312-主动面;313-第二芯片接合垫;314-背板面;315-电极层;33-基板;332-图样面;35-第一区域凸块;36-第二区域凸块;40-楔型结合装置;41-金属线;411-楔形接合;413-颈端;42-夹具;421-通道;43-超音波传感器;44-楔形接合工具;45-切割器。
具体实施方式
以下结合附图,对本发明上述的和另外的技术特征和优点作更详细的说明。
图2A及图2B为本发明一较佳实施例的具有区域凸块的芯片俯视立体图及覆晶封装结构的结构示意图。如图所示,本发明覆晶封装结构200包括有一芯片21、一基板23及一区域凸块25,并且该基板23可为一印刷电路板。
其中,芯片21包括有一芯片接合垫211及一主动面212,该芯片接合垫211为一铝制的电极焊垫,并设置在该主动面212上。
基板23包括有一图样面232,该图样面232具有数个导线布局的图样。另外,芯片21的芯片接合垫211是透过区域凸块25电性连接至基板23的图样面232上。
一般覆晶技术需要在接合垫(I/O垫片)下形成凸块底下金属(under bumpmetal;UBM),然而,本发明中的区域凸块25能够直接连接至芯片接合垫211并不需要UBM,借此以减少覆晶封装结构200的制作流程,如此芯片21所产生的电子讯号即可透过区域凸块25的电性传导而顺利的传输至基板23上。此外,本发明区域凸块25可为一铝线/铝带、金线/金带或其他金属材质的线或带所制作而成。
本发明区域凸块25借由一楔形接合方法制作凸块的形状及尺寸,其相较于现有的线柱形凸块15可轻易制作出较大尺寸的凸块,再者,区域凸块25能够形成为一局部区域的凸块,而线柱形凸块15只能形成为一较小尺寸面积的圆形凸块。
区域凸块25可依照芯片的特殊电性需求而设计成任何所需的矩形凸块尺寸,借此提升覆晶封装结构200的导电效率及散热效率。例如:芯片接合垫211若作为一电源接合垫,芯片接合垫211必须具有较大的尺寸,相对的区域凸块25也将跟随着芯片接合垫211设计成较大的尺寸,则两者间即可提供一足够的电流导通面积及一较低的接触阻抗,借此以改善覆晶封装结构200的导电效率。此外,由于芯片接合垫211及区域凸块25具有较大的尺寸,则温度受热面积也将跟着增加,如此在进行完覆晶封装结构200的制作封装后,将可进一步改善温度散热的问题。
图3A及图3B为本发明另一实施例的具有区域凸块的芯片立体图及覆晶封装结构的结构示意图。如图所示,本实施例的覆晶封装结构300包括有一芯片31、一基板33、一第一区域凸块35及一第二区域凸块36。
其中芯片31包括有一主动面312及一背板面314,一第一芯片接合垫311及一第二芯片接合垫313设置在该主动面312上,而一电极层315设置在该背板面314上。第一芯片接合垫311为一铝制的源极电极焊垫,第二芯片接合垫313为一铝制的栅极电极焊垫,而电极层315为一漏极的电极层,并且第一芯片接合垫311的尺寸将于大于第二芯片接合垫313。
基板33包括有一图样面332,该图样面332包括有数个电路布局的图样。第一芯片接合垫311及第二芯片接合垫313分别透过第一区域凸块35及第二区域凸块36电性连接至图样面332。同样的,本实施例的第一区域凸块35及第二区域凸块36能够直接连接至第一芯片接合垫311及第二芯片接合垫313并不需要UBM,借此以减少覆晶封装结构200的制作流程。此外,第一区域凸块35的尺寸将于大于第二区域凸块36,并且两者可为一铝线/铝带、金线/金带或其他金属材质的线或带所制作而成。
本发明的第一区域凸块35及第二区域凸块36同样的借由一楔形接合方法制作凸块的形状及尺寸,其相较于现有的线柱形凸块15可轻易制作出较大尺寸的凸块,借此以提升覆晶封装结构300导电效率及散热效率,如此,本发明可排除现有的线球形接合技术(wire ball bonding technology)在制作凸块的形状及尺寸时所产生的限制,并且仍可保持较低的制作价格。
图4为本发明一楔形接合方法的楔形结合装置的结构示意图。如图所示,楔型结合装置40包括一金属线41(或可为一金属带)、一夹具42、一超音波传感器43及一楔形接合工具44。
其中夹具42包括有一通道421,金属线41夹在夹具42的通道421中,以在通道421内操作延伸。金属线41进一步透过通道421延伸连接至超音波传感器43,然后,超音波传感器43将金属线41连接至楔形接合工具44,以便金属线41沿着楔形接合工具44接合至芯片21的芯片接合垫211,并因此在芯片接合垫211上形成一楔形接合411。另外,楔形接合411借由一楔形接合方法来制作形成,并进一步透过一金属扩散技术来压合完成该楔形接合411,该金属扩散技术能够采用一超音波接合、一热音波接合或一热压接合的方式来进行压合的动作。
楔型结合装置40进一步包括一切割器45,在楔形接合411接合至芯片21的芯片接合垫211后,该切割器45将切割楔形接合411的颈端413,以切断金属线41与楔形接合411间的连接,而形成本发明的区域凸块25。
当然,本发明楔型结合方法也可运用在图3A及图3B实施例的芯片31上,以形成该第一区域凸块35或该第二区域凸块36。
图5A及图5B为本发明一楔形接合方法的接合处理的步骤流程图。首先,如图5A所示,楔型结合装置40降下至芯片21的芯片接合垫211上,并提供一金属线41至芯片21的芯片接合垫211,以透过楔型结合方法而形成楔型结合411在芯片21的芯片接合垫211上。
如图5B所示,在楔型结合411形成在芯片21的芯片接合垫211后,切割器45将进行一切割动作,切割器45降下至楔型结合411的颈端413处,切断金属线41与楔形接合411间的连接,接着,楔型结合装置40将从芯片21的芯片接合垫211脱离,最后以形成该区域凸块25。
以上所述仅为本发明的较佳实施例,对本发明而言仅仅是说明性的,而非限制性的。本专业技术人员理解,在本发明权利要求所限定的精神和范围内可对其进行许多改变,修改,甚至等效,但都将落入本发明的保护范围内。
Claims (16)
1.一种具有区域凸块的覆晶封装结构,其特征在于其结构包括有:
一基板,包括一图样面;
一芯片,包括有一主动面及一背面,一第一芯片接合垫及一第二芯片接合垫设置在所述主动面上;
一第一区域凸块,连接所述第一芯片接合垫及所述图样面;及
一第二区域凸块,连接所述第二芯片接合垫及所述图样面。
2.如权利要求1所述的覆晶封装结构,其特征在于所述第一芯片接合垫的尺寸大于所述第二芯片接合垫。
3.如权利要求1所述的覆晶封装结构,其特征在于所述第一芯片接合垫为一源极电极焊垫。
4.如权利要求1所述的覆晶封装结构,其特征在于所述第二芯片接合垫为一栅极电极焊垫。
5.如权利要求1所述的覆晶封装结构,其特征在于所述芯片的所述背面上设置有一电极层,所述电极层为一漏极电极层。
6.如权利要求1所述的覆晶封装结构,其特征在于所述第一区域凸块的尺寸大于所述第二区域凸块。
7.如权利要求1所述的覆晶封装结构,其特征在于所述第一区域凸块及所述第二区域凸块的材质选择为一铝线/铝带、一金线/金带或其他金属材质的线或带所制作而成。
8.如权利要求1所述的覆晶封装结构,其特征在于所述第一区域凸块及所述第二区域凸块直接连接所述第一芯片接合垫及所述第二芯片接合垫。
9.如权利要求1所述的覆晶封装结构,其特征在于所述第一区域凸块及所述第二区域凸块可依照所述芯片的特殊电性需求而设计成任何所需的矩形凸块尺寸。
10.一种具有区域凸块的覆晶封装结构,其结构包括有:
一基板,包括一图样面;
一芯片,包括有一主动面及一背面,一芯片接合垫设置在所述主动面上;及
一区域凸块,电性连接所述芯片接合垫及所述图样面;
其中,所述区域凸块是楔形接合的。
11.如权利要求10所述的覆晶封装结构,其特征在于所述区域凸块直接连接所述芯片接合垫。
12.如权利要求10所述的覆晶封装结构,其特征在于所述区域凸块的材质选择为一铝线/铝带、一金线/金带或其他金属材质的线或带所制作而成。
13.一种在芯片上形成区域凸块的楔形接合方法,其步骤包括有:
提供一金属线;
利用楔形的方式结合所述金属线在一芯片的一芯片接合垫上,借此以形成一楔形接合;及
切断所述金属线与所述楔形接合间的连接以形成一区域凸块。
14.如权利要求13所述的楔形接合方法,其特征在于所述楔形接合借由所述楔形接合方法来制作形成,并透过一金属扩散技术来压合完成所述楔形接合。
15.如权利要求14所述的楔形接合方法,其特征在于所述金属扩散技术采用一超音波接合、一热音波接合或一热压接合的方式。
16.如权利要求1所述的覆晶封装结构在功率晶体管上的应用。
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US10802508P | 2008-10-24 | 2008-10-24 | |
US61/108,025 | 2008-10-24 |
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US9064805B1 (en) * | 2013-03-13 | 2015-06-23 | Itn Energy Systems, Inc. | Hot-press method |
TWI823329B (zh) * | 2022-04-07 | 2023-11-21 | 頎邦科技股份有限公司 | 玻璃覆晶封裝方法及其晶片 |
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US6520399B1 (en) * | 2001-09-14 | 2003-02-18 | Raytheon Company | Thermosonic bonding apparatus, tool, and method |
JP4294405B2 (ja) * | 2003-07-31 | 2009-07-15 | 株式会社ルネサステクノロジ | 半導体装置 |
US8507320B2 (en) * | 2008-03-18 | 2013-08-13 | Infineon Technologies Ag | Electronic device including a carrier and a semiconductor chip attached to the carrier and manufacturing thereof |
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US20110031302A1 (en) | 2011-02-10 |
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