CN101527123A - Liquid crystal display device - Google Patents
Liquid crystal display device Download PDFInfo
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- CN101527123A CN101527123A CN200810065798A CN200810065798A CN101527123A CN 101527123 A CN101527123 A CN 101527123A CN 200810065798 A CN200810065798 A CN 200810065798A CN 200810065798 A CN200810065798 A CN 200810065798A CN 101527123 A CN101527123 A CN 101527123A
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Abstract
The invention provides a liquid crystal display device, which comprises a liquid crystal panel, an internal interface circuit and a control circuit. The liquid crystal panel comprises an active matrix and a source driver for driving the active matrix. The internal interface circuit comprises a connecting unit. The control circuit is connected to the source drive through the connecting unit. The connecting unit comprises a plurality of data pins for transmitting data signals, and the plurality of data pins are arranged adjacently. The display data signal is converted into a low voltage differential signal in the control circuit and is output to the source driver through the data pins of the connecting unit.
Description
Technical field
The invention relates to a kind of liquid crystal indicator.
Background technology
Liquid crystal indicator because have in light weight, little power consumption, radiation is low and advantage such as easy to carry and being used widely in electronic product.Along with the panel size and the resolution of liquid crystal indicator increases gradually, vision signal is subjected to the challenge of electromagnetic interference (EMI) increasing in liquid crystal indicator internal transmission process, present for this reason industry adopts low-swing difference signal usually, and (Reduced Swing Differential Signal, RSDS) form carries out video signal transmission.
Seeing also Fig. 1, is a kind of structural representation of prior art liquid crystal indicator.This liquid crystal indicator 100 comprises a liquid crystal panel 110, an internal interface circuit 180 and a control circuit 190.Wherein this internal interface circuit 180 is used to realize that the signal between this control circuit 190 and this liquid crystal panel 110 transmits.
This liquid crystal panel 110 comprises an active-matrix 150, a gate drivers 120, one first source electrode driver 130 and one second source electrode driver 140.Wherein this active-matrix 150 comprises the sweep trace X that many parallel interval are provided with
1, X
2... X
2m, many and this sweep trace X
1, X
2... X
2mVertically disposed data line Y insulate
1, Y
2... Y
2n, and a plurality of by this sweep trace X
1, X
2... X
2mWith this data line Y
1, Y
2... Y
2nSeparate the pixel cell 170 that defines and be matrix distribution.Wherein, this sweep trace X
1, X
2... X
2mBe connected to this gate drivers 120, this data line Y
1, Y
2... Y
nBe connected to this first source electrode driver 130, this data line Y
N+1, Y
N+2... Y
2nBe connected to this second source electrode driver 140.
This pixel cell 170 comprises a thin film transistor (TFT) 171, a pixel electrode 172 and a public electrode 173.To be positioned at i is listed as the capable pixel cell of j 170 and is designated as P
(i, j)(1≤i≤2m, 1≤j≤2n), then in the active-matrix 150 of this liquid crystal panel 110, be positioned at the 1st to all capable pixel cell P of n
(i, j)(1≤i≤2m, 1≤j≤n) drive the source electrode of its thin film transistor (TFT) 171 and this data line Y by this first source electrode driver 130
j(1≤j≤n) is corresponding to be connected, its grid and drain electrode respectively with this sweep trace X
i(1≤i≤2m) are connected with these pixel electrode 172 correspondences.And be positioned at n+1 to the capable pixel cell P of 2n
(i, j)(1≤i≤2m, n+1≤j≤2n) drive the source electrode of its thin film transistor (TFT) 171 and this data line Y by this second source electrode driver 140
j(n+1≤j≤2n) is corresponding to be connected, its grid and drain electrode also respectively with this sweep trace X
i(1≤i≤2m) are connected with these pixel electrode 172 correspondences.This pixel electrode 172, this public electrode 173 and be clipped in liquid crystal layer therebetween (figure do not show) and form a liquid crystal capacitance 174.
This internal interface circuit 180 comprises one first connector 101 and one second connector 102.This control circuit 190 comprises time schedule controller 192.This first connector 101 and this second connector 102 are respectively applied for the vision signal by these time schedule controller 150 outputs are sent to this liquid crystal panel 110.This vision signal comprises display data signal and clock signal.This display data signal is 6 R/G/B binary signals, and it adopts the low-swing difference signal form to transmit, and it comprises 6 red primary binary signals, 6 green primary binary signals and 6 blue primary binary signals.These 6 red primary binary signals, these 6 green primary binary signals and this 6 blue primary binary signals comprise three differential pairs respectively, and each differential pair comprises a positive signal and a negative polarity signal respectively.With these 6 blue primary binary signals is example, and the positive-negative polarity signal of its three differential pairs can be designated as B0P, B0N, B1P, B1N, B2P and B2N respectively; These 6 red primary binary signals and these 6 green primary binary signals can correspondingly carry out mark.
This first connector 101 comprises 50 pins (pins), and it is defined as pin respectively the first to the five No. ten.This second connector 102 comprises 30 pins, and it is defined as pin respectively the 51 to the eight No. ten.Wherein, each functions of pins is as shown in table 1 respectively.
Table 1
| Pin number | Function | Pin number | Function | Pin number | Function | | Function | |
| 1 | |
21 | CLKP-1 | 41 | GND | 61 | G0N-2 | |
| 2 | B0N-1 | 22 | |
42 | NC | 62 | G0P-2 | |
| 3 | B0P-1 | 23 | R0N-1 | 43 | NC | 63 | GND | |
| 4 | GND | 24 | R0P-1 | 44 | VDD | 64 | G1N-2 | |
| 5 | B1N-1 | 25 | |
45 | GND | 65 | G1P-2 | |
| 6 | B1P-1 | 26 | R1N-1 | 46 | VDD | 66 | |
|
| 7 | |
27 | R1P-1 | 47 | VDD | 67 | G2N-2 |
| 8 | B2N-1 | 28 | |
48 | VDD | 68 | G2P-2 |
| 9 | B2P-1 | 29 | R2N-1 | 49 | NC | 69 | GND |
| 10 | GND | 30 | R2P-1 | 50 | NC | 70 | CLKN-2 |
| 11 | G0N-1 | 31 | GND | 51 | GND | 71 | CLKP-2 |
| 12 | G0P-1 | 32 | STP-1 | 52 | B0N-2 | 72 | |
| 13 | |
33 | DLP | 53 | B0P-2 | 73 | R0N-2 |
| 14 | G1N-1 | 34 | POL | 54 | GND | 74 | R0P-2 |
| 15 | G1P-1 | 35 | STP-2 | 55 | B1N-2 | 75 | |
| 16 | |
36 | |
56 | B1P-2 | 76 | R1N-2 |
| 17 | G2N-1 | 37 | CLK- |
57 | GND | 77 | R1P-2 |
| 18 | G2P-1 | 38 | STP- |
58 | B2N-2 | 78 | GND |
| 19 | |
39 | OE- |
59 | B2P-2 | 79 | R2N-2 |
| 20 | CLKN-1 | 40 | |
60 | GND | 80 | R2P-2 |
Annotate: in the table 1, " *-1 " and " *-2 " represents corresponding with this first source electrode driver 130 and this second source electrode driver 140 respectively; " *-G " expression is corresponding with this gate drivers 120.GND represents ground connection (Ground), NC represents vacant (No Connection), CLK represents clock (Clock) signal, OE represents output enable (Output Enable) signal, STP represents initial pulse (Start Pulse) signal, POL represents output polarity (Polarity) control signal, and DLP represents data latching pulse (Data Latch Pulse) signal.
As can be seen from Table 1, all adopt a grounding pin to carry out electrical isolation between the pairing pin of each differential pair in this first connector 101 and this second connector 102, this mainly is because the low-swing difference signal form is by Low Voltage Differential Signal (Low VoltageDifferential Signal, LVDS) form development.Particularly, traditional Low Voltage Differential Signal is because the positive-negative polarity signal of each differential pair is subjected to the electromagnetic interference (EMI) of contiguous differential pair inconsistent in transmission course respectively, and because the voltage swing of Low Voltage Differential Signal big (about 400mV), thereby thereby its differential mode noise cause signal degradation more easily.Need between adjacent low-voltage differential is to pairing pin, adopt a grounding pin to carry out electrical isolation when therefore, tradition adopts the Low Voltage Differential Signal form to carry out the display data signal transmission to suppress differential mode noise.Based on same reason, when at present industry adopts the low-swing difference signal form to carry out data transmission, also can in first connector 101 of this internal interface circuit 180 and second connector 102, introduce a grounding pin between the pairing pin of adjacent differential pair usually and carry out electrical isolation.
But owing to introduce a large amount of grounding pins in first connector 101 of this internal interface circuit 180 and second connector 102, the pin number of this internal interface circuit 180 is bigger, make that thus the spent cost of this first connector 101 that this internal interface circuit 180 adopted and this second connector 102 is higher, and further cause the cost of this liquid crystal indicator 100 also higher.On the other hand, above-mentioned a large amount of grounding pin makes this first connector 101 and this second connector, 102 overall dimensionss increase, thereby these internal interface circuit 180 inner printed circuit board (PCB) and data lines that need to be equipped with respective area, this further increases the cost of this liquid crystal indicator 100.
Summary of the invention
For solving prior art liquid crystal indicator cost problem of higher, be necessary to provide a kind of liquid crystal indicator cheaply.
A kind of liquid crystal indicator, it comprises a liquid crystal panel, an internal interface circuit and a control circuit.This liquid crystal panel comprises that an active-matrix and is used to drive the source electrode driver of this active-matrix.This internal interface circuit comprises a linkage unit.This control circuit is connected to this source electrode driver by this linkage unit.This linkage unit comprises a plurality of data pin that are used for the transmitting and displaying data-signal, and the adjacent setting of these a plurality of data pin.This display data signal is converted to low-swing difference signal in this control circuit, and outputs to this source electrode driver by the data pin of this linkage unit.
A kind of liquid crystal indicator, it comprises a liquid crystal panel, an internal interface circuit and a control circuit.This liquid crystal panel comprises a plurality of pixel cells.This internal interface circuit comprises a linkage unit.This control circuit is connected to this liquid crystal panel by this linkage unit.This linkage unit comprises a plurality of data pin that are used for the transmitting and displaying data-signal and are provided with continuously.This display data signal is converted to low-swing difference signal in this control circuit, and outputs to this liquid crystal panel by the data pin of this linkage unit, to drive this pixel cell display frame.
A kind of liquid crystal indicator, it comprises a liquid crystal panel, an internal interface circuit and a control circuit.This liquid crystal panel comprises a plurality of pixel cells, one first source electrode driver and one second source electrode driver.These a plurality of pixel cell parts are driven by this first source electrode driver, and another part is driven by this second source electrode driver.This internal interface circuit comprises one first linkage unit and one second linkage unit.This first linkage unit comprises first data pin of a plurality of adjacent settings, and this second linkage unit comprises second data pin of a plurality of adjacent settings.This first data pin and this second data pin are respectively applied for the display data signal of this first source electrode driver of transmission and this second source electrode driver correspondence.This display data signal is converted to low-swing difference signal in this control circuit, and outputs to this first source electrode driver and this second source electrode driver respectively to drive this pixel cell by this first data pin and second data pin.
Compared with prior art, in the internal interface circuit of liquid crystal indicator of the present invention, this linkage unit is used for the adjacent or continuous setting of a plurality of data pin of transmitting and displaying data-signal, thereby effectively reduces the size of this liquid crystal indicator internal connecting elements.Usually this undersized linkage unit cost is lower, so the present invention effectively reduces the cost of this liquid crystal indicator.In addition, corresponding because this linkage unit size is less with this linkage unit, can adopt undersized printed circuit board (PCB) and data line in this internal interface circuit, the cost of this liquid crystal indicator is further reduced thus.
Description of drawings
Fig. 1 is a kind of structural representation of prior art liquid crystal indicator.
Fig. 2 is the structural representation of liquid crystal indicator first embodiment of the present invention.
Fig. 3 is the circuit diagram of linkage unit of the internal interface circuit of liquid crystal indicator shown in Figure 2.
Fig. 4 is the oscillogram of the internal interface circuit institute data signals transmitted of liquid crystal indicator shown in Figure 2.
Fig. 5 is the structural representation of liquid crystal indicator second embodiment of the present invention.
Embodiment
Seeing also Fig. 2, is the structural representation of liquid crystal indicator first embodiment of the present invention.This liquid crystal indicator 200 comprises a liquid crystal panel 210, an internal interface circuit 280 and a control circuit 290.Wherein, this internal interface circuit 280 is used to realize that the signal between this control circuit 290 and this liquid crystal panel 210 transmits.
This liquid crystal panel 210 comprises an active-matrix 250, a gate drivers 220, one first source electrode driver 230 and one second source electrode driver 240.Wherein this active-matrix 250 comprises the sweep trace X that many parallel interval are provided with
1, X
2... X
2m, many and this sweep trace X
1, X
2... X
2mVertically disposed data line Y insulate
1, Y
2... Y
2n, and a plurality of by this sweep trace X
1, X
2... X
2mWith this data line Y
1, Y
2... Y
2nSeparate the pixel cell 270 that defines and be matrix distribution.Wherein, this sweep trace X
1, X
2... X
2mBe connected to this gate drivers 220, this data line Y
1, Y
2... Y
nBe connected to this first source electrode driver 230, this data line Y
N+1, Y
N+2... Y
2nBe connected to this second source electrode driver 240.
This pixel cell 270 comprises a thin film transistor (TFT) 271, a pixel electrode 272 and a public electrode 273.To be positioned at i is listed as the capable pixel cell of j 270 and is designated as P
(i, j)(1≤i≤2m, 1≤j≤2n), then in the active-matrix 250 of this liquid crystal panel 210, be positioned at the 1st to all capable pixel cell P of n
(i, j)(1≤i≤2m, 1≤j≤n) drive, and this pixel cell P by this first source electrode driver 230
(i, j)(among the 1≤i≤2m, 1≤j≤n), the source electrode of this thin film transistor (TFT) 271 and this data line Y
j(1≤j≤n) is corresponding to be connected, its grid and drain electrode respectively with this sweep trace X
i(1≤i≤2m) are connected with these pixel electrode 272 correspondences.And be positioned at n+1 to the capable pixel cell P of 2n
(i, j)(1≤i≤2m, n+1≤j≤2n) drive, and this pixel cell P by this second source electrode driver 240
(i, j)(among the 1≤i≤2m, n+1≤j≤2n), the source electrode of this thin film transistor (TFT) 271 and this data line Y
j(n+1≤j≤2n) is corresponding to be connected, its grid and drain electrode also respectively with this sweep trace X
i(1≤i≤2m) are connected with these pixel electrode 272 correspondences.This pixel electrode 272, this public electrode 273 and be clipped in liquid crystal layer therebetween (figure do not show) and form a liquid crystal capacitance 274.
This control circuit 290 comprises time schedule controller 292.This internal interface circuit 280 comprises a linkage unit 201.This linkage unit 201 is a connector, and it is used for the vision signal by these time schedule controller 292 outputs is sent to this liquid crystal panel 210.This vision signal comprises display data signal and clock signal.Wherein, this display data signal is 6 R/G/B binary signals, and it is to adopt the low-swing difference signal form to transmit, and it comprises 6 red primaries (R) binary signal, 6 green primary (G) binary signals and 6 blue primaries (B) binary signal.These 6 red primary binary signals, these 6 green primary binary signals and this 6 blue primary binary signals comprise three differential pairs respectively, and each differential pair comprises a positive signal and a negative polarity signal respectively.With these 6 blue primary binary signals is example, and the positive-negative polarity signal of its three differential pairs can be designated as B0P, B0N, B1P, B1N, B2P and B2N respectively; These 6 red primary binary signals and these 6 green primary binary signals can correspondingly carry out mark.
See also Fig. 3, it is the circuit diagram of this linkage unit 201.This linkage unit 201 comprises 60 pins, and it is defined as pin respectively the first to the six No. ten.In the present embodiment, the distance between adjacent two pins is 0.45-0.55mm, is preferably 0.5mm.Wherein, each functions of pins is as shown in table 2 respectively.
Table 2
| Pin number | Function | Pin number | Function | Pin number | Function | | Function | |
| 1 | |
16 | |
31 | B1N-1 | 46 | R2N-2 | |
| 2 | |
17 | R0N-1 | 32 | B1P-1 | 47 | R2P-2 | |
| 3 | VDD-1 | 18 | R0P-1 | 33 | B2N-1 | 48 | G0N-2 | |
| 4 | VDD-2 | 19 | R1N-1 | 34 | B2P-1 | 49 | G0P-2 | |
| 5 | VDD-G | 20 | R1P-1 | 35 | |
50 | G1N-2 | |
| 6 | |
21 | R2N-1 | 36 | CLKN-1 | 51 | G1P-2 | |
| 7 | GND | 22 | R2P-1 | 37 | CLKP-1 | 52 | G2N-2 | |
| 8 | STP-1 | 23 | G0N-1 | 38 | GND | 53 | G2P-2 | |
| 9 | STP-2 | 24 | G0P-1 | 39 | CLKN-2 | 54 | B0N-2 | |
| 10 | CKV | 25 | G1N-1 | 40 | CLKP-2 | 55 | B0P-2 | |
| 11 | OE-G | 26 | G1P-1 | 41 | |
56 | B1N-2 | |
| 12 | CLK- |
27 | G2N-1 | 42 | R0N-2 | 57 | B1P-2 | |
| 13 | STP-G | 28 | G2P-1 | 43 | R0P-2 | 58 | B2N-2 | |
| 14 | |
29 | B0N-1 | 44 | R1N-2 | 59 | B2P-2 | |
| 15 | |
30 | B0P-1 | 45 | R1P-2 | 60 | GND |
Annotate: in the table 2, " *-1 " and " *-2 " represents corresponding with this first source electrode driver 230 and this second source electrode driver 240 respectively; " *-G " expression is corresponding with this gate drivers 220.VDD represents supply voltage, GND represents ground connection, NC represents vacant, CLK represents clock signal, OE represents the output enable signal, and STP represents initial pulse signal, and POL represents the output polarity control signal, DLP represents the data latching pulse signal, and CKV represents Kickback voltage compensation (Compensation Of Kick-back Voltage) signal.
As seen from Table 2, this linkage unit 201 comprises a plurality of first data pin (i.e. 17-34 pin) of the display data signal that is used to transmit these first source electrode driver, 230 correspondences, and the adjacent setting of these a plurality of first data pin.Particularly, these a plurality of adjacent first data pin that are provided with comprise a head end data pin and a terminal data pin, and except this head end data pin and this end data pin, adjacent two pins of arbitrary first data pin also are respectively one of this first data pin.That is to say that these a plurality of first data pin are arranged on this linkage unit 201 continuously, and do not introduce grounding pin between the first adjacent data pin and carry out electrical isolation.In addition, this linkage unit 201 also comprises a plurality of second data pin (i.e. 42-59 pin) of the display data signal that is used to transmit these second source electrode driver, 240 correspondences, and these a plurality of second data pin are similarly continuous setting, also do not introduce grounding pin between the second adjacent data pin and carry out electrical isolation.
When these liquid crystal indicator 200 work, this control circuit 290 receives this vision signal, and by its inner time schedule controller 292 this vision signal is resolved to above-mentioned display data signal and clock signal.This time schedule controller 292 further converts this display data signal to the low-swing difference signal form, and by this linkage unit 201 this display data signal is transferred to corresponding first source electrode driver 230 and second source electrode driver 240 respectively.This time schedule controller 292 is transferred to this clock signal correspondence this gate drivers 220, this first source electrode driver 230 and this second source electrode driver 240 simultaneously.
This first source electrode driver 230 receives its corresponding display data signal by the 17-32 pin of this linkage unit 201, and the 3rd, 8,10,14,15,36 and No. 37 pin by this linkage unit 201 receives its corresponding supply voltage, initial pulse signal, output polarity control signal, Kickback voltage compensating signal, data latching pulse signal, positive polarity clock signal and negative polarity clock signal respectively.This first source electrode driver 230 further converts this display data signal to corresponding display driver voltage.
This second source electrode driver 240 receives its pairing display data signal by the 42-59 pin of this linkage unit 201, and the 4th, 9,10,14,15,39 and No. 40 pin by this linkage unit 201 receives its corresponding supply voltage, initial pulse signal, output polarity control signal, Kickback voltage compensating signal, data latching pulse signal, positive polarity clock signal and negative polarity clock signal respectively.This second source electrode driver 240 equally further converts this display data signal to corresponding display driver voltage.
This gate drivers 220 receives supply voltage by No. 5 pin of this linkage unit 201, and the 11st, 12 and No. 13 pin by this linkage unit 201 receives its corresponding output enable signal, clock signal and initial pulse signal respectively.This gate drivers 220 further produces a plurality of scanning pulse signals according to above-mentioned signal, and is applied to this sweep trace X in regular turn
1, X
2... X
2mWhen this scanning pulse signal is applied to this i (bar sweep trace X of 1≤i≤2m)
iThe time, with this sweep trace X
i(1≤i≤2m) goes thin film transistor (TFT) 271 conductings to the i that is connected.This first source electrode driver 230 and this second source electrode driver 240 output to this i row pixel cell P with its inner display driver voltage correspondence that produces respectively
(i, j)(the pixel electrode 272 of 1≤j≤2n).Simultaneously, this public electrode 273 receives the common electric voltage that is sent by a common electric voltage circuit (figure does not show), thereby makes formation one electric field between this pixel electrode 272 and this public electrode 273.The liquid crystal molecule that this electric field driven is clipped between this pixel electrode 272 and this public electrode 273 rotates, and the throughput of control light is to show corresponding picture.
As can be seen from the above description, compare with the internal interface circuit 180 of above-mentioned prior art liquid crystal indicator 100, in the linkage unit 201 of the internal interface circuit 280 of this liquid crystal indicator 200, the grounding pin between the adjacent differential pair institute corresponding data pin is removed.Because this display data signal is to adopt the form of low amplitude of oscillation difference low-voltage signal to carry out the signal transmission, and the positive-negative polarity voltage of signals amplitude of oscillation of low each differential pair of amplitude of oscillation difference low-voltage signal all less (representative value is respectively ± 200mV), thereby its issuable differential mode noise in transmission course is less.Specifically, in this internal interface circuit 280, though the positive-negative polarity signal of this display data signal each differential pair in transmission course also can produce the inconsistent of certain amplitude under the electromagnetic interference (EMI) of contiguous differential pair, but because this display data signal is to convert low amplitude of oscillation difference low-voltage signal form to transmit again, therefore the inconsistent amplitude of above-mentioned electromagnetic interference (EMI) is less, does not influence the transmission of signal usually.Above analysis is verified by experiment, and is specific as follows described.
Seeing also Fig. 4, is the internal interface circuit 280 data signals transmitted actual verification results' of liquid crystal indicator 200 of the present invention oscillogram.This oscillogram is the 27th and No. 28 measured signal waveform of pin of expression, also promptly represents the signal waveform of the 3rd differential pair of these first source electrode driver, 230 pairing 6 green primary binary signals.This oscillogram is to be to record under 1280 * 1024 the Dot On/Off picture with the sweep frequency display resolution of 60Hz at this liquid crystal indicator 200 by the oscillographic difference detector of TEK TDS7404 type, and it comprises one first curve 401, one second curve 402 and one the 3rd curve 403.Wherein this first curve 401 is voltage curves of the positive signal G2P-1 of the 3rd differential pair of these 6 green primary binary signals, this second curve 402 is voltage curves of its negative polarity signal G2N-1, and the 3rd curve 403 is differential mode voltage curves of the 3rd differential pair of these 6 green primary signals.Be 424mV by the 3rd curve 403 actual these differential mode voltage values that record in the experiment.Because the differential mode voltage value of low-swing difference signal (is the difference of its positive-negative polarity voltage of signals amplitude of oscillation usually, representative value is 400mV) just can satisfy transmission requirement as long as be not less than 200mV, do not carry out electrical isolation though therefore introduce grounding pin between the 3rd pairing data pin of differential pair of these 6 green primary binary signals and the pairing data pin of other differential pairs, experimental results show that in fact its laser propagation effect can't be affected.That is to say, the positive signal G2P-1 of the 3rd differential pair of these 6 green primary binary signals and negative polarity signal G2N-1 are in transmission course, the actual value of its differential mode voltage is in allowed limits owing to being subjected to the degree that noise departs from ideal value (being above-mentioned representative value), and therefore above-mentioned noise can't impact the laser propagation effect of the 3rd differential pair of these 6 green primary binary signals.
Seeing also table 3, is the differential mode voltage value that each differential pair institute data signals transmitted records in experiment in the internal interface circuit 280 of this liquid crystal indicator 200.
Table 3
| Differential pair | The differential mode voltage value | Unit | Differential pair | The differential mode voltage value | Unit |
| R0P-1/R0N-1 | 488 | mV | R0P-2/R0N-2 | 616 | mV |
| R1P-1/R1N-1 | 504 | mV | R1P-2/R1N-2 | 568 | mV |
| R2P-1/R2N-1 | 552 | mV | R2P-2/R2N-2 | 456 | mV |
| G0P-1/G0N-1 | 504 | mV | G0P-2/G0N-2 | 456 | mV |
| G1P-1/G1N-1 | 480 | mV | G1P-2/G1N-2 | 312 | mV |
| G2P-1/G2N-1 | 424 | mV | G2P-2/G2N-2 | 432 | mV |
| B0P-1/B0N-1 | 360 | mV | B0P-2/B0N-2 | 360 | mV |
| B1P-1/B1N-1 | 552 | mV | B1P-2/B1N-2 | 520 | mV |
| B2P-1/B2N-1 | 472 | mV | B2P-2/B2N-2 | 632 | mV |
By table 3 as seen, all differential mode voltage values of the display data signal that the internal interface circuit 280 of this liquid crystal indicator 200 is transmitted are all greater than 200mV, that is to say, this internal interface circuit 280 can satisfy the transmission requirement of low-swing difference signal, and its laser propagation effect can't be affected because of removing the pairing grounding pin of adjacent differential pair.
In sum, liquid crystal indicator 200 of the present invention is within it in the linkage unit 201 of portion's interface circuit 280, be used to transmit the data pin adjacent setting respectively of this first source electrode driver 230 and these second source electrode driver, 240 pairing low-swing difference signals, the grounding pin that is used to carry out electrical isolation between every pair of data pin is removed.The experiment proved that the removal of above-mentioned grounding pin can't impact the laser propagation effect of this internal interface circuit 280.That is to say, in the internal interface circuit 180 of the transmission low-swing difference signal that the liquid crystal indicator 100 of prior art comes based on the interface circuit development of transmitting the Low Voltage Differential Signal form, adopt a grounding pin to carry out a kind of technology prejudice that electrical isolation is present industry between the pairing data pin of adjacent differential pair respectively.Liquid crystal indicator 200 of the present invention effectively overcomes above-mentioned technology prejudice, and brings following technique effect.On the one hand, because a large amount of grounding pins are removed, in the internal interface circuit 280 of this liquid crystal indicator 200, the pin of this linkage unit 201 obtains more effectively utilizing, thereby the less cost of its size is lower, thereby reduces the cost of this liquid crystal indicator 200.On the other hand, because these linkage unit 201 total areas are less, the printed circuit board (PCB) corresponding with this linkage unit 201 and the size of data line can effectively reduce equally in this internal interface circuit 280, can further reduce the cost of this internal interface circuit 280 and this liquid crystal indicator 200 thus.
In addition, liquid crystal indicator 200 of the present invention is not confined to above embodiment and describes.For example this control circuit 290 can comprise further that also a scale controller (Scaler) carries out convergent-divergent control to data-signal, and this time schedule controller 292 directly is integrated in this scale controller inside.Again for example, in this internal interface circuit 280, the linkage unit 201 of this 60 pin also can adopt the linkage unit replacement of a pair of 30 pins etc.
Seeing also Fig. 5, is the structural representation of liquid crystal indicator second embodiment of the present invention.The structural similarity of this liquid crystal indicator 500 and above-mentioned liquid crystal indicator 200, its difference is: the liquid crystal panel 510 of this liquid crystal indicator 500 only comprises one source pole driver 530.Active-matrix 550 inner all pixel cells 570 of this liquid crystal panel 510 drive by this source electrode driver 530.The internal interface circuit 580 of this liquid crystal indicator 500 comprises a linkage unit 501, and it is used for transmission of data signals and clock signal gate drivers 520 and the source electrode driver 530 to this liquid crystal panel 510.This linkage unit 501 comprises 36 pins, and each functions of pins is as shown in table 4 respectively.In the table 4, " *-S " expression is corresponding with this source electrode driver 530; " *-G " expression is corresponding with this gate drivers 520, and each pin function symbol is corresponding with linkage unit 201 each pin function of liquid crystal indicator shown in the table 2 200.
Table 4
| Pin number | Function | Pin number | Function | Pin number | Function | | Function | |
| 1 | GND | 10 | CLK-G | 19 | R2N | 28 | |
|
| 2 | NC | 11 | STP-G | 20 | R2P | 29 | B1N | |
| 3 | VDD- |
12 | DLP- |
21 | G0N | 30 | B1P | |
| 4 | VDD- |
13 | POL- |
22 | G0P | 31 | |
|
| 5 | |
14 | |
23 | G1N | 32 | |
|
| 6 | |
15 | R0N | 24 | |
33 | |
|
| 7 | STP- |
16 | R0P | 25 | G2N | 34 | CLKN- |
|
| 8 | CKV- |
17 | R1N | 26 | G2P | 35 | CLKP- |
|
| 9 | OE- |
18 | R1P | 27 | |
36 | GND |
As can be seen from Table 4, in 36 pins of the linkage unit 501 of this internal interface circuit 580, the 15-32 pin is used for the transmitting and displaying data-signal as data pin, and all adjacent setting of this 15-32 pin, thereby makes that the less cost of size of this linkage unit 501 is lower.On the other hand, in this liquid crystal indicator 500, all pixel cells 570 of this active-matrix 510 drive by this source electrode driver 530, thereby make the linkage unit 501 of this internal interface circuit 580 only need adopt 36 pins.Therefore, the cost of this liquid crystal indicator 500 can further reduce, and makes that the structure of this liquid crystal panel 510 is compact more, meets the industry trend of liquid crystal indicator microization.
Claims (10)
1. liquid crystal indicator, it comprises a liquid crystal panel, an one internal interface circuit and a control circuit, this liquid crystal panel comprises that an active-matrix and is used to drive the source electrode drive circuit of this active-matrix, this internal interface circuit comprises a linkage unit, this control circuit is connected to this source electrode driver by this linkage unit, this linkage unit comprises a plurality of data pin that are used for the transmitting and displaying data-signal, this display data signal is converted to low-swing difference signal in this control circuit, and output to this source electrode drive circuit by the data pin of this linkage unit, it is characterized in that: adjacent this linkage unit that is arranged on of these a plurality of data pin.
2. liquid crystal indicator as claimed in claim 1 is characterized in that: this display data signal is 6 R/G/B binary signals.
3. liquid crystal indicator as claimed in claim 1 is characterized in that: the distance between adjacent two data pin is between 0.45 millimeter to 0.55 millimeter.
4. liquid crystal indicator as claimed in claim 1, it is characterized in that: this active-matrix comprises a plurality of pixel cells, this source electrode drive circuit comprises one first source electrode driver and one second source electrode driver, these a plurality of pixel cell parts are driven by this first source electrode driver, and another part is driven by this second source electrode driver.
5. liquid crystal indicator as claimed in claim 4, it is characterized in that: these a plurality of data pin comprise first data pin of a plurality of adjacent settings and second data pin of a plurality of adjacent settings, and this first data pin is respectively applied for this first source electrode driver of transmission and the pairing display data signal of this second source electrode driver with this second data pin.
6. liquid crystal indicator as claimed in claim 5, it is characterized in that: these a plurality of first data pin and these a plurality of second data pin comprise a head end data pin and a terminal data pin respectively, and except that this head end data pin and this end data pin, adjacent two pins of arbitrary first data pin are respectively one of this first data pin, and adjacent two pins of arbitrary second data pin are respectively one of this second data pin.
7. liquid crystal indicator as claimed in claim 6, it is characterized in that: this linkage unit comprises 60 pins, these 60 pins are the first to the six No. ten pin that sets gradually, and wherein the 17 to the 30 No. four pin is as this first data pin.The 42 to the 50 No. nine pin is as this second data pin.
8. liquid crystal indicator as claimed in claim 1, it is characterized in that: this linkage unit comprises 36 pins, these 36 pins are the first to the 30 No. six pin that sets gradually, and wherein the 15 to the 30 No. two pin is used to transmit this display data signal.
9. liquid crystal indicator, it comprises a liquid crystal panel, an one internal interface circuit and a control circuit, this liquid crystal panel comprises a plurality of pixel cells, this internal interface circuit comprises a linkage unit, this control circuit is connected to this liquid crystal panel by this linkage unit, this linkage unit comprises a plurality of data pin that are used for the transmitting and displaying data-signal, this display data signal is converted to low-swing difference signal in this control circuit, and output to this liquid crystal panel by the data pin of this linkage unit, it is characterized in that: these a plurality of data pin are arranged on this linkage unit continuously.
10. liquid crystal indicator, it comprises: a liquid crystal panel, an one internal interface circuit and a control circuit, this liquid crystal panel comprises a plurality of pixel cells, one first source electrode driver and one second source electrode driver, and these a plurality of pixel cell parts are driven by this first source electrode driver, another part is driven by this second source electrode driver, this internal interface circuit comprises one first linkage unit and one second linkage unit, this first linkage unit comprises a plurality of first data pin, this second linkage unit comprises a plurality of second data pin, and this first data pin and this second data pin are respectively applied for the display data signal of this first source electrode driver of transmission and this second source electrode driver correspondence; This display data signal is converted to low-swing difference signal in this control circuit, and output to this first source electrode driver and this second source electrode driver respectively to drive this pixel cell by this first data pin and second data pin, it is characterized in that: adjacent respectively this first linkage unit and this second linkage unit of being arranged on of this first data pin with this second data pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100657982A CN101527123B (en) | 2008-03-07 | 2008-03-07 | Liquid crystal display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100657982A CN101527123B (en) | 2008-03-07 | 2008-03-07 | Liquid crystal display device |
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| CN101527123A true CN101527123A (en) | 2009-09-09 |
| CN101527123B CN101527123B (en) | 2011-12-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2008100657982A Expired - Fee Related CN101527123B (en) | 2008-03-07 | 2008-03-07 | Liquid crystal display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105575346A (en) * | 2014-10-13 | 2016-05-11 | 群创光电股份有限公司 | Display panel and automatic testing method for display panel |
| CN115394196A (en) * | 2022-08-29 | 2022-11-25 | Tcl华星光电技术有限公司 | Display module and electronic terminal |
| CN116564246A (en) * | 2023-07-10 | 2023-08-08 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4809590B2 (en) * | 2004-03-31 | 2011-11-09 | エーユー オプトロニクス コーポレイション | Electronic equipment |
| TWI292569B (en) * | 2005-03-11 | 2008-01-11 | Himax Tech Ltd | Chip-on-glass liquid crystal display and transmission method thereof |
| TWI291152B (en) * | 2005-07-05 | 2007-12-11 | Quanta Comp Inc | Interface unit and interface transmission method |
| US7705841B2 (en) * | 2006-01-20 | 2010-04-27 | Novatek Microelectronics Corp. | Display system and method for embeddedly transmitting data signals, control signals, clock signals and setting signals |
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2008
- 2008-03-07 CN CN2008100657982A patent/CN101527123B/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105575346A (en) * | 2014-10-13 | 2016-05-11 | 群创光电股份有限公司 | Display panel and automatic testing method for display panel |
| CN105575346B (en) * | 2014-10-13 | 2018-08-14 | 群创光电股份有限公司 | Display panel and display panel automated detection method |
| CN115394196A (en) * | 2022-08-29 | 2022-11-25 | Tcl华星光电技术有限公司 | Display module and electronic terminal |
| CN115394196B (en) * | 2022-08-29 | 2023-12-29 | Tcl华星光电技术有限公司 | Display module and electronic terminal |
| CN116564246A (en) * | 2023-07-10 | 2023-08-08 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN116564246B (en) * | 2023-07-10 | 2023-10-31 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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| Publication number | Publication date |
|---|---|
| CN101527123B (en) | 2011-12-14 |
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