CN116564246B - Display panel and display device - Google Patents
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- CN116564246B CN116564246B CN202310836564.8A CN202310836564A CN116564246B CN 116564246 B CN116564246 B CN 116564246B CN 202310836564 A CN202310836564 A CN 202310836564A CN 116564246 B CN116564246 B CN 116564246B
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The application discloses a display panel and a display device, wherein the display panel comprises a plurality of sub-pixels, data driving chips and grid driving chips which are distributed in an array, the plurality of sub-pixels comprise a plurality of row pixel blocks, each data output pin is correspondingly connected with one row of sub-pixels in each column pixel block through a data line, the connection mode of the data line is changed, and the number of the data output pins can be reduced; and each grid output pin is correspondingly connected with one row of sub-pixels in each row of pixel block through a grid line, and each grid control pin is used for enabling charging of one column of pixel block, so that the driving mode of the grid driving chip is changed, progressive scanning of more rows can be realized by the same number of pins, and compared with the resolution of (M1+M2) x N, the resolution of M1 x M2 x N can be realized in the prior art, the resolution of M1 x M2 x N can be realized, and not only can higher resolution be realized by the same number of pins, but also the frame space and the manufacturing cost can not be increased.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
In a display panel, a data line is typically connected to a column of sub-pixels, and a scan line is typically connected to a row of sub-pixels, so as to implement progressive scanning.
Each data line needs to be connected with one data output pin of the data driving chip to transmit data signals to the corresponding sub-pixel, and each scanning line needs to be connected with one grid output pin of the grid driving chip to transmit scanning signals. And writing the data signals into the corresponding sub-pixels through the control of the scanning signals in the progressive scanning process so as to realize the expected display.
However, as resolution increases, such driving schemes require a greater number of data output pins and/or gate output pins; in the case of exceeding the number of output pins of the chip design, it is also necessary to increase the number of chips. This not only increases the frame space of the display panel, but also increases the manufacturing cost of the display panel.
Disclosure of Invention
The application provides a display panel and a display device, which are used for relieving the technical problem that more output pins are required for high resolution.
In a first aspect, the present application provides a display panel, the display panel including a plurality of sub-pixels, a data driving chip and a gate driving chip distributed in an array, the plurality of sub-pixels including a plurality of row pixel blocks, the plurality of rows of sub-pixels in a row pixel block being divided into at least one column pixel block, the column pixel block including a plurality of columns of sub-pixels; the data driving chip comprises N data output pins, each data output pin is correspondingly connected with a row of sub-pixels in each row of pixel blocks through a data line, and N is a positive integer; the grid driving chip comprises M1 grid control pins and M2 grid output pins, each grid output pin is correspondingly connected with one row of sub-pixels in each row of pixel blocks through a grid line, each grid control pin is used for enabling charging of one column of pixel blocks, and M1 and M2 are integers which are larger than or equal to 2.
In some embodiments, each gate output pin outputs a gate driving signal, and the M2 gate output pins output M2 gate driving signals with sequentially varying phases; each grid control pin outputs a grid control signal, and M1 grid control pins output M1 grid control signals with phases changed in sequence; and the grid control signal is used for controlling M2 pulses with sequentially changed output phases of M2 grid drive signals connected with the pixel blocks in the same column.
In some embodiments, the plurality of sub-pixels includes a first row of pixel blocks including a first column of pixel blocks and a second row of pixel blocks including a second column of pixel blocks; each data output pin is connected with the same column of sub-pixels in the first column of pixel blocks and the second column of pixel blocks; each grid output pin is connected with an X-th row of sub-pixels in the first row of pixel blocks and an X-th row of sub-pixels in the second row of pixel blocks; the M1 gate control pins include a first gate control pin for enabling charging of the first column of pixel blocks and a second gate control pin for enabling charging of the second column of pixel blocks.
In some embodiments, the M2 gate output pins output M2 gate driving signals with sequentially varying phases, the first gate control pin outputs a first gate control signal, and the second gate control pin outputs a second gate control signal; under the condition that a first grid control signal generates a starting edge of a pulse, M2 grid drive signals sequentially output corresponding pulses so as to charge each row of sub-pixels in a first column of pixel blocks row by row; in the case where the second gate control signal has a start edge of a pulse, the M2 gate drive signals sequentially output corresponding pulses to charge each row of sub-pixels in the second column pixel block row by row.
In some embodiments, the plurality of sub-pixels includes a first row of pixel blocks and a second row of pixel blocks, the first row of pixel blocks includes a first column of pixel blocks and a third column of pixel blocks, the second row of pixel blocks includes a second column of pixel blocks and a fourth column of pixel blocks, the first column of pixel blocks and the second column of pixel blocks are in a same column, and the third column of pixel blocks and the fourth column of pixel blocks are in a same column; each data output pin is connected with the same column of sub-pixels in the first column of pixel blocks and the second column of pixel blocks, the same column of sub-pixels in the third column of pixel blocks and the same column of sub-pixels in the fourth column of pixel blocks; each grid output pin is connected with an X-th row of sub-pixels in the first row of pixel blocks and an X-th row of sub-pixels in the second row of pixel blocks; the M1 gate control pins include a first gate control pin for enabling charging of the first column pixel block, a second gate control pin for enabling charging of the second column pixel block, a third gate control pin for enabling charging of the third column pixel block, and a fourth gate control pin for enabling charging of the fourth column pixel block.
In some embodiments, the M2 gate output pins output M2 gate driving signals with sequentially varying phases, the first gate control pin outputs a first gate control signal, the second gate control pin outputs a second gate control signal, the third gate control pin outputs a third gate control signal, and the fourth gate control pin outputs a fourth gate control signal; under the condition that a first grid control signal generates a starting edge of a pulse, M2 grid drive signals sequentially output corresponding pulses so as to charge each row of sub-pixels in a first column of pixel blocks row by row; under the condition that the third grid control signal generates a starting edge of a pulse, M2 grid drive signals sequentially output corresponding pulses so as to charge each row of sub-pixels in the third column of pixel blocks row by row; under the condition that the second grid control signal generates a starting edge of a pulse, M2 grid drive signals sequentially output corresponding pulses so as to charge each row of sub-pixels in the second column of pixel blocks row by row; in the case where the start edge of the pulse occurs in the fourth gate control signal, the M2 gate driving signals sequentially output the corresponding pulses to charge each row of the sub-pixels in the fourth column pixel block row by row.
In some embodiments, the plurality of sub-pixels further includes a third row of pixel blocks, the third row of pixel blocks including a fifth column of pixel blocks and a sixth column of pixel blocks, the fifth column of pixel blocks being in a same column as the first column of pixel blocks and the second column of pixel blocks, the sixth column of pixel blocks being in a same column as the third column of pixel blocks and the fourth column of pixel blocks; each data output pin is connected with the same column of sub-pixels in the first column of pixel blocks, the second column of pixel blocks and the fifth column of pixel blocks and connected with the same column of sub-pixels in the third column of pixel blocks, the fourth column of pixel blocks and the sixth column of pixel blocks; each grid output pin is connected with an X-th row of sub-pixels in the first row of pixel blocks, an X-th row of sub-pixels in the second row of pixel blocks and an X-th row of sub-pixels in the third row of pixel blocks; the M1 gate control pins further include a fifth gate control pin for enabling charging of the fifth column of pixel blocks and a sixth gate control pin for enabling charging of the sixth column of pixel blocks.
In some embodiments, the fifth gate control pin outputs a fifth gate control signal, and the sixth gate control pin outputs a sixth gate control signal; after the charging of each row of sub-pixels in the fourth column of pixel blocks is completed, under the condition that a starting edge of a pulse appears in the fifth gate control signal, M2 gate drive signals sequentially output corresponding pulses so as to charge each row of sub-pixels in the fifth column of pixel blocks row by row; in the case where the start edge of the pulse occurs in the sixth gate control signal, the M2 gate driving signals sequentially output the corresponding pulses to charge each row of the sub-pixels in the sixth column pixel block row by row.
In some of these embodiments, M1 is greater than the number of pixel blocks in a row.
In a second aspect, the present application provides a display device, which includes a display panel in at least one embodiment, where the display panel is a liquid crystal display panel.
According to the display panel and the display device provided by the application, each data output pin is correspondingly connected with one row of sub-pixels in each row of pixel blocks through the data line, so that the connection mode of the data line is changed, and the number of the data output pins can be reduced; and each grid output pin is correspondingly connected with one row of sub-pixels in each row of pixel block through a grid line, and each grid control pin is used for enabling charging of one column of pixel block, so that the driving mode of the grid driving chip is changed, progressive scanning of more rows can be realized by the same number of pins, and compared with the resolution of (M1+M2) x N, the resolution of M1 x M2 x N can be realized in the prior art, the resolution of M1 x M2 x N can be realized, and not only can higher resolution be realized by the same number of pins, but also the frame space and the manufacturing cost can not be increased.
Drawings
The technical solution and other advantageous effects of the present application will be made apparent by the following detailed description of the specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display panel in the related art.
Fig. 2 is a schematic circuit diagram of the sub-pixel shown in fig. 1.
Fig. 3 is a schematic diagram of a first structure of a display panel according to an embodiment of the application.
FIG. 4 is a timing diagram of the display panel shown in FIG. 3.
Fig. 5 is a schematic diagram of a second structure of a display panel according to an embodiment of the application.
FIG. 6 is a timing diagram of the display panel shown in FIG. 5.
Fig. 7 is a schematic diagram of a third structure of a display panel according to an embodiment of the application.
FIG. 8 is a timing diagram of the display panel shown in FIG. 7.
Fig. 9 is a schematic diagram of a fourth structure of a display panel according to an embodiment of the application.
Fig. 10 is a timing diagram of the display panel shown in fig. 9.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated, whereby a feature defining "first," "second," or the like, may explicitly or implicitly include one or more of such features, and in the description of the present application, "a plurality" means two or more, unless otherwise specifically limited.
Fig. 1 is a schematic structural diagram of a related art display panel, which includes N data lines, M gate lines, and a plurality of sub-pixels P1 distributed in an array.
In the explanation of N equal to 128 and M equal to 48, M, N may be other positive integers. Where m=m1+m2.
Each data line is connected to one column of sub-pixels P1, for example, a first data line DL1 is connected to a first column of sub-pixels P1 from left to right, and a second data line DL2 is connected to a second column of sub-pixels P1 from left to right.
Each gate line is connected to one row of sub-pixels P1, for example, a first gate line GL1 is connected to the first row of sub-pixels P1 from top to bottom, a second gate line GL2 is connected to the second row of sub-pixels P1 from top to bottom.
Each data line needs to be connected to one data output pin DOP of the data driving chip 100 to transmit a data signal to a corresponding sub-pixel P1, and each gate line needs to be connected to one gate output pin GOP of the gate driving chip 200 to transmit a corresponding gate driving signal. And writes the data signal to the corresponding sub-pixel P1 through the control of the gate driving signal in the progressive scanning process to realize the intended display.
However, as resolution increases, such driving schemes require a greater number of data out pins DOP and/or gate out pins GOP; in the case of exceeding the number of output pins of the chip design, it is also necessary to increase the number of chips. This not only increases the frame space of the display panel, but also increases the manufacturing cost of the display panel.
Fig. 2 is a schematic circuit diagram of the sub-pixel P1 shown in fig. 1. The sub-pixel P1 includes a transistor T1, a liquid crystal capacitor, and a storage capacitor, wherein one of a source electrode and a drain electrode of the transistor T1 is connected to the data line DL, a gate electrode of the transistor T1 is connected to the gate line GL, the other of the source electrode and the drain electrode of the transistor T1 is connected to one end of the liquid crystal capacitor Clc and one end of the storage capacitor Cst, the other end of the liquid crystal capacitor Clc is connected to a first common voltage end CFCOM of the color film substrate, and the other end of the storage capacitor Cst is connected to a second common voltage end ACOM of the array substrate.
In view of the above-mentioned problem that the high resolution requires more output pins, the present embodiment provides a display panel, as shown in fig. 1 to 10, the display panel includes a plurality of sub-pixels P1 distributed in an array, a data driving chip 100 and a gate driving chip 200, the plurality of sub-pixels P1 includes a plurality of row pixel blocks HPB, the plurality of rows of sub-pixels P1 in the row pixel blocks HPB are divided into at least one column pixel block LPB, and the column pixel block LPB includes a plurality of columns of sub-pixels P1; the data driving chip 100 includes N data output pins DOP, each of which is correspondingly connected to a column of sub-pixels P1 in each column of pixel blocks LPB through a data line, where N is a positive integer; the gate driving chip 200 includes M1 gate control pins SOP and M2 gate output pins GOP, each gate output pin GOP is correspondingly connected to a row of sub-pixels P1 in each row of pixel blocks HPB through a gate line, each gate control pin SOP is used for enabling charging of a column of pixel blocks LPB, and M1 and M2 are integers greater than or equal to 2.
It can be understood that in the display panel provided in this embodiment, each data output pin DOP is correspondingly connected to one column of sub-pixels P1 in each column of pixel block LPB, so that a connection mode of a data line is changed, and further, the number of data output pins DOP can be reduced; and each gate output pin GOP is correspondingly connected with a row of sub-pixels P1 in each row of pixel blocks HPB through a gate line, and each gate control pin SOP is used for enabling charging of a column of pixel blocks LPB, so that the driving mode of the gate driving chip 200 is changed, progressive scanning of more rows can be realized by the same number of pins, and compared with the resolution of (m1+m2) x N in the prior art, the resolution of M1 x M2 x N can be realized, and not only can higher resolution be realized by the same number of pins, but also the frame space and the manufacturing cost are not increased.
Where the number of column pixel blocks LPB in each row pixel block HPB is Y, Y may be a positive integer of 1, 2, 3, or the like. The application can further realize the resolution of M1 x M2 x (Y x N).
The first data output pin DOP-1 is connected to all the first data lines DL1, the second data output pin DOP-2 is connected to all the second data lines DL 2.
The first gate control pin SOP-1 is connected to the first gate control line SL-1, and the third gate control pin (not shown) is connected to the third gate control line SL-3. The M1-1 th gate control pin (not shown) is connected to the M1-1 st gate control line SL-M1-1, and the M1 st gate control pin SOP-M1 is connected to the M1 st gate control line SL-M1. Wherein each gate control line SL-1 to SL-M1 is only used for illustrating the control relationship, which is not actually connected to the corresponding column pixel block LPB. Each gate control pin SOP may be an internal pin of the gate driving chip 200.
The first gate output pin GOP-1 is connected to all of the first gate drive lines GL-1, and the M2-th gate output pin GOP-M2 is connected to all of the M2-th gate drive lines GL-M2.
In one embodiment, each gate output pin GOP outputs a gate driving signal, and M2 gate output pins GOP output M2 gate driving signals with sequentially changed phases; each grid control pin SOP outputs a grid control signal, and M1 grid control pins SOP output M1 grid control signals with the phase changing in sequence; a gate control signal is used to control M2 pulses whose output phases are sequentially changed by M2 gate driving signals connected to the same column of pixel blocks LPB.
The first gate output pin GOP-1 outputs the first gate driving signal GLS-1, and the M2 gate output pin GOP-M2 outputs the M2 gate driving signal GLS-M2. The first gate control pin SOP-1 may output the first gate control signal SLS-1 inside the gate driving chip 200, the third gate control pin may output the third gate control signal SLS-3 inside the gate driving chip 200, the M1-1 th gate control pin may output the M1-1 th gate control signal SLS-M1-1 inside the gate driving chip 200, and the M1 st gate control pin SOP-M1 may output the M1 th gate control signal SLS-M1 inside the gate driving chip 200.
As shown in fig. 3 and 4, first, when the pulse of the first gate control signal SLS-1 arrives, the pulses of the first gate drive signals GLS-1 to M2-th gate drive signals GLS-M2 are driven into the first row sub-pixels P1 to M2-th row sub-pixels P1 in the first column pixel block LPB1 row by row to realize the progressive scanning or charging of the first column pixel block LPB 1; then, in the case where the pulse of the third gate control signal SLS-3 arrives, the pulse of the first gate drive signal GLS-1 to the M2 th gate drive signal GLS-M2 is driven into the first row subpixel P1 to the M2 nd row subpixel P1 in the third column pixel block LPB3 row by row to achieve progressive scanning or charging of the third column pixel block LPB 3; then, in the case that the pulse of the M1 th gate control signal SLS-M1 arrives, the pulses of the first gate driving signals GLS-1 to M2 nd gate driving signals GLS-M2 are driven into the first row sub-pixels P1 to M2 nd row sub-pixels P1 in the M1 st column pixel block LPBM1 row by row to realize the progressive scanning or charging of the M1 st column pixel block LPBM1, so that the progressive scanning or charging of the entire display panel is completed.
In one embodiment, as shown in fig. 3 and 5, the plurality of sub-pixels P1 includes a first row of pixel blocks HPB1 and a second row of pixel blocks HPB2, the first row of pixel blocks HPB1 includes a first column of pixel blocks LPB1, and the second row of pixel blocks HPB2 includes a second column of pixel blocks LPB2; each data output pin DOP is connected with the same column of sub-pixels P1 in the first column of pixel blocks LPB1 and the second column of pixel blocks LPB2; each grid output pin GOP is connected with the X-th row of sub-pixels P1 in the first row of pixel blocks HPB1 and the X-th row of sub-pixels P1 in the second row of pixel blocks HPB 2; the M1 gate control pins SOP include a first gate control pin SOP-1 for enabling charging of the first column of pixel blocks LPB1 and a second gate control pin for enabling charging of the second column of pixel blocks LPB 2.
In the case where the row pixel block HPB has only one column pixel block LPB, the row pixel block HPB is substantially the same as the column pixel block LPB.
In one embodiment, M2 gate output pins GOP output M2 gate driving signals with sequentially changed phases, a first gate control pin SOP-1 outputs a first gate control signal SLS-1, and a second gate control pin outputs a second gate control signal SLS-2; in the case where the first gate control signal SLS-1 has a start edge of a pulse, the M2 gate driving signals sequentially output corresponding pulses to charge each row of the sub-pixels P1 in the first column pixel block LPB1 row by row; in the case where the second gate control signal SLS-2 has a start edge of a pulse, the M2 gate driving signals sequentially output corresponding pulses to charge each row of the sub-pixels P1 in the second column pixel block LPB2 row by row.
As shown in fig. 5 and 6, first, when the pulse of the first gate control signal SLS-1 arrives, the pulses of the first gate drive signals GLS-1 to M2 gate drive signals GLS-M2 are driven into the first row sub-pixels P1 to M2 row sub-pixels P1 in the first column pixel block LPB1 row by row to realize the progressive scanning or charging of the first column pixel block LPB 1; then, when the pulse of the second gate control signal SLS-2 arrives, the pulses of the first gate drive signals GLS-1 to M2-th gate drive signals GLS-M2 are driven into the first row sub-pixels P1 to M2-th row sub-pixels P1 in the second column pixel block LPB2 row by row to realize the progressive scanning or charging of the second column pixel block LPB2, so far, the progressive scanning or charging of the whole display panel is completed.
In one embodiment, as shown in fig. 3 and 7, the plurality of sub-pixels P1 includes a first row pixel block HPB1 and a second row pixel block HPB2, the first row pixel block HPB1 includes a first column pixel block LPB1 and a third column pixel block LPB3, the second row pixel block HPB2 includes a second column pixel block LPB2 and a fourth column pixel block LPB4, the first column pixel block LPB1 and the second column pixel block LPB2 are located in the same column, and the third column pixel block LPB3 and the fourth column pixel block LPB4 are located in the same column; each data output pin DOP is connected to the same column of sub-pixels P1 in the first column of pixel block LPB1 and the second column of pixel block LPB2, the same column of sub-pixels P1 in the third column of pixel block LPB3 and the fourth column of pixel block LPB 4; each grid output pin GOP is connected with the X-th row of sub-pixels P1 in the first row of pixel blocks HPB1 and the X-th row of sub-pixels P1 in the second row of pixel blocks HPB 2; the M1 gate control pins SOP include a first gate control pin SOP-1 for enabling charging of the first column pixel block LPB1, a second gate control pin for enabling charging of the second column pixel block LPB2, a third gate control pin for enabling charging of the third column pixel block LPB3, a third gate control pin for enabling charging of the fourth column pixel block LPB4, and a fourth gate control pin.
Note that the X-th row of subpixels P1 are X rows of subpixels P1 from left to right in the corresponding row of pixel blocks HPB.
In one embodiment, M2 gate output pins GOP output M2 gate driving signals with sequentially changed phases, a first gate control pin SOP-1 outputs a first gate control signal SLS-1, a second gate control pin outputs a second gate control signal SLS-2, a third gate control pin outputs a third gate control signal SLS-3, and a fourth gate control pin outputs a fourth gate control signal SLS-4; in the case where the first gate control signal SLS-1 has a start edge of a pulse, the M2 gate driving signals sequentially output corresponding pulses to charge each row of the sub-pixels P1 in the first column pixel block LPB1 row by row; in the case that the third gate control signal SLS-3 has a start edge of a pulse, the M2 gate driving signals sequentially output corresponding pulses to charge each row of the sub-pixels P1 in the third column pixel block LPB3 row by row; in the case where the second gate control signal SLS-2 has a start edge of a pulse, the M2 gate driving signals sequentially output corresponding pulses to charge each row of the sub-pixels P1 in the second column pixel block LPB2 row by row; in the case where the start edge of the pulse occurs in the fourth gate control signal SLS-4, the M2 gate driving signals sequentially output the corresponding pulses to charge each row of the sub-pixels P1 in the fourth column pixel block LPB4 row by row.
As shown in fig. 7 and 8, first, when the pulse of the first gate control signal SLS-1 arrives, the pulses of the first gate drive signals GLS-1 to M2 gate drive signals GLS-M2 are driven into the first row sub-pixels P1 to M2 row sub-pixels P1 in the first column pixel block LPB1 row by row to realize the progressive scanning or charging of the first column pixel block LPB 1; then, in the case that the pulse of the third gate control signal SLS-3 arrives, the pulse of the first gate drive signal GLS-1 to the M2 th gate drive signal GLS-M2 is driven into the first row sub-pixel P1 to the M2 nd row sub-pixel P1 in the third column pixel block LPB3 row by row to realize the progressive scanning or charging of the third column pixel block LPB3, and then, in the case that the pulse of the second gate control signal SLS-2 arrives, the pulse of the first gate drive signal GLS-1 to the M2 th gate drive signal GLS-M2 is driven into the first row sub-pixel P1 to the M2 nd row sub-pixel P1 in the second column pixel block LPB2 row by row to realize the progressive scanning or charging of the second column pixel block LPB2; then, when the pulse of the fourth gate control signal SLS-4 arrives, the pulses of the first gate driving signal GLS-1 to the M2 th gate driving signal GLS-M2 are driven into the first row sub-pixel P1 to the M2 nd row sub-pixel P1 in the fourth column pixel block LPB4 row by row to realize the progressive scanning or charging of the fourth column pixel block LPB4, so far, the progressive scanning or charging of the entire display panel is completed.
In one embodiment, as shown in fig. 3 and 9, the plurality of sub-pixels P1 further includes a third row of pixel blocks HPB3, the third row of pixel blocks HPB3 includes a fifth column of pixel blocks LPB5 and a sixth column of pixel blocks LPB6, the fifth column of pixel blocks LPB5 is located in the same column as the first column of pixel blocks LPB1 and the second column of pixel blocks LPB2, and the sixth column of pixel blocks LPB6 is located in the same column as the third column of pixel blocks LPB3 and the fourth column of pixel blocks LPB 4; each data output pin DOP is connected to the same column of sub-pixels P1 in the first column of pixel block LPB1, the second column of pixel block LPB2, and the fifth column of pixel block LPB5, and to the same column of sub-pixels P1 in the third column of pixel block LPB3, the fourth column of pixel block LPB4, and the sixth column of pixel block LPB 6; each gate output pin GOP is connected to the X-th row sub-pixel P1 in the first row pixel block HPB1, the X-th row sub-pixel P1 in the second row pixel block HPB2, and the X-th row sub-pixel P1 in the third row pixel block HPB 3; the M1 gate control pins SOP further include a fifth gate control pin for enabling charging of the fifth column pixel block LPB5 and a sixth gate control pin for enabling charging of the sixth column pixel block LPB 6.
It should be noted that, as the number of the row pixel blocks HPB and/or the column pixel blocks LPB increases, the resolution of the display panel increases.
In one embodiment, the fifth gate control pin outputs a fifth gate control signal, and the sixth gate control pin outputs a sixth gate control signal; after the charging of each row of the sub-pixels P1 in the fourth column pixel block LPB4 is completed, in the case that a start edge of a pulse occurs in the fifth gate control signal, the M2 gate drive signals sequentially output corresponding pulses to charge each row of the sub-pixels P1 in the fifth column pixel block LPB5 row by row; in the case where the start edge of the pulse occurs in the sixth gate control signal, the M2 gate drive signals sequentially output the corresponding pulses to charge each row of the sub-pixels P1 in the sixth column pixel block LPB6 row by row.
As shown in fig. 9 and 10, when the pulse of the first gate control signal SLS-1 arrives, the pulses of the first gate drive signals GLS-1 to M2 gate drive signals GLS-M2 are driven into the first row sub-pixels P1 to M2 row sub-pixels P1 in the first column pixel block LPB1 row by row to realize the progressive scanning or charging of the first column pixel block LPB 1; then, in the case that the pulse of the third gate control signal SLS-3 arrives, the pulse of the first gate drive signal GLS-1 to the M2 th gate drive signal GLS-M2 is driven into the first row sub-pixel P1 to the M2 nd row sub-pixel P1 in the third column pixel block LPB3 row by row to realize the progressive scanning or charging of the third column pixel block LPB3, and then, in the case that the pulse of the second gate control signal SLS-2 arrives, the pulse of the first gate drive signal GLS-1 to the M2 th gate drive signal GLS-M2 is driven into the first row sub-pixel P1 to the M2 nd row sub-pixel P1 in the second column pixel block LPB2 row by row to realize the progressive scanning or charging of the second column pixel block LPB2; then, in the case that the pulse of the fourth gate control signal SLS-4 arrives, the pulses of the first to M2 th gate driving signals GLS-1 to GLS-M2 are driven into the first to M2 nd row sub-pixels P1 to P1 in the fourth column pixel block LPB4 row by row to realize the progressive scanning or charging of the fourth column pixel block LPB 4; then, in the case that the pulse of the fifth gate control signal SLS-5 arrives, the pulses of the first to M2 th gate driving signals GLS-1 to GLS-M2 are driven into the first to M2 nd row sub-pixels P1 to P1 in the fifth column pixel block LPB5 row by row to realize the progressive scanning or charging of the fifth column pixel block LPB 5; then, in the case that the pulse of the sixth gate control signal SLS-6 arrives, the pulse of the first to M2 th gate driving signals GLS-1 to GLS-M2 is driven into the first to M2 nd row sub-pixels P1 to P1 in the sixth column pixel block LPB6 row by row to realize the progressive scanning or charging of the sixth column pixel block LPB 6. Thus, the progressive scanning or charging of the whole display panel is completed.
In one embodiment, M1 is greater than the number of row pixel blocks HPB.
It should be noted that this embodiment is advantageous for realizing a display panel with a larger resolution.
In one embodiment, the present embodiment provides a display device including the display panel in at least one embodiment.
It can be understood that, because the display device provided in this embodiment includes the display panel in at least one embodiment, the connection manner of the data lines is changed by correspondingly connecting each data output pin DOP with one column of sub-pixels P1 in each column of pixel block LPB through the data lines, so that the number of the data output pins DOP can be reduced; and each gate output pin GOP is correspondingly connected with a row of sub-pixels P1 in each row of pixel blocks HPB through a gate line, and each gate control pin SOP is used for enabling charging of a column of pixel blocks LPB, so that the driving mode of the gate driving chip 200 is changed, progressive scanning of more rows can be realized by the same number of pins, and compared with the resolution of (m1+m2) x N in the prior art, the resolution of M1 x M2 x N can be realized, and not only can higher resolution be realized by the same number of pins, but also the frame space and the manufacturing cost are not increased.
The display panel may be, but not limited to, a liquid crystal display panel, or a self-luminous display panel, for example, an organic light emitting diode display panel, a micro light emitting diode display panel, a mini light emitting diode display panel, or a quantum dot light emitting diode display panel having a 2T 1C-type pixel circuit.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The display panel and the display device provided by the embodiments of the present application are described in detail, and specific examples are applied to illustrate the principles and embodiments of the present application, and the description of the above embodiments is only used to help understand the technical solution and core ideas of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (10)
1. A display panel, the display panel comprising:
a plurality of sub-pixels distributed in an array, wherein the plurality of sub-pixels comprise a plurality of row pixel blocks, a plurality of rows of sub-pixels in one row pixel block are divided into at least one column pixel block, and the column pixel block comprises a plurality of columns of sub-pixels;
the data driving chip comprises N data output pins, each data output pin is correspondingly connected with a column of sub-pixels in each column of pixel block through a data line, and N is an integer greater than or equal to 2;
the grid driving chip comprises M1 grid control pins and M2 grid output pins, each grid output pin is correspondingly connected with one row of sub-pixels in each row of pixel blocks through a grid line, each grid control pin is used for enabling charging of one row of pixel blocks, and M1 and M2 are integers which are larger than or equal to 2.
2. The display panel according to claim 1, wherein each of the gate output pins outputs a gate driving signal, and the M2 gate output pins output M2 gate driving signals with sequentially changed phases;
each grid control pin outputs a grid control signal, and the M1 grid control pins output M1 grid control signals with the phase changing in sequence;
and the grid control signal is used for controlling M2 grid drive signals connected with the same column pixel block to output M2 pulses with sequentially changed phases.
3. The display panel of claim 1, wherein the plurality of subpixels comprise a first row of pixel blocks and a second row of pixel blocks, the first row of pixel blocks comprising a first column of pixel blocks, the second row of pixel blocks comprising a second column of pixel blocks;
each data output pin is connected with the same column of sub-pixels in the first column of pixel blocks and the second column of pixel blocks;
each grid output pin is connected with an X-th row of sub-pixels in the first row of pixel blocks and an X-th row of sub-pixels in the second row of pixel blocks;
the M1 gate control pins include a first gate control pin for enabling charging of the first column of pixel blocks and a second gate control pin for enabling charging of the second column of pixel blocks.
4. The display panel according to claim 3, wherein the M2 gate output pins output M2 gate driving signals whose phases sequentially vary, the first gate control pin outputs a first gate control signal, and the second gate control pin outputs a second gate control signal; wherein the method comprises the steps of
Under the condition that the first grid control signal generates a starting edge of a pulse, the M2 grid drive signals sequentially output corresponding pulses so as to charge each row of sub-pixels in the first column of pixel blocks row by row;
in the case that the second gate control signal has a start edge of a pulse, the M2 gate driving signals sequentially output corresponding pulses to charge each row of sub-pixels in the second column of pixel blocks row by row.
5. The display panel of claim 1, wherein the plurality of subpixels comprise a first row of pixel blocks and a second row of pixel blocks, the first row of pixel blocks comprising a first column of pixel blocks and a third column of pixel blocks, the second row of pixel blocks comprising a second column of pixel blocks and a fourth column of pixel blocks, the first column of pixel blocks and the second column of pixel blocks being in a same column, the third column of pixel blocks and the fourth column of pixel blocks being in a same column;
each data output pin is connected with the same column of sub-pixels in the first column of pixel blocks and the second column of pixel blocks, the same column of sub-pixels in the third column of pixel blocks and the same column of sub-pixels in the fourth column of pixel blocks;
each grid output pin is connected with an X-th row of sub-pixels in the first row of pixel blocks and an X-th row of sub-pixels in the second row of pixel blocks;
the M1 gate control pins include a first gate control pin for enabling charging of the first column of pixel blocks, a second gate control pin for enabling charging of the second column of pixel blocks, a third gate control pin for enabling charging of the third column of pixel blocks, and a fourth gate control pin for enabling charging of the fourth column of pixel blocks.
6. The display panel according to claim 5, wherein the M2 gate output pins output M2 gate driving signals whose phases sequentially change, the first gate control pin outputs a first gate control signal, the second gate control pin outputs a second gate control signal, the third gate control pin outputs a third gate control signal, and the fourth gate control pin outputs a fourth gate control signal; wherein the method comprises the steps of
Under the condition that the first grid control signal generates a starting edge of a pulse, the M2 grid drive signals sequentially output corresponding pulses so as to charge each row of sub-pixels in the first column of pixel blocks row by row;
under the condition that the third gate control signal generates a starting edge of a pulse, the M2 gate driving signals sequentially output corresponding pulses so as to charge each row of sub-pixels in the third column of pixel blocks row by row;
under the condition that the second grid control signal generates a starting edge of a pulse, the M2 grid drive signals sequentially output corresponding pulses so as to charge each row of sub-pixels in the second column of pixel blocks row by row;
in the case that the fourth gate control signal has a start edge of a pulse, the M2 gate driving signals sequentially output corresponding pulses to charge each row of sub-pixels in the fourth column of pixel blocks row by row.
7. The display panel of claim 6, wherein the plurality of sub-pixels further comprises a third row of pixel blocks, the third row of pixel blocks comprising a fifth column of pixel blocks and a sixth column of pixel blocks, the fifth column of pixel blocks being in the same column as the first column of pixel blocks and the second column of pixel blocks, the sixth column of pixel blocks being in the same column as the third column of pixel blocks and the fourth column of pixel blocks;
each data output pin is connected with the same column of sub-pixels in the first column of pixel blocks, the second column of pixel blocks and the fifth column of pixel blocks and with the same column of sub-pixels in the third column of pixel blocks, the fourth column of pixel blocks and the sixth column of pixel blocks;
each gate output pin is connected with an X-th row of sub-pixels in the first row of pixel blocks, an X-th row of sub-pixels in the second row of pixel blocks, and an X-th row of sub-pixels in the third row of pixel blocks;
the M1 gate control pins further include a fifth gate control pin for enabling charging of the fifth column of pixel blocks and a sixth gate control pin for enabling charging of the sixth column of pixel blocks.
8. The display panel of claim 7, wherein the fifth gate control pin outputs a fifth gate control signal and the sixth gate control pin outputs a sixth gate control signal;
after the charging of each row of sub-pixels in the fourth column of pixel blocks is completed, under the condition that a starting edge of a pulse appears in the fifth gate control signal, the M2 gate drive signals sequentially output corresponding pulses so as to charge each row of sub-pixels in the fifth column of pixel blocks row by row; in the case that the start edge of the pulse occurs in the sixth gate control signal, the M2 gate driving signals sequentially output corresponding pulses to charge each row of sub-pixels in the sixth column pixel block row by row.
9. The display panel according to any one of claims 1-8, wherein M1 is greater than the number of pixel blocks of the row.
10. A display device comprising the display panel according to any one of claims 1 to 9, wherein the display panel is a liquid crystal display panel.
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