CN101499248B - LCD, LCD driving circuit and driving method thereof - Google Patents
LCD, LCD driving circuit and driving method thereof Download PDFInfo
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- CN101499248B CN101499248B CN2008100660330A CN200810066033A CN101499248B CN 101499248 B CN101499248 B CN 101499248B CN 2008100660330 A CN2008100660330 A CN 2008100660330A CN 200810066033 A CN200810066033 A CN 200810066033A CN 101499248 B CN101499248 B CN 101499248B
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Abstract
The invention relates to a liquid crystal display drive circuit, which comprises a data drive circuit. The data drive circuit includes a digital register, a counter and a comparator. The digital register is used to sequentially receive signals transmitted from outside and representing gray level and output the signals once. The counter is used to output a counting signal. The comparator receives a plurality of signals representing gray level as well as the counting signal and outputs a plurality of pulse signals with certain duty ratio to each data wire according to the signals representing the gray level and the counting signal. And the display of all gray levels is realized in virtue of the duty ratio of the pulse signals. The liquid crystal display drive circuit has smaller area, lower cost and lower heating value.
Description
Technical field
The invention relates to a kind of LCD, liquid crystal display drive circuit and driving method thereof.
Background technology
Because advantages such as the display panels tool is light, thin, power consumption is little are widely used in modernized information equipments such as TV, notebook computer, mobile phone, personal digital assistant.At present, the application of display panels on market is more and more important.
Seeing also Fig. 1, is a kind of synoptic diagram of prior art liquid crystal display drive circuit.This liquid crystal display drive circuit 10 comprises time schedule controller 11, scan driving circuit 12, a data drive circuit 13, many sweep traces that are parallel to each other 14 and many data lines 15 that intersect vertically with these sweep trace 14 insulation.This scan drive circuit 12 is used to drive this sweep trace 14.
This data drive circuit 13 is used to drive this data line 15.
This time schedule controller 11 is used to receive that (Low Voltage Differential Signaling, LVDS), and output represents the binary signal of GTG and clock signal to this data drive circuit 13 by the Low Voltage Differential Signal of external circuit transmission.
This data drive circuit 13 comprises a shift register (Shift Register) 110, one digital register (Data Register) 120, one latch (Latch) 130, a resistance string line number/weighted-voltage D/A converter (Digital-to-Analog Converter, DAC) 140 and one impact damper 150.This shift register 110 comprises a plurality of shifting deposit units 111, and these a plurality of shifting deposit units 111 are used for the clock signal according to 11 outputs of this time schedule controller, export a gating signal successively to this digital register 120.
This digital register 120 comprises a plurality of digital deposit units 121, these a plurality of digital deposit units 121 are used for according to this gating signal, receive successively and be used for the binary signal (n 〉=1) that the n row show, and before receiving n+1 row binary signal, export this n row binary signal to this latch 130.This latch 130 comprises a plurality of latch units 131, each latch units 131 corresponding digital deposit unit 121, each latch units 131 is stored the binary signal of digital deposit unit 121 outputs of its correspondence respectively, exports this resistance string line number/weighted-voltage D/A converter 140 then together to.
This resistance string line number/weighted-voltage D/A converter 140 is according to the binary signal of its reception, and corresponding output gray scale voltage is to this impact damper 150, and these a plurality of gray scale voltages offer each bar data line 15 after cushioning via this impact damper 150.
Usually, this resistance string line number/weighted-voltage D/A converter 140 is to utilize a plurality of resistance (figure do not show) series connection dividing potential drop and form a plurality of gray scale voltages, and footprint area is bigger.Especially when the binary signal of representing GTG changed 8 into by 6, the number of this resistance string line number/weighted-voltage D/A converter 140 need be increased to 4, caused the increase greatly of the area and the cost of this liquid crystal display drive circuit 10.In addition, this resistance string line number/weighted-voltage D/A converter 140 is pure heat generating components, makes that the thermal value of this liquid crystal display drive circuit 10 is higher.
Summary of the invention
In order to solve the problem that prior art liquid crystal display drive circuit area is big, cost is high and thermal value is high, be necessary to provide the liquid crystal display drive circuit that a kind of area is less, cost is lower and thermal value is lower.
In order to solve the problem that prior art liquid crystal display drive circuit area is big, cost is high and thermal value is high, also be necessary to provide a kind of driving method of liquid crystal display drive circuit.
In order to solve the problem that prior art liquid crystal display drive circuit area is big, cost is high and thermal value is high, also be necessary to provide the LCD that a kind of area is less, cost is lower and thermal value is lower.
A kind of liquid crystal display drive circuit, it comprises a data drive circuit.This data drive circuit comprises a digital register, a counter, a comparer and a logical circuit and a level shifting circuit.This digital register is used for receiving successively the signal of the representative GTG of external transmission, and exports this signal together.This counter is used to export count signal.This comparer receives the signal of a plurality of representative GTGs and this count signal, and according to the signal of these a plurality of representative GTGs with the output of this count signal is a plurality of has the pulse signal of certain dutycycle to this logical circuit.This logical circuit receives these a plurality of pulse signals with certain dutycycle and carries out logical process, and exports this and a plurality ofly have the pulse signal of certain dutycycle to level shifting circuit.This level shifting circuit is used to change the pulse height of the pulse signal of this logical circuit output, and exports these a plurality of pulse signals with certain dutycycle to each bar data line, realizes the demonstration of each GTG by the dutycycle of this pulse signal.
A kind of liquid crystal display drive circuit, it comprises a data drive circuit.This data drive circuit comprises a comparer and a logical circuit and a signal input end, and this comparer comprises a plurality of comparing units, and each comparing unit comprises a first input end, one second input end and an output terminal.These a plurality of first input ends receive the signal of a plurality of representative GTGs, and these a plurality of second input ends all receive a signal that is linear change in time, and a plurality of output terminals outputs are a plurality of has the pulse signal of certain dutycycle to this logical circuit for these.This signal input end outputs control signals to this logical circuit.This logical circuit receives these a plurality of pulse signal and these control signals with certain dutycycle and carries out logical process, and export these a plurality of pulse signals to each bar data line with certain dutycycle, realize the demonstration of each GTG by the dutycycle of this pulse signal.
A kind of driving method of liquid crystal display drive circuit, it comprises the steps: that a. receives the signal of the representative GTG of external transmission successively, and exports this signal together; B. simultaneously, provide a count signal; C. the relatively signal of these a plurality of representative GTGs and this count signal, export a plurality of pulse signals with certain dutycycle, d. will these a plurality of pulse amplitudes be adjusted into a predetermined high level and and be scheduled to low level voltage difference and export each bar data line to, realize the demonstration of each GTG by the dutycycle of this pulse signal with certain dutycycle.
A kind of driving method of liquid crystal display drive circuit, its signal and one that comprises the steps: that many comparing units of a. receive a plurality of representative GTGs respectively is the signal of linear change in time; B. export a plurality of pulse signals with certain dutycycle, c. will these a plurality of pulse amplitudes be adjusted into a predetermined high level and and be scheduled to low level voltage difference and export each bar data line to, realize the demonstration of each GTG by the dutycycle of this pulse signal with certain dutycycle.
A kind of LCD, it comprises that a liquid crystal display drive circuit and an operating voltage provide end.This operating voltage provides end to be used to this liquid crystal display drive circuit that operating voltage is provided.This liquid crystal display drive circuit comprises a data drive circuit, and this data drive circuit comprises a digital register, a counter, a comparer and a logical circuit and a level shifting circuit.This digital register is used for receiving successively the signal of the representative GTG of external transmission, and exports this signal together.This counter is used to export count signal.This comparer receives the signal of these a plurality of representative GTGs and this count signal, and according to the signal of these a plurality of representative GTGs with the output of this count signal is a plurality of has the pulse signal of certain dutycycle to this logical circuit.This logical circuit receives these a plurality of pulse signals with certain dutycycle and carries out logical process, and exports this and a plurality ofly have the pulse signal of certain dutycycle to level shifting circuit.This level shifting circuit is used to change the pulse height of the pulse signal of this logical circuit output, and exports these a plurality of pulse signals with certain dutycycle to each bar data line, realizes the demonstration of each GTG by the dutycycle of this pulse signal.
A kind of LCD, it comprises that a liquid crystal display drive circuit and an operating voltage provide end.This operating voltage provides end to be used to this liquid crystal display drive circuit that operating voltage is provided.This liquid crystal display drive circuit comprises a data drive circuit, this data drive circuit comprises a comparer and a logical circuit and a signal input end, this comparer comprises a plurality of comparing units, and each comparing unit comprises a first input end, one second input end and an output terminal.These a plurality of first input ends receive the signal of a plurality of representative GTGs, and these a plurality of second input ends all receive a signal that is linear change in time, and a plurality of output terminals outputs are a plurality of has the pulse signal of certain dutycycle to this logical circuit for these.This signal input end outputs control signals to this logical circuit.This logical circuit receives these a plurality of pulse signal and these control signals with certain dutycycle and carries out logical process, and export these a plurality of pulse signals to each bar data line with certain dutycycle, realize the demonstration of each GTG by the dutycycle of this pulse signal.
Compared to prior art, LCD of the present invention, liquid crystal display drive circuit with and driving method be the demonstration that recently realizes each GTG by the duty that control exports the pulse signal of data line to, it is not the demonstration that realizes each GTG by the size of control gray scale voltage, therefore need not use the resistance string line number/weighted-voltage D/A converter of prior art, significantly reduce area, cost and the thermal value of this liquid crystal display drive circuit.
Description of drawings
Fig. 1 is a kind of synoptic diagram of prior art liquid crystal display drive circuit.
Fig. 2 is the synoptic diagram of liquid crystal display drive circuit first embodiment of the present invention.
Fig. 3 is the synoptic diagram of liquid crystal display drive circuit second embodiment of the present invention.
Fig. 4 is the part synoptic diagram of liquid crystal display drive circuit the 3rd embodiment of the present invention.
Fig. 5 is the corresponding relation figure of the dutycycle of the pulse signal exported of GTG and this first level conversion unit of the binary signal representative that receives of the comparer of liquid crystal display drive circuit shown in Figure 4.
Fig. 6 is the corresponding relation figure of the pixel voltage at the actual displayed GTG of the display panels that drives of driving circuit shown in Figure 4 and liquid crystal two ends.
Fig. 7 is the corresponding relation figure of exemplary 8 binary signals and 6 binary signals.
Fig. 8 is the synoptic diagram of LCD one better embodiment of the present invention.
Embodiment
Seeing also Fig. 2, is the synoptic diagram of liquid crystal display drive circuit first embodiment of the present invention.This liquid crystal display drive circuit 20 comprises time schedule controller 21, scan driving circuit 22, a data drive circuit 23, many sweep traces that are parallel to each other 24 and many data lines 25 that intersect vertically with these sweep trace 24 insulation.This scan drive circuit 22 is used to drive this sweep trace 24.This data drive circuit 23 is used to drive this data line 25.
This time schedule controller 21 is used to receive the Low Voltage Differential Signal of external circuit transmission, and output represents the binary signal of GTG and clock signal to this data drive circuit 23.
This data drive circuit 23 comprises a shift register 210, a digital register 220, a latch 230, a comparer 240, a binary counter 260, one first control end 270, one second control end 280 and an impact damper 250.
This shift register 210 comprises a plurality of shifting deposit units 211, these a plurality of shifting deposit units 211 are used for the clock signal according to 21 outputs of this time schedule controller, export one first gating signal successively to this digital register 220, also export one second gating signal successively to this latch 230.This shifting deposit unit 211 is exported this two gating signals in turn.
This first control end 270 is used to provide one the 3rd gating signal to this digital register 220 and this binary counter 260, and this second control end 280 is used to provide one the 4th gating signal to this latch 230 and this binary counter 260.These two control ends 270,280 provide the 3rd gating signal and the 4th gating signal in turn.This comparer 240 comprises a plurality of comparing units 241, and each comparing unit 241 comprises a first input end 242, one second input end 243 and an output terminal 244.
This digital register 220 comprises a plurality of digital deposit units 221, these a plurality of digital deposit units 221 are used for according to this first gating signal, receive successively and be used for the binary signal (n 〉=1) that n row pixel cell shows, and, export the first input end 242 of these a plurality of binary signals together to each comparing unit 240 according to the 3rd gating signal.
The structure of this latch 230 is identical with this digital register 220, comprise a plurality of latch units 231, these a plurality of latch units 231 are according to this second gating signal, receive the binary signal that n+1 row pixel cell shows that is used for of external transmission successively, and, export the first input end 242 of these a plurality of binary signals together to each comparing unit 241 according to the 4th gating signal.
When this binary counter 260 receives the 3rd gating signal or the 4th gating signal, begin counting, export second input end 243 of a count signal simultaneously to each comparing unit 241.Two signals that these a plurality of comparing units 241 receive according to these two input ends 242,243, export and a plurality ofly have the pulse signal of certain dutycycle to this impact damper 250, these a plurality of pulse signals offer each bar data line 25 after cushioning via this impact damper 250, offer a plurality of pixel electrodes (not indicating) via these many data lines 25 again, thereby form a pixel voltage in the two ends of a plurality of liquid crystal capacitances (not indicating).The size of this pixel voltage of controlled amount system of the dutycycle by this pulse signal, thus realize the demonstration of each GTG.
The driving method of this liquid crystal display drive circuit 20 comprises the steps: that this time schedule controller 21 of a. receives one first Low Voltage Differential Signal of external circuit transmission, clock signal is to this shifting deposit unit 211, and export one first binary signal subsequently to these a plurality of digital deposit units 221, wherein, this first Low Voltage Differential Signal is to be used for the Low Voltage Differential Signal that n (n 〉=1) row pixel cell shows, first binary signal is to be used for the binary signal that n row pixel cell shows.B. this shifting deposit unit 211 is exported one first gating signal successively to these a plurality of digital deposit units 221.C. these a plurality of digital deposit units 221 receive this first binary signal successively according to this first gating signal.D. this first control end 270 provides one the 3rd gating signal to this a plurality of digital deposit units 221 and this binary counter 260.E. these a plurality of digital deposit units 221 are exported the first input end 242 of this first binary signal to each comparing unit 240 together according to the 3rd gating signal; When this binary counter 260 receives the 3rd gating signal, begin counting, export second input end 243 of a count signal simultaneously to each comparing unit 241.F. these a plurality of comparing units 241 are according to two signals of these two input ends, 242,243 receptions, the pulse signal of exporting a plurality of certain dutycycles is to this impact damper 250, these a plurality of pulse signals offer each bar data line 25 after cushioning via this impact damper 250, offer a plurality of pixel electrodes (not indicating) via these many data lines 25 again, thereby form a pixel voltage in the two ends of a plurality of liquid crystal capacitances (not indicating).The size of this pixel voltage of controlled amount system of the dutycycle by this pulse signal, thus realize the demonstration of each GTG.
G. this time schedule controller 21 receives one second Low Voltage Differential Signal of external circuit transmission, clock signal is to this shifting deposit unit 211, and export one second binary signal subsequently to these a plurality of digital deposit units 221, wherein, this second Low Voltage Differential Signal is to be used for the Low Voltage Differential Signal that n+1 (n 〉=1) row pixel cell shows, second binary signal is to be used for the binary signal that n+1 row pixel cell shows.H. this shifting deposit unit 211 is exported one second gating signal successively to these a plurality of latch units 231.I. these a plurality of latch units 231 receive this second binary signal successively according to this second gating signal.J. this second control end 280 provides one the 4th gating signal to this a plurality of latch units 231 and this binary counter 260.K. these a plurality of latch units 231 are exported the first input end 242 of this second binary signal to each comparing unit 240 together according to the 4th gating signal; When this binary counter 260 receives the 4th gating signal, begin counting, export second input end 243 of a count signal simultaneously to each comparing unit 241.L. these a plurality of comparing units 241 are according to two signals of these two input ends, 242,243 receptions, the pulse signal of exporting a plurality of certain dutycycles is to this impact damper 250, these a plurality of pulse signals offer each bar data line 25 after cushioning via this impact damper 250, offer a plurality of pixel electrodes (not indicating) via these many data lines 25 again, thereby form a pixel voltage in the two ends of a plurality of liquid crystal capacitances (not indicating).The size of this pixel voltage of controlled amount system of the dutycycle by this pulse signal, thus realize the demonstration of each GTG.
Compared to prior art, this liquid crystal display drive circuit 20 is the demonstrations that recently realize each GTG by the duty that control is applied to the pulse signal of data line 25, it is not the demonstration that realizes each GTG by the size of control gray scale voltage, therefore need not use the resistance string line number/weighted-voltage D/A converter of prior art, significantly reduce area, cost and the thermal value of this liquid crystal display drive circuit 20.
Seeing also Fig. 3, is the synoptic diagram of liquid crystal display drive circuit second embodiment of the present invention.The difference of the liquid crystal display drive circuit 20 of this liquid crystal display drive circuit 30 and first embodiment is: the data drive circuit 33 of this liquid crystal display drive circuit 30 further comprises a logical circuit 380 and a signal input end 390.This signal input end 390 and this logical circuit 380 can carry out logical process to the pulse signal of comparer 340 outputs, as black plug processing, white plug processing etc.
This logical circuit 380 comprises a plurality of logical blocks 381, and each logical block 381 comprises one first logic input terminal 382, one second logic input terminal 383 and a logic output terminal 384.This first logic input terminal 382 is connected to the output terminal 344 of comparing unit 341, and this second logic input terminal 383 is connected to this signal input end 390, and the pulse signal of a plurality of certain dutycycles of these a plurality of logic output terminal 384 outputs is to impact damper 350.
The driving method of the driving method of this liquid crystal display drive circuit 30 and the first embodiment liquid crystal display drive circuit 20 is roughly the same, its difference is step f and step l: two signals that these a plurality of comparing units 341 receive according to two input end, export first logic input terminal 382 of the pulse signal of a plurality of certain dutycycles to this logical block 381, these signal input end 390 outputs one simultaneously control signal to second logic input terminal 383 of this logical block 381,381 pairs of these a plurality of pulse signals with certain dutycycle of this logical block carry out logical process, and then export impact damper 350 to, via offering each bar data line 35 after these impact damper 350 bufferings.
This signal input end 390 can be imported the low level that the low level of the pulse signal that a high level that equates with the high level of the pulse signal of this comparing unit 341 outputs or exports with this comparing unit 341 equates as required, promptly realizes the signal of black plug or the signal of realization white plug.This logical block 381 can be selected logical AND gate, logic sum gate etc. as required for use.This liquid crystal display drive circuit 30 further utilizes the pulse signal of a logical circuit 380 and 340 outputs of 390 pairs of comparers of a signal input end to handle, and can promote the display quality of display panels.
Seeing also Fig. 4, is the part synoptic diagram of liquid crystal display drive circuit the 3rd embodiment of the present invention.The difference of the liquid crystal display drive circuit 30 of this liquid crystal display drive circuit 40 and second embodiment is: the data drive circuit of this liquid crystal display drive circuit 40 (not label) further comprises a level shifting circuit 420.Usually, the high and low level of the pulse signal of logical block 481 outputs is respectively 3.3V, 0V.During this 3.3V driven liquid crystal molecule, liquid crystal molecule reverses slowly, can cause ghost.In addition, this direction of an electric field remains unchanged for a long time, can make liquid crystal molecule aging, and characteristic is destroyed.This level shifting circuit 420 is used to change the pulse height of the pulse signal of these a plurality of logical blocks 481 outputs, this pulse height is increased, and adopt inversion driving mode to change direction of an electric field.
This level shifting circuit 420 comprises a plurality of first level conversion units (First LevelShift) 421, one positive high level input end 431, one negative high level input end 432, one positive low level input end 433, one a negative low level input end 434 and reverse turn control circuit 410.This first level conversion unit 421 comprises a high level input end 422, a low level input end 423, a pulse signal input terminal 424 and an output terminal 425.This high and low level input end 422,423 is respectively applied for and receives predetermined high level and predetermined low level.This pulse signal input terminal 424 is connected to the logic output terminal 484 of logical block 481, receives the pulse signal with certain dutycycle of these logic output terminal 484 outputs.This first level conversion unit 421 is used for according to the predetermined high level of its high and low level input end 422,423 and predetermined low level, changes the pulse height of the pulse signal of these pulse signal input terminal 424 receptions.These output terminal 425 outputs are a plurality of to have this dutycycle, this predetermined high level and should be scheduled to low level pulse signal to impact damper (figure does not show), via offering each bar data line (figure does not show) after this buffer buffers.
This reverse turn control circuit 410 is used to control display panels when positive voltage drives, this positive high level input end 431 and this positive low level input end 433 receive positive high level PHV and positive low level PLV respectively, and input to this first level conversion unit 421, when negative voltage driving, should bear high level input end 432 and should receive negative high electric NHV and negative low level NLV respectively by negative low level input end 434, and input to this first level conversion unit 421.
This positive high level PHV, positive low level PLV can utilize the main operating voltage V of a digital adjustable resistance (figure does not show) of this liquid crystal display drive circuit 40 to a DC-DC converter (figure does not show) output
AVDD(figure do not show) dividing potential drop and providing.Should bear the main operating voltage V that high level NHV and negative low level NLV can utilize two charge pumps (figure does not show) earlier this DC-DC converter to be exported
AVDDChange into-V
AVDD, utilize again another digital trimmable resistance (figure do not show) to this-V
AVDDDividing potential drop provides.
This reverse turn control circuit 410 comprises one second level conversion unit (Second LevelShift), 401,1 the 3rd level conversion unit (Third Level Shift), 402, one not gate 403, a counter-rotating control end 404, a first transistor 405, a transistor seconds 406, one the 3rd transistor 407 and one the 4th transistor 408.
This counter-rotating control end 404 is connected to the grid (not label) of this first transistor 405 via this second level conversion unit 401.The source electrode of this first transistor 405 (not label) is connected to this positive high level input end 431, and drain electrode (not label) is connected to the high level input end 422 of this first level conversion unit 421.
This counter-rotating control end 404 also is connected to the grid (not label) of this transistor seconds 406 via this second level conversion unit 401.The source electrode of this transistor seconds 406 (not label) is connected to this positive low level input end 433, and drain electrode (not label) is connected to the low level input end 423 of this first level conversion unit 421.
This counter-rotating control end 404 also is connected to the grid (not label) of the 3rd transistor 407 in regular turn via this not gate 403 and the 3rd level conversion unit 402.The source electrode of the 3rd transistor 407 (not label) is connected to this negative high level input end 432, and drain electrode (not label) is connected to the high level input end 422 of this first level conversion unit 121.
This counter-rotating control end 404 also is connected to the grid (not label) of the 4th transistor 408 via this not gate 403 and the 3rd level conversion unit 404.The source electrode of the 4th transistor 408 (not label) is connected to this negative low level input end 434, and drain electrode (not label) is connected to the low level input end 423 of this first level conversion unit 421.
This second level conversion unit 401 and the 3rd level conversion unit 402 all are used for the 3.3V or the 0V level of 404 inputs of this counter-rotating control end are changed respectively.
The driving method of the liquid crystal display drive circuit 30 of the driving method of this liquid crystal display drive circuit 40 and second embodiment is roughly the same, its difference is step f and step l: output is a plurality of has the pulse signal of certain dutycycle to this level shifting circuit for this logical block 481, after this level shifting circuit is adjusted the pulse height of this pulse signal, offer each bar data line via this impact damper again, specific as follows: when this counter-rotating control end 404 inputs one 3.3V level, these the first transistor 405 and these transistor seconds 406 conductings, the 3rd transistor 407 and the 4th transistor 408 end, this positive high level input end 431 and this positive low level input end 433 export respectively positive high level PHV and just low level PLV to this first level conversion unit 421, this first level conversion unit 421 is converted to this positive high level PHV and this positive low level PLV respectively with the pulse height of the pulse signal of its reception, and offer each bar data line via this impact damper, this pulse signal offers a plurality of pixel electrodes (not indicating) via these many data lines again, thereby forms a pixel voltage in the two ends of a plurality of liquid crystal capacitances (not indicating).The size of this pixel voltage of controlled amount system of the dutycycle by this pulse signal, thus realize the demonstration of each GTG.
When this counter-rotating control end 404 inputs one 0V level, this the first transistor 405 and this transistor seconds 406 end, the 3rd transistor 407 and 408 conductings of the 4th transistor, should negative high level input end 432 and should negative low level input end 434 export respectively and bear high level PHV and negative low level PLV to this first level conversion unit 421, this first level conversion unit 421 is converted to this negative high level NHV and negative low level NLV respectively with the pulse height of the pulse signal of its reception, and offer each bar data line via this impact damper, this pulse signal offers a plurality of pixel electrodes via these many data lines again, thereby forms a pixel voltage in the two ends of a plurality of liquid crystal capacitances.The size of this pixel voltage of controlled amount system of the dutycycle by this pulse signal, thus realize the demonstration of each GTG.
Because this liquid crystal display drive circuit 40 further utilizes the pulse height of a plurality of pulse signals of 420 pairs of these comparers of a level shifting circuit, 440 outputs to adjust, increase pressure reduction between this high and low level, and change direction of an electric field between this high and low level, thereby adopt the display panels of this driving circuit 40 can effectively overcome ghost and the aging problem of liquid crystal molecule.
Seeing also Fig. 5, is the corresponding relation figure of the dutycycle of the pulse signal exported of pre-demonstration GTG and this first level conversion unit 421 of the binary signal representative that receives of this comparer 440.As shown in Figure 5, the dutycycle that shows GTG and this pulse signal in advance is to be the monotone increasing relation.In addition, the pixel voltage at the dutycycle of pulse signal and liquid crystal capacitance two ends also is to be the monotone increasing relation, and the therefore pre-pixel voltage at GTG and liquid crystal capacitance two ends that shows is the monotone increasing relation.
Seeing also Fig. 6, is the corresponding relation figure of the pixel voltage at the actual displayed GTG of the display panels that drives of this driving circuit 40 and liquid crystal two ends.As shown in Figure 6, the pixel voltage at actual displayed GTG and liquid crystal two ends is not to be the monotone increasing relation, therefore if adopt curve shown in Figure 5 to apply pulse signal, the actual displayed GTG of display panels is not pre-demonstration GTG, and it is incorrect so can to cause the actual displayed GTG to show.Therefore, the liquid crystal display drive circuit of four embodiment of the invention is provided below.
Four embodiment of the invention liquid crystal display drive circuit and the 3rd embodiment liquid crystal display drive circuit are roughly the same, and its key distinction is: this liquid crystal display drive circuit further comprises a question blank, and this question blank connects time schedule controller.What the 1st row of this question blank were stored is 2n (n 〉=3) position binary signal, what the 2nd row were stored is 2n+2m (n 〉=3, m 〉=1) position binary signal, this 2n position binary signal is a corresponding 22n GTG respectively, and this 2n+2m position binary signal is 22n the GTG of selecting from 0～22n+2m-1 GTG.The corresponding 2n position binary signal of each 2n+2m position binary signal, the corresponding relation curve of this 2n+2m position binary signal and this 2n position binary signal can be curve shown in Figure 6.
Seeing also Fig. 7, is the corresponding relation figure of exemplary 8 binary signals and 6 binary signals.Wherein, corresponding relation curve shown in Figure 7 is identical with corresponding relation curve shown in Figure 6.
The driving method of the driving method of this liquid crystal display drive circuit and the 3rd embodiment liquid crystal display drive circuit is roughly the same, its difference is step a and step g: this time schedule controller receives the Low Voltage Differential Signal of external transmission, this Low Voltage Differential Signal is converted to the 2n position binary signal of representing GTG, and from this question blank, find the 2n+2m position binary signal of a correspondence, offer this digital register again.
Because this liquid crystal display drive circuit adopts a question blank to inquire about the corresponding 2n+2m position binary signal of exporting with this time schedule controller of 2n position binary signal, thereby revise the dutycycle of pulse signal, and then the pixel voltage at modification liquid crystal two ends, can so that the pixel voltage at the GTG of binary signal representative and liquid crystal two ends this satisfy corresponding relation shown in Figure 6, thereby overcome the inaccurate problem of actual displayed GTG.
Seeing also Fig. 8, is the synoptic diagram of LCD one better embodiment of the present invention.This LCD 50 comprises that a 5V power supply 51, a reducing transformer 52, a DC-DC converter 53, a level produce circuit 54, a public voltage generating circuit 55 and a liquid crystal display drive circuit 56.This liquid crystal display drive circuit 56 is liquid crystal display drive circuits of the 4th embodiment.
This reducing transformer 52 comprises one first voltage input end 521 and an operating voltage output terminal 522.This first voltage input end 521 is connected to this 5V power supply 51.This operating voltage output terminal 522 is connected to time schedule controller 561, scanner driver 562 and the data driver 563 of this liquid crystal display drive circuit 56 respectively, is used to this time schedule controller 561, this scanner driver 562 and this data driver 563 that the operating voltage of 3.3V is provided.
This DC-DC converter 53 comprises one second voltage input end, 531, one main operating voltage output terminal 532, a grid electrode high-voltage output end 533 and a grid electrode low-voltage output end 534.This second voltage input end 531 is connected to this 5V power supply 51.This grid electrode high-voltage output end 533 is connected to this scanner driver 562, is used to export grid high pressure V
GHTo this scanner driver 562.This grid electrode low-voltage output end 534 is connected to this scanner driver 562, is used to export grid low pressure V
GLTo this scanner driver 562.This main operating voltage output terminal 532 is connected to this public voltage generating circuit 55 and this level produces circuit 54.This public voltage generating circuit 55 is used for this main operating voltage V
AVDDChange a common electric voltage into.
This level produces circuit 54 and comprises one first digital adjustable resistance (figure does not show), one second digital adjustable resistance (figure does not show) and two charge pumps (figure does not show).This first digital adjustable resistance is used for this main operating voltage V
AVDDChange a positive high level PHV and a positive low level PLV into.These two charge pumps are used for this main operating voltage V
AVDDChange into-V
AVDD, this second digital adjustable resistance be used for this-V
AVDDChange a negative high level NHV and a negative low level NLV into.These four level PHV, PLV, NHV, NLV offer four level input ends (figure does not show) of the data drive circuit 563 of liquid crystal display drive circuit 56 respectively.
It is described that liquid crystal display drive circuit of the present invention is not limited to above embodiment, as: the binary counter 260 of the first embodiment liquid crystal display drive circuit 20 also can be substituted by decade counter, its output decimal system count signal, utilize a converter that the binary signal of this latch 230 or 220 outputs of this digital register is converted to decadic signaling, this comparer 240 receives these two decadic signalings, also exportable pulse signal with certain dutycycle.
The first embodiment liquid crystal display drive circuit 20 also can not use this binary counter, as long as the signal that second input end 243 of this comparer 240 receives satisfy be linear change in time requirement just can, promptly the corresponding relation linear function of signal and time just can.
The 3rd embodiment liquid crystal display drive circuit 40 also can not comprise this logical circuit and this signal input end, and the pulse signal input terminal 424 of this first level conversion unit 421 is connected directly to the output terminal of comparing unit.
It is described that LCD 50 of the present invention is not limited to above embodiment, as: this LCD 50 also can adopt the liquid crystal display drive circuit of first to the 3rd embodiment or its change design.
Claims (9)
1. liquid crystal display drive circuit, it comprises a data drive circuit, this data drive circuit comprises a digital register, this digital register is used for receiving successively the signal of the representative GTG of external transmission, and export this signal together, it is characterized in that: this data drive circuit further comprises a counter, a comparer and a logical circuit and a level shifting circuit, and this counter is used to export count signal; This comparer receives signal and this count signal of a plurality of representative GTGs, and according to the signal of these a plurality of representative GTGs with the output of this count signal is a plurality of has the pulse signal of certain dutycycle to this logical circuit, this logical circuit receives these a plurality of pulse signals with certain dutycycle and carries out logical process, and export this and a plurality ofly have the pulse signal of certain dutycycle to level shifting circuit, this level shifting circuit is used to change the pulse height of the pulse signal of this logical circuit output, and export these a plurality of pulse signals to each bar data line with certain dutycycle, realize the demonstration of each GTG by the dutycycle of this pulse signal.
2. liquid crystal display drive circuit as claimed in claim 1, it is characterized in that: this level circuit of walking around comprises a plurality of first level conversion units, each first level conversion unit correspondence is connected between a logical block and the data line, this first level conversion unit comprises that one is used to import the high level input end of a predetermined high level, one is used to import a predetermined low level low level input end, one pulse signal input terminal and an output terminal, the logic output terminal of these a plurality of logical blocks is connected to this a plurality of pulse signal input terminals respectively, and exports a plurality of certain dutycycles that have via the output terminal of these a plurality of first level conversion units, should be scheduled to low level pulse signal to each bar data line with being somebody's turn to do by predetermined high level.
3. liquid crystal display drive circuit, it comprises a data drive circuit, it is characterized in that: this data drive circuit comprises a comparer and a logical circuit and a signal input end, this comparer comprises a plurality of comparing units, each comparing unit comprises a first input end, one second input end and an output terminal, these a plurality of first input ends receive the signal of a plurality of representative GTGs, these a plurality of second input ends all receive a signal that is linear change in time, output of a plurality of output terminals is a plurality of has the pulse signal of certain dutycycle to this logical circuit for these, this signal input end outputs control signals to this logical circuit, this logical circuit receives these a plurality of pulse signal and these control signals with certain dutycycle and carries out logical process, and export these a plurality of pulse signals to each bar data line with certain dutycycle, realize the demonstration of each GTG by the dutycycle of this pulse signal.
4. the driving method of a liquid crystal display drive circuit, it comprises the steps:
A. receive the signal of the representative GTG of external transmission successively, and export this signal together; B., one count signal is provided; C. the relatively signal of these a plurality of representative GTGs and this count signal, export a plurality of pulse signals with certain dutycycle, d. will these a plurality of pulse amplitudes be adjusted into a predetermined high level and and be scheduled to low level voltage difference and export each bar data line to, realize the demonstration of each GTG by the dutycycle of this pulse signal with certain dutycycle.
5. the driving method of liquid crystal display drive circuit as claimed in claim 4, it is characterized in that: among the step a, the signal of the representative GTG of external transmission is a Low Voltage Differential Signal, this step a further comprises: time schedule controller is converted to this Low Voltage Differential Signal the 2n position binary signal of representing GTG successively, and then export this 2n position binary signal digital deposit unit at the most successively, n 〉=3, these a plurality of digital deposit units are exported this 2n position binary signal together.
6. the driving method of liquid crystal display drive circuit as claimed in claim 5, it is characterized in that: step a further comprises: find a 2n+2m position binary signal corresponding with this 2n position binary signal successively from a question blank, and then export this 2n+2m position binary signal successively to these a plurality of digital deposit units, wherein, m 〉=1, the corresponding relation of this 2n+2m position binary signal and this 2n position binary signal satisfies the corresponding relation curve of the pixel voltage at actual displayed GTG and liquid crystal two ends.
7. the driving method of a liquid crystal display drive circuit, its signal and one that comprises the steps: that many comparing units of a. receive a plurality of representative GTGs respectively is the signal of linear change in time; B. export a plurality of pulse signals with certain dutycycle, c. will these a plurality of pulse amplitudes be adjusted into a predetermined high level and and be scheduled to low level voltage difference and export each bar data line to, realize the demonstration of each GTG by the dutycycle of this pulse signal with certain dutycycle.
8. LCD, it comprises that a liquid crystal display drive circuit and an operating voltage provide end, this operating voltage provides end to be used to this liquid crystal display drive circuit that operating voltage is provided, this liquid crystal display drive circuit comprises a data drive circuit, this data drive circuit comprises a digital register, this digital register is used for receiving successively the signal of the representative GTG of external transmission, and export this signal together, it is characterized in that: this data drive circuit further comprises a counter, one comparer and a logical circuit and a level shifting circuit, this counter is used to export count signal, this comparer receives signal and this count signal of these a plurality of representative GTGs, and according to the signal of these a plurality of representative GTGs with the output of this count signal is a plurality of has the pulse signal of certain dutycycle to this logical circuit, this logical circuit receives these a plurality of pulse signals with certain dutycycle and carries out logical process, and export this and a plurality ofly have the pulse signal of certain dutycycle to level shifting circuit, this level shifting circuit is used to change the pulse height of the pulse signal of this logical circuit output, and export these a plurality of pulse signals to each bar data line with certain dutycycle, realize the demonstration of each GTG by the dutycycle of this pulse signal.
9. LCD, it comprises that a liquid crystal display drive circuit and an operating voltage provide end, this operating voltage provides end to be used to this liquid crystal display drive circuit that operating voltage is provided, this liquid crystal display drive circuit comprises a data drive circuit, it is characterized in that: this data drive circuit comprises a comparer and a logical circuit and a signal input end, this comparer comprises a plurality of comparing units, each comparing unit comprises a first input end, one second input end and an output terminal, these a plurality of first input ends receive the signal of a plurality of representative GTGs, these a plurality of second input ends all receive a signal that is linear change in time, output of a plurality of output terminals is a plurality of has the pulse signal of certain dutycycle to this logical circuit for these, this signal input end outputs control signals to this logical circuit, this logical circuit receives these a plurality of pulse signal and these control signals with certain dutycycle and carries out logical process, and export these a plurality of pulse signals to each bar data line with certain dutycycle, realize the demonstration of each GTG by the dutycycle of this pulse signal.
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| CN2008100660330A CN101499248B (en) | 2008-02-01 | 2008-02-01 | LCD, LCD driving circuit and driving method thereof |
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| CN2008100660330A CN101499248B (en) | 2008-02-01 | 2008-02-01 | LCD, LCD driving circuit and driving method thereof |
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| CN109308881A (en) * | 2018-10-29 | 2019-02-05 | 惠科股份有限公司 | A kind of driving method of display panel, its driving device and display device |
| CN109493803B (en) * | 2018-10-29 | 2021-01-08 | 惠科股份有限公司 | Driving method and driving device of display panel and display device |
| CN109243363A (en) * | 2018-11-16 | 2019-01-18 | 重庆秉为科技有限公司 | A kind of control system of all-colour LED |
| CN111599315B (en) * | 2020-06-19 | 2021-11-16 | 京东方科技集团股份有限公司 | Shift register, grid driving circuit and driving method thereof |
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| CN1427383A (en) * | 2002-12-06 | 2003-07-02 | 北京利亚德电子科技有限公司 | LED display screen display control device and its control method |
| US20070262948A1 (en) * | 2006-05-11 | 2007-11-15 | Han Kwan Young | Backlight, method for driving backlight, and liquid crystal display having the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1427383A (en) * | 2002-12-06 | 2003-07-02 | 北京利亚德电子科技有限公司 | LED display screen display control device and its control method |
| US20070262948A1 (en) * | 2006-05-11 | 2007-11-15 | Han Kwan Young | Backlight, method for driving backlight, and liquid crystal display having the same |
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