CN101521567A

CN101521567A - Sampling method and data recovering circuit thereof

Info

Publication number: CN101521567A
Application number: CN200810081312A
Authority: CN
Inventors: 海谭古研; 陈威良; 陈元辉
Original assignee: United Microelectronics Corp
Current assignee: United Microelectronics Corp
Priority date: 2008-02-25
Filing date: 2008-02-25
Publication date: 2009-09-02
Anticipated expiration: 2028-02-25
Also published as: CN101521567B

Abstract

The invention discloses a sampling method and a data recovering circuit thereof. The sampling method comprises the steps as follows: firstly, a first clock, a second clock, a third clock and a fourth clock are provided, the second clock is left behind a first preset phase of the first clock, the third clock and the fourth clock are respectively left behind second preset phases of the first clock and the second clock, and the second preset phase is one half of the first preset phase; secondly, the first clock and the second clock are respectively utilized for sampling digital signals; thirdly, positions of data state switching points of the digital signals are judged according to sampling results of the first clock and the second clock; fourthly, according to the judging results, the third clock or the fourth clock are selected as a better sampling clock; and finally, the better sampling clock is utilized for sampling the digital signals.

Description

Sampling method and data recovery circuit thereof

Technical field

The present invention relates to a kind of sampling method and data recovery circuit thereof, and particularly relate to a kind of sampling method and data recovery circuit thereof that improves the correctness of data sampling.

Background technology

Link in (serial link) system at high speed serialization; usually can be inconsistent because of the drift or the chip layout of manufacture of semiconductor; or be because in connect the difference in length of metal wire (wire-int erconnect); variations in temperature; the variation of relay element (intermediate devices); capacitive coupling; the flaw (material imperfections) of metal part and the input capacitance difference of clock and signaling channel ... etc. factor; and cause received clock of receiving terminal (in association area of the present invention, the English of clock is strobe) and data that situation asynchronous or gap (skew) is arranged.

Fig. 1 is at the received clock of receiving terminal and the sequential chart of digital signal.As shown in Figure 1, when the clock CLK2 of clock CLK1 that receiving terminal received and its phase-locked loop (phase locked loop is called for short PLL) is synchronous, just can utilize the falling edge (falling edge) of clock CLK2 that the digital signal DATA that receives is taken a sample.In ideal conditions, the data state switching of digital signal DATA (transition) point aligns with the rising edge of clock CLK2.Thus, the falling edge of clock CLK2 will carry out data sampling at the intermediate point (just Zui Jia data sampling point, shown in mark 102) of each, obtains correct data with assurance.

Yet, when digital signal DATA falls behind or leads over clock CLK2, will gappedly occur, as shown in Figure 2.Fig. 2 is at the received clock of receiving terminal and another sequential chart of data.Do not align with the rising edge of clock CLK2 when the data state switching points of digital signal DATA, just produced gap 202.If gap 202 is too big, cause the falling edge of clock CLK2 just to drop on (shown in mark 204) near the data state switching points of digital signal DATA, just be sampled to wrong data easily.

For fear of being sampled to wrong data, United States Patent (USP) proposes a kind of oversampling (over sampling) technology for No. 5905769, as shown in Figure 3.Fig. 3 is the sampling clock of oversampling technology and a sequential chart of digital signal.In this figure, mark 24-1-24-12 all is expressed as the rising edge (rising edge) or the falling edge of sampling clock, those edges can be described as the sampling edge, and mark 28-1-28-4 then represents wherein four positions of digital signal DATA, and the value of position 28-1-28-4 is respectively 1,0,1 and 0.As for mark S[0]-S[11] then be expressed as the sampling result under the different time, its sampling value of numeral of each sampling result top.Figure can find out that sampling frequency is enhanced thus, so that each position can be sampled three times.With first three sampling result S[0]-S[2] be example, because the sampling value of these three sampling results is all 1, so the value of decidable first (28-1 ascends the throne) is 1.

Take a sample with such sampling technique, under digital signal and the nonsynchronous situation of sampling clock, still can be sampled to correct data, as shown in Figure 4.Fig. 4 is the sampling clock of oversampling technology and another sequential chart of digital signal.Please refer to Fig. 4, equally with first three sampling result S[0]-S[2] be example, be 1 because two sampling values are arranged in the middle of the sampling value of these three sampling results, having only a sampling value is 0, so also the value of decidable first (28-1 ascends the throne) is 1.In other words, as long as have two sampling values the same in the middle of three sampling values, just with the value of this identical value as sampled position.

Yet, even this oversampling technology can promote the correctness of data sampling, but, make the sampling edge drop under the situation of data state switching points at the excesssive gap of digital signal and sampling clock, judge the value of sampled position by this method, just wrongheaded situation can take place.

Summary of the invention

Purpose of the present invention is providing a kind of sampling method exactly, and it can improve the correctness of data sampling.

Another object of the present invention provides a kind of data recovery circuit, and it uses sampling method of the present invention, to improve the correctness of data sampling.

Based on above-mentioned and other purpose, the present invention proposes a kind of sampling method, the step of this sampling method comprises: at first, first clock, second clock, the 3rd clock and the 4th clock are provided, the frequency of each clock is identical, and second clock falls behind first clock, first preset phase, and the 3rd clock and the 4th clock fall behind first clock and second clock second preset phase respectively, and second preset phase is first preset phase half.Then, utilize first clock and second clock sampling digital signal respectively, and all with the rising edge of first clock and second clock or falling edge as the sampling edge, wherein, the bit length of digital signal equated with the clock cycle of first clock, second clock, the 3rd clock and the 4th clock.Then, judge the positions of data state switching points of digital signal according to the sampling result of first clock and second clock.Then, select with the 3rd clock or the 4th clock as preferable sampling clock according to judged result.Then, utilize preferable sampling clock sampling digital signal, wherein, the sampling edge of preferable sampling clock is identical with the sampling edge of first clock.

Based on above-mentioned and other purpose, the present invention proposes a kind of data recovery circuit, and this data recovery circuit includes oversampling module, time replacement module and clearance control module.The oversampling module is in order to receive first clock, second clock, the 3rd clock and the 4th clock, the frequency of each clock is identical, and second clock falls behind first clock, first preset phase, and the 3rd clock and the 4th clock fall behind first clock and second clock second preset phase respectively, and second preset phase is first preset phase half.During the first, the oversampling module is utilized first clock and second clock sampling digital signal, and all with the rising edge of first clock and second clock or falling edge as the sampling edge.During the second, the oversampling module is utilized the 3rd clock and the 4th clock sampling digital signal, and the sampling edge of the 3rd clock and the 4th clock is identical with the sampling edge of first clock.In addition, the oversampling module also is converted to parallel data with sampling result, and with the output as the oversampling module, and the bit length of above-mentioned digital signal equated with the clock cycle of above-mentioned four clocks.The parallel data that time replacement module is exported in order to synchronous oversampling module is to produce synchronized result.The clearance control module during the first, judge the positions of data state switching points of digital signal according to synchronized result, select the 3rd clock or the 4th clock as preferable sampling clock with the foundation judged result, and during the second, clearance control module controls time replacement module, time replacement module is selected from synchronized result by the synchronous concatenation data that preferable sampling clock obtained, with the output as data recovery circuit.

Based on above-mentioned and other purpose, the present invention proposes another kind of data recovery circuit, and this data recovery circuit includes oversampling module, time replacement module and clearance control module.The oversampling module receives first clock, second clock, the 3rd clock, the 4th clock, the 5th clock, the 6th clock, the 7th clock and the 8th clock, the frequency of each clock is identical, and second clock falls behind first clock, first preset phase, the 3rd clock and the 4th clock fall behind first clock and second clock second preset phase respectively, and the 5th clock, the 6th clock, the 7th clock and the 8th clock fall behind first clock respectively, second clock, the 3rd clock and the 4th clock the 3rd preset phase, and second preset phase is first preset phase half, and the 3rd preset phase is second preset phase half.During the first, the oversampling module is utilized first clock and second clock sampling digital signal, and all with the rising edge of first clock and second clock or falling edge as the sampling edge.During the second, the oversampling module is utilized the 3rd clock and the 4th clock sampling digital signal, and the sampling edge of the 3rd clock and the 4th clock is identical with the sampling edge of first clock.In between the third phase, the oversampling module is utilized the 5th clock and the 6th clock digital signal of taking a sample, or utilizes the 7th clock and the 8th clock digital signal of taking a sample.Wherein, the sampling edge of the 5th clock, the 6th clock, the 7th clock and the 8th clock is identical with the sampling edge of first clock.In addition, the oversampling module is converted to parallel data with sampling result, and with the output as the oversampling module, and the bit length of above-mentioned digital signal equated with the clock cycle of above-mentioned eight clocks.The parallel data that time replacement module is exported in order to synchronous oversampling module is to produce synchronized result.The clearance control module according to the positions of data state switching points of synchronized result judgement digital signal, selects the 3rd clock or the 4th clock as preferable sampling clock with the foundation judged result during the first.During the second, the clearance control module is judged the positions of data state switching points of digital signal according to synchronized result, and selects to differ one of them of two clocks of the 3rd preset phase as best sampling clock with preferable sampling clock according to judged result.In between the third phase, clearance control module controls oversampling module is selected best sampling clock and is taken a sample with the clock that best sampling clock differs first preset phase, and control time replacement module, time replacement module is selected from synchronized result by the synchronous concatenation data that best sampling clock obtained, with the output as data recovery circuit.

Described according to one embodiment of the invention, it also comprises the time of delay of coming the control figure signal according to the residing position of the data state switching points of digital signal, so that the intermediate point of the position of digital signal is adjusted to the sampling edge of (/) good sampling clock, or make the intermediate point convergence sampling edge of (/) good sampling clock of the position of digital signal.

The present invention is because of providing four frequencies identical, but has the sampling clock that out of phase postpones, and second clock wherein falls behind first clock, first preset phase, the 3rd clock and the 4th clock then fall behind first clock and second clock second preset phase respectively, and second preset phase is half of first preset phase.Then, utilize first clock and second clock to judge the data state switching points position of digital signal, and select the sampling edge in the middle of the 3rd clock and the 4th clock and be used as preferable sampling clock near the clock of the position intermediate point of digital signal, utilizing the preferable sampling clock digital signal of taking a sample, and then improve the correctness of data sampling.Even, the present invention also can arrange in pairs or groups and utilize the skill of the time of delay of adjusting digital signal, so that the intermediate point of the position of digital signal is adjusted to the sampling edge of preferable sampling clock, or make the sampling edge of the preferable sampling clock of intermediate point convergence of the position of digital signal, further to improve the correctness of data sampling.

For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.

Description of drawings

Fig. 1 is at the received clock of receiving terminal and the sequential chart of digital signal.

Fig. 2 is at the received clock of receiving terminal and another sequential chart of data.

Fig. 3 is the sampling clock of oversampling technology and a sequential chart of digital signal.

Fig. 4 is the sampling clock of oversampling technology and another sequential chart of digital signal.

Fig. 5 (a)-Fig. 5 (c), 6 (a)-Fig. 6 (c), Fig. 7 (a)-Fig. 7 (b), Fig. 8 (a)-Fig. 8 (c), Fig. 9 (a)-Fig. 9 (c) and Figure 10 (a)-Figure 10 (b) are all the key diagram according to sampling method of the present invention.

Figure 11 is for using a wherein preferable operational flowchart of sampler of the present invention.

Figure 12, Figure 13, Figure 15 and Figure 16 are all the wherein calcspar of a data recovery circuit that adopts sampling method of the present invention.

Figure 14 is the circuit block diagram of wherein a kind of execution mode of variable delay module 1240.

Figure 17 is the flow chart according to the sampling method of one embodiment of the invention.

The figure elements symbol description

24-1-24-12: sampling edge

28-1-28-4: position

102,204: mark

202: the gap

1102-1112,1702-1710: step

1210,1510: the oversampling module

1212,1214,1414,1426,1512,1514: multiplexer

1216,1516: the oversampling circuit

1220,1520: time replacement module

1230,1530: the clearance control module

1240,1540: the variable delay module

1410: the phase I delay control circuit

1420: the second stage delay control circuit

1411-1413,1421-1425: delay cell

A, B, C, D, A ', B ', C ', D ', CLK1, CLK2: clock

CS1, CS2: control signal

DATA: digital signal

DS: the output of variable delay module

OS: the output of oversampling circuit

OUT: the output of data recovery circuit

S[0]-S[11]: sampling result

SL: select signal

TS: synchronized result.

Embodiment

Fig. 5 (a) is the key diagram according to sampling method of the present invention.Please refer to Fig. 5 (a), for convenience of description, it is identical that mark A, B, C and the D among the figure is expressed as four frequencies, but have clock that out of phase postpones (in association area of the present invention, the English of clock is strobe), and identical mark is represented identical clock.Then being expressed as the sampling edge of this clock as for mark A, B, C and the other arrow of D, is example with the arrow on two mark A next doors in scheming, and these two arrows are represented the sampling edge of two adjacent pulses of clock A.

In these four clocks, clock B falls behind clock A first preset phase, and clock C and clock D then fall behind clock A and clock B second preset phase respectively, and second preset phase is first preset phase half.With this example, it is 180 ° that first preset phase is stipulated, so second preset phase is 90 °.By among the figure as can be known, clock A, clock B, clock C and clock D all use rising edge or falling edge to be used as the edge of taking a sample.In addition, mark DATA is expressed as digital signal, and its data are to transmit in the mode of serial, and the bit length of digital signal DATA equated with the clock cycle of above-mentioned four clocks.

Please continue with reference to Fig. 5 (a), at first, utilize clock A and the clock B digital signal DATA that takes a sample respectively.Then, judge the positions of data state switching points of digital signal DATA according to the sampling result of clock A and clock B.The mode of judgment data state switching points position can use following two formulas to illustrate:

(A[0]XOR?B[0])+(A[1]XOR?B[1])+(A[2]XOR?B[2])+…+(A[M-1]XOR?B[M-1])

... (formula 1)

(B[0]XOR?A[1])+(B[1]XOR?A[2])+(B[2]XOR?A[3])+…+(B[M-1]XOR?A[M])

... (formula 2)

Whether formula 1 is to be used for the position of judgment data state switching points to be positioned at after the sampling edge of clock A before the sampling edge with clock B, and whether 2 of formulas are to be used for the position of judgment data state switching points to be positioned at after the sampling edge of clock B before the sampling edge with clock A.

In formula 1 and formula 2, A[0]-A[M] total (M+1) the individual sampling result of expression clock A, and B[0] ^-B[M] represent that then clock B has (M+1) individual sampling result, wherein, M is a positive integer, a plurality of purpose of taking a sample is correct for guaranteeing sampling result again.Then represent the sampling result of clock A and clock B is carried out XOR (exclusive-OR) computing as for XOR.In judgment data state switching points position, need use formula 1 and formula 2 described modes to judge simultaneously.If formula 1 resulting value is a nonzero value, and formula 2 resulting values are zero, and the position that then can judge the judgment data state switching points is positioned at after the sampling edge of clock A before the sampling edge with clock B, and promptly data state switching points is positioned at A[0] and B[0] between, and A[1] and B[1] between, by that analogy.Otherwise if formula 1 resulting value is zero, and formula 2 resulting values are nonzero value, then but the position of judgment data state switching points is positioned at after the sampling edge of clock B before the sampling edge with clock A, be that data state switching points is positioned at B[0] and A[1] between, and B[1] and A[2] between, by that analogy.

Next, just can select to be used as preferable sampling clock according to judged result with clock C or clock D.In this example, because positions of data state switching points is positioned at after the sampling edge of clock A before the sampling edge with clock B, and just between the two the centre at sampling edge of clock A and clock B, therefore the sampling edge of clock D is positioned at the intermediate point (Zui Jia data sampling point just) of the position of digital signal DATA, so can select clock D as preferable sampling clock, and utilize clock D to carry out data sampling, obtain correct data with assurance.Certainly, in more rigorous system, utilize clock A and clock B to come the step of judgment data state switching points position can be repeated repeatedly, to avoid judging by accident positions of data state switching points.

Example shown in Fig. 5 (a) is an ideal situation, so that the sampling edge of clock D is positioned at the intermediate point of the position of digital signal DATA just, but under nonideal situation, according to the selected preferable sampling clock of judged result, its the sampling edge still can digital signal DATA the position intermediate point near, shown in Fig. 5 (b) and Fig. 5 (c).Fig. 5 (b) and Fig. 5 (c) are another key diagram according to sampling method of the present invention.Please earlier with reference to Fig. 5 (b), figure can obviously find out thus, the data state switching points position of digital signal DATA also is positioned at after the sampling edge of clock A before the sampling edge with clock B, but than sampling edge near clock A, therefore in the middle of the two sampling edge of clock C and clock D, the sampling edge of clock D can be near the intermediate point of the position of digital signal DATA, so select clock D to make comparatively ideal of sampling.Referring again to Fig. 5 (c), figure can obviously find out thus, the data state switching points position of digital signal DATA also is before the sampling edge that is positioned at after the sampling edge of clock A with clock B, but near the sampling edge of clock B, so select clock D to make comparatively ideal of sampling.

Above-mentioned Fig. 5 (a)-Fig. 5 (c) for example, all be to be example before being positioned at after the sampling edge of clock A sampling edge with clock B with the data state switching points position, therefore all select clock D as preferable sampling clock, but be positioned at after the sampling edge of clock B before the sampling edge with clock A if judge positions of data state switching points, then select clock C comparatively desirable, shown in Fig. 6 (a)-Fig. 6 (c), just can understand as preferable sampling clock.Fig. 6 (a)-Fig. 6 (c) also is another key diagram according to sampling method of the present invention.Because Fig. 6 (a)-described mode of operation of Fig. 6 (c) and Fig. 5 (a)-described mode of operation of Fig. 5 (c) are extremely similar, the user just repeats no more at this when understanding the rest by analogy.Except Fig. 5 (a)-Fig. 5 (c) and Fig. 6 (a)-described situation of Fig. 6 (c), when judging positions of data state switching points and be positioned at the sampling edge of clock A or the sampling edge of clock B, then can select clock C and clock D wherein arbitrary, shown in Fig. 7 (a) and Fig. 7 (b), just can understand as preferable sampling clock.Fig. 7 (a) and Fig. 7 (b) are another key diagram according to sampling method of the present invention.

By above-mentioned example as can be known, because the sampling edge of just having got rid of preferable sampling clock in the selection course of preferable sampling clock is positioned at the possibility of data state switching points, therefore by the obtained data of this sampling mode, its correctness can be than coming highly by the correctness of the obtained data of prior art.

In addition, under nonideal situation, the sampling edge of preferable sampling clock can't be positioned at the intermediate point of the position of digital signal DATA, and the present invention more provides a method, can be by suitably adjusting the time of delay of digital signal DATA, allow the intermediate point of position of digital signal DATA move to the sampling edge of preferable sampling clock, perhaps, allow the intermediate point of position of digital signal DATA level off to the sampling edge of preferable sampling clock at least.

The adjustment mode of time of delay is as follows: at first, after selected clock C or clock D are as preferable sampling clock, further going the decision data state switching points again is before the sampling edge that is positioned at after the sampling edge of clock C with clock D, still be positioned at after the sampling edge of clock D before the sampling edge with clock C, to carry out the adjustment of the time of delay of digital signal DATA according to judged result.For instance, if select clock D as preferable sampling clock, and the decision data state switching points is positioned at after the sampling edge of clock C before the sampling edge with clock D, therefore the intermediate point of the position of digital signal DATA falls behind the sampling edge of clock D as can be known, so will reduce the time of delay of digital signal DATA, so that the intermediate point of the position of digital signal DATA is adjusted to the sampling edge of clock D.Relative, if select clock D as preferable sampling clock, but the data state switching points position is positioned at after the sampling edge of clock D before the sampling edge with clock C, therefore the sampling edge of the leading clock D of intermediate point of the position of digital signal DATA as can be known, so will increase the time of delay of digital signal DATA, so that the intermediate point of the position of digital signal DATA is adjusted to the sampling edge of clock D.In like manner, if select clock C, also can sharp carry out the control of time of delay in the same way as preferable sampling clock.

In the middle of the adjustment mode of above-mentioned time of delay, no matter be the time of delay that increases or reduce digital signal DATA, each adjustment can with the single stage or being divided into a plurality of stages implements.For example, then can be divided into rough adjustment and adjust with thin portion to be divided into two stages.Utilize earlier rough the adjustment to carry out significantly the time and adjust, and then utilize thin portion to adjust to make the sampling edge of the more close preferable sampling clock of intermediate point of position.Wherein, the adjusting range of rough adjustment the (just the first stage is adjusted) should not can greater than 1/4th of bit length.

In addition, because the adjustment in each stage all possibly can't once just be adjusted to the right place, therefore the actual needs during user's viewable design and allow the adjustment in each stage carry out several times more, and can go to the position of judgment data state switching points again after each the adjustment, according to this position of the intermediate point of decision bits whether be adjusted excessive, further to obtain the optimum delay time in this stage.If a certain stage be adjusted at constantly conversion (the toggle phenomenon promptly occurring) between certain two time of delay, so as long as the time of implementation in each stage of qualification, and limit, and then proceed the adjustment of next stage and get final product by the optimum delay time of the time of delay of finally obtaining as this stage.

Have the knack of this skill person, the number that also can increase clock is operated, as long as the sum of clock equals 2N, wherein, N is a positive integer.Fig. 8 (a) is another key diagram according to sampling method of the present invention.Please after comparison, can find simultaneously with reference to Fig. 5 (a) and Fig. 8 (a), Fig. 8 (a) than Fig. 5 (a) many four clocks, come mark with A ', B ', C ' and D ' respectively, and identical mark is represented identical clock.Also being expressed as the sampling edge of this clock as for mark A ', B ', C ' and the other arrow of D ', is example with the arrow on two mark A ' next doors in scheming, and these two arrows are represented the sampling edge of two adjacent pulses of clock A '.

In these eight clocks, the frequency of clock A ', clock B ', clock C ' and clock D ' four is identical with the frequency of clock A, and clock A ', clock B ', clock C ' and clock D ' fall behind clock A, clock B, clock C and clock D the 3rd preset phase respectively, and the 3rd preset phase is second preset phase half.With this example, it is 180 ° that first preset phase is also stipulated, so second preset phase is 90 °, and the 3rd preset phase is 45 °.By among the figure as can be known, clock A ', clock B ', clock C ' and clock D ' all use rising edge or falling edge to be used as the edge of taking a sample, and this sampling edge is identical with the sampling edge of clock A.In addition, mark DATA also is expressed as digital signal, and the clock cycle of eight clocks among the bit length of digital signal DATA and the figure equates.

Please continue with reference to Fig. 8 (a), though Fig. 8 (a) utilizes 8 clocks to operate, yet it obtains the mode and the described acquisition mode striking resemblances of Fig. 5 (a) of preferable sampling clock.With this example, be to utilize clock A and clock B to judge the positions of data state switching points of digital signal, from clock C and clock D, select clock D then and be used as preferable sampling clock.Yet Fig. 8 (a) and the two described mode of Fig. 5 (a) different be in, the described mode of Fig. 8 (a) more will be different from the middle of clock C and the clock D preferable sampling clock person as reference clock (also be about to clock C and be used as reference clock), and then utilize clock C and the clock D digital signal DATA that takes a sample.Then, judge the positions of data state switching points of digital signal DATA according to the sampling result of clock D and clock C.The mode of judgment data state switching points position can use following two formulas to illustrate:

(C[0]XOR?D[0])+(C[1]XOR?D[1])+(C[2]XOR?D[2])+…+(C[M-1]XOR?D[M-1])

... (formula 3)

(D[0]XOR?C[1])+(D[1]XOR?C[2])+(D[2]XOR?C[3])+…+(D[M-1]XOR?C[M])

... (formula 4)

Whether formula 3 is to be used for the position of judgment data state switching points to be positioned at after the sampling edge of clock C before the sampling edge with clock D, and whether 4 of formulas are to be used for the position of judgment data state switching points to be positioned at after the sampling edge of clock D before the sampling edge with clock C.

In formula 3 and formula 4, C[0]-C[M] total (M+1) the individual sampling result of expression clock C, D[0]-D[M] represent that then clock D has (M+1) individual sampling result, wherein M is a positive integer.Then represent the sampling result of clock C and clock D is carried out XOR as for XOR.In judgment data state switching points position, also need use formula 3 and formula 4 described modes to judge simultaneously.If formula 3 resulting values are nonzero value, and formula 4 resulting values are zero, and the position that then can judge the judgment data state switching points is positioned at after the sampling edge of clock C before the sampling edge with clock D.Otherwise if formula 3 resulting values are zero, and formula 4 resulting values are nonzero value, but then the position of judgment data state switching points is positioned at after the sampling edge of clock D before the sampling edge with clock C.

Next, just can select to differ 45 ° one of them of two clocks as best sampling clock, just select clock B ' or clock D ' as best sampling clock according to judged result with clock D (being preferable sampling clock).In Fig. 8 (a), because positions of data state switching points is just between the two the centre at sampling edge of clock A and clock B, and be positioned at the sampling edge of clock C just, then clock B ' or clock D ' are wherein arbitrary all can be used as best sampling clock.Though in this example, the two sampling edge of clock B ' and clock D ' is not the intermediate point that is positioned at the position of digital signal DATA with respect to clock D, but still very approaching, so can be sampled to correct data.Certainly, in more rigorous system, utilize clock C and clock D to come the step of judgment data state switching points position also can repeat repeatedly, to avoid judging by accident positions of data state switching points.

Fig. 8 (b) and Fig. 8 (c) also are another key diagram according to sampling method of the present invention, and this two diagram is an example with 8 clocks also.Please earlier with reference to Fig. 8 (b), figure can obviously find out thus, the data state switching points position of digital signal DATA is positioned at after the sampling edge of clock D before the sampling edge with clock C, but than sampling edge near clock C, therefore, in the middle of the two sampling edge of clock B ' and clock D ', the sampling edge of clock B ' can be near the intermediate point of the position of digital signal DATA, so select clock B ' to make comparatively ideal of sampling.Referring again to Fig. 8 (c), figure can obviously find out thus, the data state switching points position of digital signal DATA is positioned at after the sampling edge of clock C before the sampling edge with clock D, but near the sampling edge of clock C, so select clock D ' to make comparatively ideal of sampling.

Above-mentioned Fig. 8 (a)-Fig. 8 (c) for example, its data state switching points position all is positioned at after the sampling edge of clock A before the sampling edge with clock B, and then utilizes clock C and clock D to judge best sampling clock.Below all be positioned at after the sampling edge of clock B before the sampling edge with clock A with the data state switching points position again, and then utilize clock C and clock D to judge best sampling clock to be example, shown in Fig. 9 (a)-Fig. 9 (c).Fig. 9 (a)-Fig. 9 (c) is another key diagram according to sampling method of the present invention.In addition, positions of data state switching points is positioned at the sampling edge of clock A or the sampling edge of clock B, and then utilizes clock C and clock D to judge the example of best sampling clock, then represents in Figure 10 (a) and Figure 10 (b).Figure 10 (a) and Figure 10 (b) also are another key diagram according to sampling method of the present invention.Since Fig. 9 (a)-Fig. 9 (c) and Figure 10 (a)-described mode of operation of Figure 10 (b) and Fig. 8 (a)-Fig. 8 (c) be described-mode of operation is extremely similar, and in these diagrams, presented the sequential relationship between each clock and the digital signal, the user just repeats no more at this when picking out best sampling clock easily by diagram.

By above-mentioned example as can be known, carry out sampling operation by eight clocks, its correctness can be come highly than the correctness of carrying out sampling operation by four clocks.In addition, although under nonideal situation, the sampling edge of best sampling clock can't be positioned at the intermediate point of the position of digital signal DATA, yet the user but equally can be by suitably adjusting the time of delay of digital signal DATA, for example utilize the mode of the time of delay of aforementioned adjustment digital signal DATA, allow the intermediate point of position of digital signal DATA move to the sampling edge of best sampling clock, perhaps, allow the intermediate point of position of digital signal DATA level off to the sampling edge of best sampling clock at least.Certainly, should be less than 1/8th of the bit length that equals digital signal by the delay scope that can adjust the time of delay of control figure signal DATA.

Can know that from the described method of above each embodiment for using sampler of the present invention, its preferable operating process should comprise the adjustment action of the time of delay of digital signal, as shown in figure 11.Figure 11 is for using a wherein preferable operational flowchart of sampler of the present invention.Please refer to Figure 11, this sampler (not shown) can be according to following flow operations: at first, select best sampling clock (as step 1102) from 2N sampling clock.Then, adjust the time of delay (as step 1104) of digital signal roughly.Then, judge whether the rough action of adjusting surpasses its scheduled time (as step 1106).When being judged as not, continue the rough time of delay of adjusting digital signal; When being judged as when being, then thin portion adjusts the time of delay (as step 1108) of digital signal.Then, judge whether the action that thin portion adjusts surpasses its scheduled time (as step 1110).When being judged as not, continue the time of delay that thin portion adjusts digital signal; When being judged as when being, then dynamically adjust the time of delay of digital signal, so that the intermediate point of the position of digital signal is near the sampling edge (as step 1112) of selected sampling clock.By such sampling mode, the probability that this sampler is sampled to misdata will reduce widely.Certainly, operating process shown in Figure 11 not necessarily will be adjusted through two stages, might need only a stage, for example only adjusts roughly.Thus, after judging that the rough action of adjusting has surpassed its scheduled time, just direct execution in step 1112.

Figure 12 recovers the calcspar of (data recovery) circuit for wherein data that adopt sampling method of the present invention.Please refer to Figure 12, this data recovery circuit includes oversampling module 1210, time replacement module 1220 and clearance control module 1230.Oversampling module 1210 is in order to receive clock A, clock B, clock C and clock D, the frequency of these four clocks is all identical, and clock B falls behind clock A first preset phase, and clock C and clock D fall behind clock A and clock B second preset phase respectively, and second preset phase is first preset phase half.In this example, it is 180 ° that first preset phase is stipulated, so second preset phase is 90 °.In addition, the data of digital signal DATA are to transmit in the mode of serial, and the bit length of digital signal DATA equated with the clock cycle of above-mentioned four clocks.

Circuit shown in Figure 12 is operated during being divided into two, and at first, during the first, oversampling module 1210 is utilized clock A and the clock B digital signal DATA that takes a sample, and all with the rising edge of clock A and clock B or falling edge as the sampling edge.And oversampling module 1210 is converted to parallel data with sampling result, with the output OS as oversampling module 1210.Then, the parallel data that time replacement module 1220 synchronous oversampling modules 1210 are exported is to produce synchronized result TS.This synchronized result TS is through the parallel data after synchronously, thus data in temporal datum mark by original inconsistent unanimity that is adjusted into.In this example, an independent clock these parallel datas of resampling that can utilize synchronously of parallel data reach.Then, clearance control module 1230 selects clock C or clock D as preferable sampling clock according to the positions of data state switching points that synchronized result TS judges digital signal DATA with the foundation judged result.Judge that the mode of the data state switching points position of digital signal DATA explained in the related description of aforementioned formula (1) and formula (2), and the selection mode of preferable sampling clock also formerly embodiment just discussed, neitherly give unnecessary details again at this.

After selecting preferable sampling clock, this data recovery circuit just enters the second phase and operates.During the second, oversampling module 1210 is utilized clock C and the clock D digital signal DATA that takes a sample, and the sampling edge of clock C and clock D is identical with the sampling edge of clock A.And oversampling module 1210 is converted to parallel data with sampling result, with the output OS as oversampling module 1210.Then, the parallel data that time replacement module 1220 synchronous oversampling modules 1210 are exported is to produce synchronized result TS.Then, clearance control module 1230 control time replacement module 1220 is selected by the synchronous concatenation data that preferable sampling clock obtained, with the output OUT as data recovery circuit time replacement module 1220 from synchronized result TS.

In this example, oversampling module 1210 realizes with

multiplexer

1212,1214 and oversampling circuit 1216.Multiplexer 1212 is in order to receive clock A and clock C, and exports clock A and clock C respectively between the first phase and in the second phase.Multiplexer 1214 is in order to receive clock B and clock D, and exports clock B and clock D respectively between the first phase and in the second phase.Oversampling circuit 1216 is in order to the clock that utilizes multiplexer 1212 and multiplexer 1214 the to be exported digital signal DATA that takes a sample.In addition, the user can utilize and independently select the signal (not shown) to input to multiplexer 1212 and multiplexer 1214, carry out the selection of clock to control these two multiplexers, as long as select the selection target of signal can cooperate the selection target that reaches the second phase between the above-mentioned first phase.Certainly, by suitable circuit design, the user also can select to utilize clearance control module 1230 to export above-mentioned selection signal.

In the related description of Figure 11, once mentioned, for using sampler of the present invention, its preferable operating process should comprise the adjustment action of the time of delay of digital signal, and the mode of the time of delay of control figure signal comprises the time of delay of coming control figure signal DATA in the mode that is divided into a plurality of stages.Below just come give an example the time of delay of control figure signal DATA, as shown in figure 13 in the mode of using 2 stages.

Figure 13 is the calcspar of wherein another data recovery circuit of employing sampling method of the present invention.Please after comparison, can find simultaneously with reference to Figure 12 and Figure 13, variable delay module 1240 that data recovery circuit shown in Figure 13 is many, and oversampling circuit 1216 is more by variable delay module 1240 receiving digital signals DATA.This variable delay module 1240 is come the time of delay of control figure signal DATA according to control signal CS1 and CS2, and control signal CS1 and CS2 be clearance control module 1230 during the second, produce according to the residing position of the data state switching points of digital signal DATA.Control signal CS1 is in order to carrying out the control of phase I, and control signal CS2 is in order to carry out the control of second stage.Therefore, the delay scope that the delay scope that control signal CS2 can adjust can be adjusted less than control signal CS1, and utilize delay scope that control signal CS1 can adjust smaller or equal to 1/4th of the bit length of digital signal DATA.After variable delay module 1240 was come the time of delay of control figure signal DATA according to control signal CS1 and CS2, oversampling circuit 1216 was just taken a sample according to

multiplexer

1212 and 1214 clocks of the being exported output DS to variable delay module 1240.

In order to be illustrated more clearly in control signal CS1 and CS2 time of delay of control figure signal DATA how, below enumerate wherein a kind of execution mode of variable delay module 1240 again, as shown in figure 14.Figure 14 is the circuit block diagram of wherein a kind of execution mode of variable delay module 1240.Please refer to Figure 14, this variable delay module 1240 includes phase I delay control circuit 1410 and second stage delay control circuit 1420.Phase I delay control circuit 1410 includes delay cell 1411-1413 and multiplexer 1414, and second stage delay control circuit 1420 includes delay cell 1421-1425 and multiplexer 1426.These delay cells are all implemented with the inverter (inverter) of a plurality of serial connections, and the serial connection number of the inverter in each delay cell is neither together, so the time that each delay cell can postpone is also all different.

In phase I delay control circuit 1410,

delay cell

1411,1412 and 1413 threes' the minimum delay time that is set at this phase I time of delay respectively, default time of delay and maximum time of delay, multiplexer 1414 selects to keep default time of delay according to control signal CS1 more then, perhaps selects to be adjusted to maximum time of delays and minimum delay time the two one of them.In addition, minimum delay time and default time of delay between the two apart from and default time of delay and maximum time of delays the two spacing equate that and spacing is all smaller or equal to 1/4th of the bit length of digital signal DATA.In other words, by the delay scope that can adjust the time of delay of phase I delay control circuit 1410 control figure signal DATA smaller or equal to 1/4th of the bit length of digital signal DATA.

In like manner, in second stage delay control circuit 1420,

delay cell

1421,1422,1423,1424 and 1425 the minimum delay time that is set at this second stage time of delay respectively, inferior few time of delay, default time of delay, inferior many time of delays and maximum time of delay, multiplexer 1426 selects to keep default time of delay according to control signal CS2 more then, perhaps select to be adjusted to minimum delay time, inferior few time of delay, inferior many time of delays and maximum time of delay one of them.In the delay control of second stage, the two the two the two the two spacing of spacing, inferior many time of delays and maximum time of delays of spacing, default time of delay and time many time of delays of spacing, inferior few time of delay and default time of delay of minimum delay time and time few time of delay, above-mentioned four spacings are all equal.

In addition, the minimum delay time of second stage and default time of delay between the two apart from and default time of delay and time of delays at most the two spacing, all less than the minimum delay time and default time of delay of phase I the two spacing and default time of delay and maximum time of delays the two spacing.In other words, the delay scope that can adjust less than the phase I of the delay scope that can adjust of second stage.Therefore, the delay of phase I control is to adjusting roughly the time of delay of digital signal DATA, and the delay of second stage control is to adjust carrying out thin portion the time of delay of digital signal DATA.Certainly, just wherein a kind of embodiment of delay control circuit that this figure represented, the user is when the number that can change the delay cell in each delay control circuit according to the demand of actual design, or even the number of increase delay control circuit, to carry out trickleer adjustment.

Above what introduce is the data recovery circuit of obtaining a preferable sampling clock from four sampling clocks, next will introduce the data recovery circuit of obtaining best sampling clock from eight sampling clocks, as shown in figure 15.Figure 15 is the calcspar of wherein another data recovery circuit of employing sampling method of the present invention.Please refer to Figure 15, this data recovery circuit includes oversampling module 1510, time replacement module 1520 and clearance control module 1530.Oversampling module 1510 is in order to receive clock A, clock B, clock C, clock D, clock A ', clock B ', clock C ' and clock D ', the frequency of these eight clocks is all identical, and clock B falls behind clock A first preset phase, clock C and clock D fall behind clock A and clock B second preset phase respectively, clock A ', clock B ', clock C ' and clock D ' then fall behind clock A, clock B, clock C, clock D the 3rd preset phase respectively, and second preset phase is first preset phase half, and the 3rd preset phase is second preset phase half.In this example, it is 180 ° that first preset phase is stipulated, so second preset phase is 90 °, second preset phase then is 45 °.In addition, the data of digital signal DATA are to transmit in the mode of serial, and the bit length of digital signal DATA equated with the clock cycle of above-mentioned eight clocks.

Circuit shown in Figure 15 is operated during being divided into three, and at first, during the first, oversampling module 1510 is utilized clock A and the clock B digital signal DATA that takes a sample, and all with the rising edge of clock A and clock B or falling edge as the sampling edge.And oversampling module 1510 is converted to parallel data with sampling result, with the output OS as oversampling module 1510.Then, the parallel data that time replacement module 1520 synchronous oversampling modules 1510 are exported is to produce synchronized result TS.This synchronized result TS is through the parallel data after synchronously, thus data in temporal datum mark by original inconsistent unanimity that is adjusted into.In this example, an independent clock these parallel datas of resampling that also can utilize synchronously of parallel data reach.Then, clearance control module 1530 selects clock C or clock D as preferable sampling clock according to the positions of data state switching points that synchronized result TS judges digital signal DATA with the foundation judged result.Judge that the mode of the data state switching points position of digital signal DATA explained in the related description of aforementioned formula (1) and formula (2), and the selection mode of preferable sampling clock also formerly embodiment just discussed, neitherly give unnecessary details again at this.

After selecting preferable sampling clock, this data recovery circuit just enters the second phase and operates.During the second, oversampling module 1510 is utilized clock C and the clock D digital signal DATA that takes a sample, and the sampling edge of clock C and clock D is identical with the sampling edge of clock A.And oversampling module 1510 is converted to parallel data with sampling result, with the output OS as oversampling module 1510.Then, the parallel data that time replacement module 1520 synchronous oversampling modules 1510 are exported is to produce synchronized result TS.Then, clearance control module 1530 is judged the positions of data state switching points of digital signal according to synchronized result TS, and one of them of two clocks of selecting to differ the 3rd preset phase with preferable sampling clock according to judged result be as best sampling clock, and produce according to best sampling clock and to select signal SL.Utilize clock C and clock D to judge that the mode of the data state switching points position of digital signal DATA explained in the related description of aforementioned formula (3) and formula (4), and the selection mode of best sampling clock also formerly embodiment just discussed, neitherly give unnecessary details again at this.

After selecting best sampling clock, this data recovery circuit just enters between the third phase and operates.In between the third phase, oversampling module 1510 is according to selecting signal SL to select clock A ' and clock B ' the digital signal DATA that takes a sample, or selects clock C ' and clock D ' the digital signal DATA that takes a sample.In a word, oversampling module 1510 can be taken a sample according to selecting signal SL to select best sampling clock and differ 180 ° clock with best sampling clock from clock A ', clock B ', clock C ' and clock D ', and the sampling edge of the sampling edge clock A of these two clocks is identical.And oversampling module 1510 is converted to parallel data with sampling result, with the output OS as oversampling module 1510.Then, the parallel data that time replacement module 1520 synchronous oversampling modules 1510 are exported is to produce synchronized result TS.Then, clearance control module 1530 control time replacement module 1520 is selected by the synchronous concatenation data that best sampling clock obtained, with the output OUT as data recovery circuit time replacement module 1520 from synchronized result TS.

In this example, oversampling module 1510 realizes with

multiplexer

1512,1514 and oversampling circuit 1516.Multiplexer 1512 is in order to receive clock A, clock C, clock A ' and clock C ', and between the first phase and in the second phase, export clock A and clock C respectively, and between the third phase, multiplexer 1512 is according to selecting signal SL to carry out the selection of clock, is used as output to select best sampling clock or differ 180 ° clock with best sampling clock in the middle of clock A ' and clock C '.Multiplexer 1514 is in order to receive clock B, clock D, clock B ' and clock D ', and between the first phase and in the second phase, export clock B and clock D respectively, and between the third phase, multiplexer 1514 carries out the selection of clock according to selection signal SL, and the clock that differs 180 ° with the output from clock B ' and central selection of clock D ' and multiplexer 1512 is used as output.The clock sampling digital signal DATA that oversampling circuit 1516 is exported in order to utilize

multiplexer

1512 and 1514.

Similarly, circuit shown in Figure 15 also can increase by a variable delay module, to be used for adjusting the time of delay of digital signal DATA.Below also come give an example the time of delay of control figure signal DATA, as shown in figure 16 in the mode of using 2 stages.Figure 16 is the calcspar of wherein another data recovery circuit of employing sampling method of the present invention.Please after comparison, can find simultaneously with reference to Figure 15 and Figure 16, variable delay module 1540 that circuit shown in Figure 16 is many, and oversampling circuit 1516 is more by variable delay module 1540 receiving digital signals DATA.The mode of operation striking resemblances of the mode of operation of this variable delay module 1540 and the variable delay module 1240 among Figure 13, so the internal circuit of variable delay module 1540 also can adopt as shown in figure 14, and the mode of circuit realizes.

According to the teaching of the various embodiments described above, can summarize some basic operating processes, as shown in figure 17.Figure 17 is the flow chart according to the sampling method of one embodiment of the invention.Please refer to Figure 17, at first, first clock, second clock, the 3rd clock and the 4th clock are provided, the frequency of each clock is identical, and second clock falls behind first clock, first preset phase, and the 3rd clock and the 4th clock fall behind first clock and second clock second preset phase respectively, and second preset phase is first preset phase half (as step 1702).Then, utilize first clock and second clock sampling digital signal respectively, and all with the rising edge of first clock and second clock or falling edge as the sampling edge, wherein, the bit length of digital signal equates (as step 1704) with the clock cycle of first clock, second clock, the 3rd clock and the 4th clock.Then, judge the positions of data state switching points (as step 1706) of digital signal according to the sampling result of first clock and second clock.Then, select with the 3rd clock or the 4th clock as preferable sampling clock (as step 1708) according to judged result.Then, utilize preferable sampling clock sampling digital signal, wherein, the sampling edge of preferable sampling clock identical with the sampling edge of first clock (as step 1710).

Indulge the above, the present invention is because of providing four frequencies identical, but has the sampling clock that out of phase postpones, and second clock wherein falls behind first clock, first preset phase, the 3rd clock and the 4th clock then fall behind first clock and second clock second preset phase respectively, and second preset phase is half of first preset phase.Then, utilize first clock and second clock to judge the data state switching points position of digital signal, and select the sampling edge in the middle of the 3rd clock and the 4th clock and be used as preferable sampling clock near the clock of the position intermediate point of digital signal, to utilize the preferable sampling clock digital signal of taking a sample, improve the correctness of data sampling.Even, the present invention also can arrange in pairs or groups and utilize the skill of the time of delay of adjusting digital signal, so that the intermediate point of the position of digital signal is adjusted to the sampling edge of preferable sampling clock, or make the sampling edge of the preferable sampling clock of intermediate point convergence of the position of digital signal, further to improve the correctness of data sampling.

Claims

1. sampling method comprises:

One first clock, a second clock, one the 3rd clock and one the 4th clock are provided, the frequency of each clock is identical, and this second clock falls behind this first clock, one first preset phase, and the 3rd clock and the 4th clock fall behind this first clock and this second clock one second preset phase respectively, and this second preset phase be this first preset phase half;

Utilize this first clock and this second clock digital signal of taking a sample respectively, and all with the rising edge of this first clock and this second clock or falling edge as the sampling edge, wherein, the bit length of this digital signal equated with the clock cycle of this first clock, this second clock, the 3rd clock and the 4th clock;

Judge the positions of data state switching points of this digital signal according to the sampling result of this first clock and this second clock;

Select with the 3rd clock or the 4th clock as a preferable sampling clock according to judged result; And

Utilize this preferable sampling clock this digital signal of taking a sample, wherein, the sampling edge of this preferable sampling clock is identical with the sampling edge of this first clock.

2. sampling method as claimed in claim 1, wherein, the mode of judging the data state switching points position of this digital signal comprises that the data state switching points of judging this digital signal is before the sampling edge that is positioned at after the sampling edge of this first clock with this second clock, after the sampling edge of this second clock with the sampling edge of this first clock before, the sampling edge of this first clock or the sampling edge of this second clock, and after the data state switching points of judging this digital signal is positioned at the sampling edge of this first clock with the sampling edge of this second clock before the time, select the 4th clock as this preferable sampling clock; After the data state switching points of judging this digital signal is positioned at the sampling edge of this second clock with the sampling edge of this first clock before the time, select the 3rd clock as this preferable sampling clock; When the data state switching points of judging this digital signal is positioned at the sampling edge of the sampling edge of this first clock or this second clock, select this preferable sampling clock of the wherein arbitrary conduct of the 3rd clock and the 4th clock.

3. sampling method as claimed in claim 2 wherein, also comprises before the step of this digital signal utilizing this preferable sampling clock to take a sample:

Control the time of delay of this digital signal according to the residing position of the data state switching points of this digital signal, so that the intermediate point of the position of this digital signal is adjusted to the sampling edge of this preferable sampling clock, or make the sampling edge of this preferable sampling clock of intermediate point convergence of the position of this digital signal.

4. sampling method as claimed in claim 3, wherein, the mode of controlling the time of delay of this digital signal comprises that the data state switching points of judging this digital signal is before the sampling edge that is positioned at after the sampling edge of the 3rd clock with the 4th clock, still be positioned at after the sampling edge of the 4th clock before the sampling edge with the 3rd clock, when selecting the 3rd clock as this preferable sampling clock, and the data state switching points of judging this digital signal is before the sampling edge that is positioned at after the sampling edge of the 3rd clock with the 4th clock the time, increase the time of delay of this digital signal, when selecting the 3rd clock as this preferable sampling clock, and the data state switching points of judging this digital signal is before the sampling edge that is positioned at after the sampling edge of the 4th clock with the 3rd clock the time, reduce the time of delay of this digital signal, when selecting the 4th clock as this preferable sampling clock, and the data state switching points of judging this digital signal is before the sampling edge that is positioned at after the sampling edge of the 3rd clock with the 4th clock the time, reduce the time of delay of this digital signal, when selecting the 4th clock as this preferable sampling clock, and the data state switching points of judging this digital signal is before the sampling edge that is positioned at after the sampling edge of the 4th clock with the 3rd clock the time, increases the time of delay of this digital signal.

5. sampling method as claimed in claim 4, wherein, comprise the time of delay that increases or reduce this digital signal in the mode in a plurality of stages, wherein, the adjusting range of current stage is greater than the adjusting range of next stage, and the adjusting range in first stage is smaller or equal to 1/4th of the bit length of this digital signal.

6. sampling method as claimed in claim 1, it also comprises provides one the 5th clock, one the 6th clock, one the 7th clock and one the 8th clock, the 5th clock, the 6th clock, the frequency of the 7th clock and the 8th clock is identical with the frequency of this first clock, and the 5th clock, the 6th clock, the 7th clock and the 8th clock fall behind this first clock respectively, this second clock, the 3rd clock and the 4th clock 1 the 3rd preset phase, and the 3rd preset phase is this second preset phase half, and take a sample in this digital signal utilizing this preferable sampling clock, more will be different from this preferable sampling clock person in the middle of the 3rd clock and the 4th clock as a reference clock, and utilize this reference clock this digital signal of taking a sample, wherein, the sampling edge of this reference clock is identical with the sampling edge of this preferable sampling clock, and this sampling method also comprises the following steps:

Judge the positions of data state switching points of this digital signal according to the sampling result of this preferable sampling clock and this reference clock;

Select to differ one of them of two clocks of the 3rd preset phase as a best sampling clock according to judged result with this preferable sampling clock; And

Utilize this best sampling clock this digital signal of taking a sample, sampling edge that wherein should the best sampling clock is identical with the sampling edge of this preferable sampling clock.

7. sampling method as claimed in claim 6, wherein, the mode of judging the data state switching points position of this digital signal comprises that the data state switching points of judging this digital signal is before the sampling edge that is positioned at after the sampling edge of this preferable sampling clock with this reference clock, after the sampling edge of this reference clock with the sampling edge of this preferable sampling clock before, or the sampling edge of this reference clock, and when this preferable sampling clock of the 3rd clock conduct, and when the data state switching points of judging this digital signal is positioned at after the sampling edge of this preferable sampling clock before the sampling edge with this reference clock, select the 5th clock as this best sampling clock; When the 3rd clock as this preferable sampling clock, and the data state switching points of judging this digital signal selects the 7th clock as this best sampling clock when being positioned at after the sampling edge of this reference clock with the sampling edge of this preferable sampling clock before; When the 3rd clock as this preferable sampling clock, and the data state switching points of judging this digital signal selects the 5th clock and the 7th clock wherein arbitrary as this best sampling clock when being positioned at the sampling edge of this reference clock; When the 4th clock as this preferable sampling clock, and the data state switching points of judging this digital signal selects the 6th clock as this best sampling clock when being positioned at after the sampling edge of this preferable sampling clock with the sampling edge of this reference clock before; When the 4th clock as this preferable sampling clock, and the data state switching points of judging this digital signal selects the 8th clock as this best sampling clock when being positioned at after the sampling edge of this reference clock with the sampling edge of this preferable sampling clock before; When the 4th clock as this preferable sampling clock, and the data state switching points of judging this digital signal selects the 6th clock and the 8th clock wherein arbitrary as this best sampling clock when being positioned at the sampling edge of this reference clock.

8. data recovery circuit comprises:

One oversampling module, receive one first clock, one second clock, one the 3rd clock and one the 4th clock, the frequency of each clock is identical, and this second clock falls behind this first clock, one first preset phase, and the 3rd clock and the 4th clock fall behind this first clock and this second clock one second preset phase respectively, and this second preset phase is this first preset phase half, in between a first phase, this oversampling module is utilized this first clock and this second clock digital signal of taking a sample, and all with the rising edge of this first clock and this second clock or falling edge as the sampling edge, in a second phase, this oversampling module is utilized the 3rd clock and the 4th clock this digital signal of taking a sample, and the sampling edge of the 3rd clock and the 4th clock is identical with the sampling edge of this first clock, this oversampling module is converted to parallel data with sampling result, with output as this oversampling module, wherein, the bit length of this digital signal equated with the clock cycle of above-mentioned four clocks;

One time replacement module, the parallel data of being exported in order to synchronous this oversampling module is to produce a synchronous result; And

One clearance control module, in between this first phase, this clearance control module is judged the positions of data state switching points of this digital signal according to this synchronized result, select the 3rd clock or the 4th clock as a preferable sampling clock with the foundation judged result, and in this second phase, this clearance control module controls module of should resetting the time is selected by the synchronous concatenation data that this preferable sampling clock obtained, with the output as this data recovery circuit this time replacement module from this synchronized result.

9. data recovery circuit as claimed in claim 8, wherein, this oversampling module comprises:

One first multiplexer in order to receiving this first clock and the 3rd clock, and is exported this first clock and the 3rd clock respectively between this first phase and in this second phase;

One second multiplexer in order to receiving this second clock and the 4th clock, and is exported this second clock and the 4th clock respectively between this first phase and in this second phase; And

One oversampling circuit is in order to the clock that utilizes this first multiplexer and this second multiplexer to export this digital signal of taking a sample.

10. data recovery circuit as claimed in claim 8, wherein this clearance control module judges that the mode of the data state switching points position of this digital signal comprises that the data state switching points of judging this digital signal is before the sampling edge that is positioned at after the sampling edge of this first clock with this second clock, after the sampling edge of this second clock with the sampling edge of this first clock before, the sampling edge of this first clock or the sampling edge of this second clock, and when this clearance control module was judged after the data state switching points of this digital signal is positioned at the sampling edge of this first clock before the sampling edge with this second clock, this clearance control module selected the 4th clock as this preferable sampling clock; When this clearance control module was judged after the data state switching points of this digital signal is positioned at the sampling edge of this second clock before the sampling edge with this first clock, this clearance control module selected the 3rd clock as this preferable sampling clock; When this clearance control module judged that the data state switching points of this digital signal is positioned at the sampling edge of the sampling edge of this first clock or this second clock, this clearance control module was selected the 3rd clock and this preferable sampling clock of the wherein arbitrary conduct of the 4th clock.

11. data recovery circuit as claimed in claim 8, it also comprises a variable delay module, and this oversampling module more receives this digital signal by this variable delay module, this variable delay module is controlled the time of delay of this digital signal according to one first control signal, and in this second phase, this clearance control module more produces this first control signal according to the residing position of the data state switching points of this digital signal.

12. data recovery circuit as claimed in claim 11 wherein, utilizes delay scope that this first control signal can adjust smaller or equal to 1/4th of the bit length of this digital signal.

13. data recovery circuit as claimed in claim 12, wherein, this variable delay module is more controlled the time of delay of this digital signal according to one second control signal, the delay scope that the delay scope that this second control signal can be adjusted can be adjusted less than this first control signal, and in this second phase, this clearance control module more produces this second control signal according to the residing position of the data state switching points of this digital signal.

14. a data recovery circuit comprises:

One oversampling module, receive one first clock, one second clock, one the 3rd clock, one the 4th clock, one the 5th clock, one the 6th clock, one the 7th clock and one the 8th clock, the frequency of each clock is identical, and this second clock falls behind this first clock, one first preset phase, the 3rd clock and the 4th clock fall behind this first clock and this second clock one second preset phase respectively, and the 5th clock, the 6th clock, the 7th clock and the 8th clock fall behind this first clock respectively, this second clock, the 3rd clock and the 4th clock 1 the 3rd preset phase, and this second preset phase is this first preset phase half, and the 3rd preset phase is this second preset phase half, in between a first phase, this oversampling module is utilized this first clock and this second clock digital signal of taking a sample, and all with the rising edge of this first clock and this second clock or falling edge as the sampling edge, in a second phase, this oversampling module is utilized the 3rd clock and the 4th clock this digital signal of taking a sample, and the sampling edge of the 3rd clock and the 4th clock is identical with the sampling edge of this first clock, in between a third phase, this oversampling module is utilized the 5th clock and the 6th clock this digital signal of taking a sample, or utilize the 7th clock and the 8th clock this digital signal of taking a sample, the 5th clock, the 6th clock, the sampling edge of the 7th clock and the 8th clock is identical with the sampling edge of this first clock, and this oversampling module is converted to parallel data with sampling result, with output as this oversampling module, wherein, the bit length of this digital signal equated with the clock cycle of above-mentioned eight clocks;

One clearance control module, in between this first phase, this clearance control module is judged the positions of data state switching points of this digital signal according to this synchronized result, select the 3rd clock or the 4th clock as a preferable sampling clock with the foundation judged result, in this second phase, this clearance control module is judged the positions of data state switching points of this digital signal according to this synchronized result, and select to differ one of them of two clocks of the 3rd preset phase as a best sampling clock with this preferable sampling clock according to judged result, in between this third phase, this oversampling module of this clearance control module controls is selected this best sampling clock and is taken a sample with the clock that this best sampling clock differs this first preset phase, and control this time replacement module, make this time replacement module from this synchronized result, select the synchronous concatenation data that obtained by this best sampling clock, with output as this data recovery circuit.

15. data recovery circuit as claimed in claim 14, wherein, this oversampling module comprises:

One first multiplexer, in order to receive this first clock, the 3rd clock, the 5th clock and the 7th clock, and between this first phase and in this second phase, export this first clock and the 3rd clock respectively, and between this third phase, this first multiplexer is subjected to this clearance control module controls, to select this best sampling clock or be used as output with clock that this best sampling clock differs this first preset phase in the middle of the 5th clock and the 7th clock;

One second multiplexer, in order to receive this second clock, the 4th clock, the 6th clock and the 8th clock, and between this first phase and in this second phase, export this second clock and the 4th clock respectively, and between this third phase, this second multiplexer is subjected to this clearance control module controls, is used as output with the clock of selecting output with this first multiplexer to differ this first preset phase in the middle of the 6th clock and the 8th clock; And

16. data recovery circuit as claimed in claim 14, it also comprises a variable delay module, and this oversampling module more receives this digital signal by this variable delay module, this variable delay module is controlled the time of delay of this digital signal according to one first control signal, and between this third phase, this clearance control module more produces this first control signal according to the residing position of the data state switching points of this digital signal.

17. data recovery circuit as claimed in claim 16 wherein, utilizes delay scope that this first control signal can adjust smaller or equal to 1/8th of the bit length of this digital signal.

18. data recovery circuit as claimed in claim 17, wherein, this variable delay module is more controlled the time of delay of this digital signal according to one second control signal, the delay scope that the delay scope that this second control signal can be adjusted can be adjusted less than this first control signal, and between this third phase, this clearance control module more produces this second control signal according to the residing position of the data state switching points of this digital signal.