CN106470346A - There are transport stream processor and the timing alignment apparatus and method of timing alignment functionality - Google Patents
There are transport stream processor and the timing alignment apparatus and method of timing alignment functionality Download PDFInfo
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- CN106470346A CN106470346A CN201510506974.1A CN201510506974A CN106470346A CN 106470346 A CN106470346 A CN 106470346A CN 201510506974 A CN201510506974 A CN 201510506974A CN 106470346 A CN106470346 A CN 106470346A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/242—Synchronization processes, e.g. processing of PCR [Program Clock References]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The present invention discloses a kind of timing alignment device, and for calibrating a clock signal of a transport stream and the sequential relationship of one first signal, one embodiment comprises：One input, for receiving this clock signal via a seasonal pulse transmission path, and receives this first signal via a first path；And an aligner.Described aligner comprises：One first sample circuit, for sampling this first signal according to this clock signal, thereby produces one first sampling result；One control circuit, for comprise this first signal in this first sampling result transform strike slip boundary when judge that this first sampling result is effective；And a first edge adjustment circuit, for adjust according to this when this first sampling result is effective the transform strike slip boundary of this clock signal and the transform strike slip boundary of this first signal one of them to meet a default sequential relationship.
Description
Technical field
The present invention is with regard to transport stream processor and timing alignment apparatus and method, especially with respect to can calibrate transmission
The transport stream processor of sequential of stream and timing alignment apparatus and method.
Background technology
In general, a signal processor is when receipt signal, sampled signal need to be carried out according to suitable seasonal pulse, thereby
The content of recovering signal.For example, processing digital video broadcast (Digital Video Broadcasting, DVB)
Transport stream (Transport Stream, TS) when, a transport stream processor can according in this transport stream seasonal pulse believe
Number sampling the many pen data signal in this transport stream, to reduce the content of this transport stream, however, due to this seasonal pulse
The transmission path of signal is different from the transmission path of every this data signal, therefore received by transport stream processor
Clock signal and data signal be likely to be out of synchronization so that transport stream processor cannot correctly sampled data signal, make
The content becoming reduced is wrong.
Content of the invention
In view of the deficiency of prior art, it is an object of the present invention to provide transport stream processor and timing alignment
Apparatus and method, to improve prior art.
The present invention discloses a kind of transport stream processor with timing alignment functionality, in order to process a transport stream, this biography
Defeated stream includes a clock signal and many data signals, and this transport stream processor comprises：One input；One aligner；
And a processing unit.Described input receives this clock signal and these data signals via multipath respectively.Institute
State aligner to comprise：Many sample circuits, for according to this clock signal these data signals separately sampled, to produce
Many sampling results；Whether one control circuit, in order to comprise its corresponding data signal according to these sampling results respectively
Transform strike slip boundary, judge the effectiveness of these sampling results；And multiple edge adjustment circuit, it is used to these samplings
When result is effective, adjust the transform strike slip boundary of these data signals respectively, make the conversion of these data signals after adjustment
Edge meets a default sequential relationship with the transform strike slip boundary of this clock signal.After described processing unit is in order to self-adjusting
Recognize a header of a packet data in these data signals, and determine this packet data according to the information of this header
Via one of them output of a message outgoing route, an image output path and data output paths.
The present invention separately discloses a kind of timing alignment device, can be applied to aforementioned transmission stream handle, for calibrating one
One clock signal of transport stream and the sequential relationship of one first signal.One embodiment of this timing alignment device comprises：
One input, for receiving this clock signal via a seasonal pulse transmission path, and via a first path receive this
One signal；And an aligner.Described aligner comprises：One first sample circuit, for according to this clock signal
Sample this first signal, thereby produce one first sampling result；One control circuit, in this first sampling result
Judge during the transform strike slip boundary comprising this first signal that this first sampling result is effective；And a first edge adjustment circuit,
It is used for adjusting the transform strike slip boundary of this clock signal and turning of this first signal when this first sampling result is effective according to this
Change sides edge one of them to meet a default sequential relationship.
The present invention accordingly discloses a kind of time sequence calibration method, for calibrating a clock signal and of a transport stream
The sequential relationship of the first signal, one embodiment comprises the steps of：Receive this seasonal pulse via a seasonal pulse transmission path
Signal, and receive this first signal multiple path reception one transport stream via a first path, this transport stream packets contains one
Clock signal and many pen data signal, this many pen data signal packet contain one first signal, this clock signal be via
One seasonal pulse path is received, and this first signal is to be received via a first path；And a calibration steps, it is used for
Calibrate the relation of this clock signal and this first signal.Described calibration steps comprises：Should according to the sampling of this clock signal
First signal, thereby produces one first sampling result；Comprise the conversion side of this first signal in this first sampling result
Judge during edge that this first sampling result is effective；And adjust this clock signal according to this when this first sampling result is effective
At least one of the transform strike slip boundary of transform strike slip boundary and this first signal preset sequential to meet a preset relation
Relation..
Feature for the present invention, implementation and effect, hereby coordinate accompanying drawing to make preferred embodiment detailed description as follows.
Brief description
Fig. 1 is the schematic diagram of an embodiment of timing alignment device of the present invention；
Fig. 2 is the schematic diagram of an embodiment of the first sample circuit of Fig. 1；
Fig. 3 is the schematic diagram of an embodiment of first edge adjustment circuit of Fig. 1；
Fig. 4 is the schematic diagram of another embodiment of aligner of Fig. 1；
The first edge adjustment circuit for Fig. 1 for the Fig. 5 adjusts an enforcement of the edge relation of clock signal and the first signal
The schematic diagram of example；
Fig. 6 is the schematic diagram of the another embodiment of aligner of Fig. 1；
Fig. 7 is the schematic diagram of an embodiment of first phase adjustment circuit of Fig. 6；
Fig. 8 is the schematic diagram of an embodiment of the transport stream processor of timing alignment device comprising Fig. 1；And
Fig. 9 is the schematic diagram of an embodiment of time sequence calibration method of the present invention.
Symbol description
100：Timing alignment device
110：Input
120：Aligner
122：First sample circuit
124：Control circuit
126：First edge adjustment circuit
CLK：Clock signal
D1：First signal
D1_Out：The first signal after calibration
D2：Secondary signal
S1：First sampling result
210：Latch unit
D1(0D)：Undelayed first signal
D1(1D)：It is delayed by the first signal of a unit
D1((N-1)D)：It is delayed by first signal of (N-1) individual unit
310：Delay cell
320、SEL：Select control unit
330：Multiplexer
Ctrl_CLK：Trigger
Shift_Ctrl_Reg：Edge adjusts signal
410：Second sample circuit
420：Second edge adjustment circuit
S2：Second sampling result
610：First phase adjustment circuit
710：Delay cell
720、SEL：Select control unit
730：Multiplexer
Phase_Ctrl_Reg：Phase adjustment signal
800：Transport stream processor
810：Input
820：Timing alignment device
830：Processing unit
832：Header detection module
834：PID judge module
842：Message outgoing route
844：Image output path
846：Data output paths
S910～S920：Step
Specific embodiment
Present invention is disclosed timing alignment device, transport stream processor and time sequence calibration method, can calibrate by not
Relation between the clock signal being transmitted with path and data signal.
Refer to Fig. 1, it is the schematic diagram of an embodiment of the timing alignment device of the present invention, as shown in figure 1,
Timing alignment device 100 comprises：One input 110；With an aligner 120.Described input 110 is, for example,
Multiple pins (Pin), for receiving a transport stream (Transport Stream, TS), this transmission via multiple paths
The stream e.g. transport stream of digital video broadcast (Digital Video Broadcasting, DVB) or other meet
The transport stream of MPEG-2 specification, comprises a clock signal CLK and many pen data signal, these data signals
Comprise one first signal D1 and secondary signal D2, when this input 110 receives via a seasonal pulse transmission path
Arteries and veins signal CLK, via one first path receive the first signal D1 and via one second path receive second letter
Number D2.Described aligner 120 is used for calibrating clock signal CLK and the relation of the first signal D1, and exports school
Signal (the first signal D1_Out after for example calibrating) after standard is for actual sampling or follow-up adjustment (such as phase
Position adjustment), and be optionally used for calibrating clock signal CLK and other data signal (such as secondary signals
D2 relation), aligner 120 comprises：One first sample circuit 122；One control circuit 124；And one
One edge adjustment circuit 126.
From the above, the first sample circuit 122 is used for sampling the first signal D1 according to clock signal CLK, thereby
Produce one first sampling result S1 and analyze for control circuit 124, an enforcement of the first sample circuit 122 is for example
Shown in Fig. 2, comprise N number of latch unit 210, this N number of latch unit 210 by signal transmission order be respectively intended to according to
Sample undelayed first signal D1 (0D), be delayed by the first signal of a unit according to clock signal CLK
D1 (1D) ..., be delayed by the first signal D1 ((N-1) D) of (N-1) individual unit, thereby produce the first sampling result
S1 comprises the sampled data of the parallel output of N pen, and wherein N is the integer more than 1, and numerical value can be by implementer according to need
Ask decision, postpones signal D1 (0D) to D1 ((N-1) D) can be produced by known or designed, designed delay circuit.
Described control circuit 124 is, for example, processor or the circuit of the logical judgment needed for executable the present embodiment, in
First sampling result S1 comprises the transform strike slip boundary (Transition Edge) (that is, 0 to 1 or 1 of the first signal D1
Level to 0 changes edge) when judge the first sampling result S1 effectively (effective first sampling result S1 be for example
Sampling value 0000111111 or 1111000000 for ten bits), if the first sampling result S1 is invalid (invalid
First sampling result S1 is, for example, that all sampling values are 1 or are 0 result), then control circuit 124 makes
First sample circuit 122 again sub-sampling the first signal D1 to produce the first new sampling result S1, until first
Till sampling result S1 is effective.Described first edge adjustment circuit 126 is used for effective in the first sampling result S1
When adjustment clock signal CLK the transform strike slip boundary of transform strike slip boundary and the first signal D1 one of to meet one
Default sequential relationship.
One embodiment of first edge adjustment circuit 126 is as shown in figure 3, comprise M delay cell 310, M
Individual selection control unit 320 (reference numerals are SEL) and M multiplexer 330, each delay cell 310 can
Postpone a delay unit, for postponing the first signal D1 of one or more units, institute according to input signal output
State M and select control unit 320 for trigger Ctrl_CLK (its frequency according to control circuit 120
It is equal to the frequency of clock signal CLK) make M multiplexer with M edge adjustment signal Shift_Ctrl_Reg
330 each output does not postpone or postpones the first signal D1 of one or more units, and wherein M is more than 1
Integer (for example M value is equal to aforesaid N value), for example, when M is that 3,3 edges adjust signal
Shift_Ctrl_Reg be 011, then receive 0 first multiplexer 330 export undelayed first signal D1,
Second multiplexer 330 receiving 1 exports the first signal D1 postponing a unit and the receive 1 the 3rd
Individual multiplexer 330 output postpones the first signal D1_Out as final output for the first signal D1 of two units
For actual sampling or other adjustment (such as phase adjustment).In one embodiment, these delay cells 310 are also
May be used to produce postpones signal D1 (0D) needed for the first sample circuit 122 to D1 ((N-1) D).
From the above, if aligner 120 is also used for calibrating the relation of clock signal CLK and secondary signal D2,
Then aligner 120 comprises as shown in Figure 4 further：One second sample circuit 410 is used for according to clock signal CLK
Sampling secondary signal D2 is to produce one second sampling result S2；Control circuit 124 is used in the second sampling result
Judge during the transform strike slip boundary that S2 comprises secondary signal D2 that the second sampling result S2 is effective；And one second edge adjust
Whole circuit 420 is used for adjusting the transform strike slip boundary and second of clock signal CLK when the second sampling result S2 is effective
One of them of the transform strike slip boundary of signal D2 is to meet this default sequential relationship, and exports the signal (example after calibration
Secondary signal D2_Out as after calibration) for actual sampling or follow-up adjustment (such as phase adjustment).Due to
Two sample circuits 410 are identical respectively with second edge adjustment circuit 420 or are equivalent to the first sample circuit 122 and
One edge adjustment circuit 126, the explanation here of redundancy and repetition gives memorandum.Clock signal CLK and other numbers
It is believed that number the adjustment of relation can be by that analogy.
Refer to Fig. 5, it is first edge adjustment circuit 126 adjustment clock signal CLK and the first signal D1
An embodiment of edge relation schematic diagram, as shown in figure 5, in the range of one (as shown in dash-dot lines in fig. 5),
Clock signal CLK before adjustment is not lined up with the edge of the first signal D1, the clock signal CLK after adjustment with
The edge of the first signal D1 near or alignment, now aforementioned default sequential relationship refer to the edge of binary signal near or
Alignment, so this not implements to limit, and the visual demand of implementer makes the edge of binary signal meet a particular kind of relationship.
It is contemplated that clock signal CLK still needs for sampling other data signals in the present embodiment, therefore first edge is adjusted
Whole circuit 126 preferentially adjusts the transform strike slip boundary of this first signal, and the visual demand of right implementer determines whichever to be adjusted,
And disclosure under this invention can learn how accordingly to adjust embodiments of the invention.If in addition, seasonal pulse letter
As the foundation of sampled data, then first edge adjustment circuit 126 is by the first signal D1 for the rising edge of number CLK
Transform strike slip boundary adjust near or alignment clock signal CLK falling edge to meet this default sequential relationship (such as
Shown in the dotted arrow of Fig. 5), thereby the rising edge of clock signal CLK can be close or alignment the first signal D1
The centre of two level constant intervals, to improve the tolerance to sampling skew；And if the decline of clock signal CLK
Edge will adjust the transform strike slip boundary of the first signal D1 as the foundation of sampled data, then first edge adjustment circuit 126
Adjust to close or alignment clock signal CLK rising edge, but as long as being embodied as possibility, the visual demand of implementer
Determine regulation rule.
Referring again to Fig. 1, control circuit 124 is after first edge adjustment circuit 126 completes edge adjustment, optional
The occurrence number of a special value is counted to selecting property according further to these data signals, and in this special value
Occurrence number meets a pre-conditioned season aligner 120 and stops calibrating the pass of this clock signal and this first signal
System, wherein this pre-conditioned optionally with frequency dependence, for example this is pre-conditioned can be in the scheduled time
This occurrence number between or be not less than a preset range.For example, the transport stream that input 110 is received is in solid
Determining deviation will transmit a synchronizing information, and this synchronizing information is a special value, pre- in one by count synchronization information
This occurrence number in fixing time, you can judge that carried out edge regulates whether correctly to these data signals.
From the above, if count value is not up to this preset number, (in other words the occurrence number of special value does not meet this
Pre-conditioned), represent calibration and do not complete, then control circuit 124 optionally makes aligner 120 adjustment first
The phase place of signal D1, now aligner 120 is as shown in fig. 6, comprise further：One first phase adjustment circuit
610, for the first signal being exported in the control lower adjustment first edge adjustment circuit 126 of control circuit 124
The phase place of D1 (claiming D1_Out afterwards), and the first signal D1_Out after output adjustment.First phase adjustment electricity
One embodiment on road 610 is as shown in fig. 7, comprise：X delay cell 710, X selection control unit 720
(reference numerals be SEL) and X multiplexer 730, often this delay cell 710 e.g. latch unit, for according to
Export the first signal D1_Out postponing one or more units according to clock signal CLK, described X selects to control
Unit 720 is used for trigger Ctrl_CLK and X phase adjustment signal according to control circuit 120
Phase_Ctrl_Reg makes each output of X multiplexer 730 not postpone or postpone the first of one or more units
Signal D1_Out, wherein X are positive integer, for example, when X is 3,3 phase adjustment signals
Phase_Ctrl_Reg is 010, then first multiplexer 730 receiving 0 exports undelayed first signal
D1_Out (i.e. the first signal D1_Out is without any delay cell 710), receive 1 second multiplexer
(i.e. the first signal D1_Out is through a delay cell for first signal D1_Out of 730 output one unit of delay
710) and receive 0 the 3rd multiplexer 730 output and postpone the first signal D1_Out of a unit (i.e.
The first signal D1_Out that second multiplexer 730 is exported) as final output the first signal D1_Out
For actual sampling or other adjustment (such as phase adjustment).Similarly, in phase-adjusting circuit 610 adjustment the
After the phase place of one signal D1_Out, control circuit 124 can count this special value according to these data signals again
Occurrence number, and in this special value occurrence number meet this pre-conditioned season aligner 120 stop calibration
Clock signal CLK and the relation of the first signal D1；Or in this special value occurrence number do not meet this preset
Condition season aligner 120 adjusts the first signal D1_Out's that first edge adjustment circuit 126 is exported again
Phase place.
Referring again to Fig. 1, aligner 120 can further include：One switch (not shown), for according to control
The control enable of circuit 124 and forbidden energy the first sample circuit 122.For example, this switch is located at clock signal
Between the source of CLK and the first sample circuit 122, when control circuit 124 makes switch conduction, the first sampling
Circuit 122 side can be sampled according to this；After completing to sample for calibrating or completing calibration, control circuit 124
Switch is made to be not turned on, thereby forbidden energy the first sample circuit 122, now control circuit 124 and first edge adjustment electricity
Running can be continued to maintain calibration effect in road 126.In addition, control circuit 124 can be according to preset rules from these
In data signal select one of them as the first signal D1 and/or select from remaining data signal wherein it
One as secondary signal D2, and similar signal behavior can be by that analogy.
Can be applicable to a transport stream processor based on front taking off timing alignment device, the present invention accordingly discloses a kind of tool
There is the transport stream processor of timing alignment functionality, one embodiment is as shown in Figure 8.Transport stream for example comes from one
Ground digital video broadcast (Digital Video Broadcasting-Terrestrial, DVB-T) device transport stream or
Other audio-visual transmission streams, comprise the multiple packages continuously transmitting in transport stream, the type of package comprises image data envelope
Bag, message data packet and message packet (such as captions, programme information etc.).Each package has a header
(Header), comprise package identification information (Packet Identifier (PID)) in header, in order to identify the type of package.
Transport stream processor 800 comprises：One input 810, an aligner 820 and a processing unit 830.Input
End 810 to receive transport stream through multiple signal paths, the transport stream packets being received contain a road clock signal CLK,
Eight circuit-switched data signal D1 to D8, a road useful signal Valid and road synchronizing signal Sync, in transport stream
The packet data system of each package is scattered in data signal D1 to D8.Aligner 820 comprise eight sample circuits,
One control circuit and eight edge adjustment circuits.These sample circuits are used for according to the separately sampled data of clock signal
Signal D1 to D8, to produce eight sampling results.Respectively according to these sampling results whether control circuit in order to
Comprise the transform strike slip boundary of its corresponding data signal, judge the effectiveness of these sampling results.These edges adjustment electricity
Road be used to these sampling results effective when, adjust the transform strike slip boundary of these data signals respectively, make this after adjustment
The transform strike slip boundary of a little data signals and the transform strike slip boundary of this clock signal meet a default sequential relationship.Aligner 820
In calibration process, more can judge calibration knot using the special value corresponding to synchronizing signal Sync in transport stream
Whether fruit is correct.For example, when useful signal Valid is 1 and synchronizing signal Sync is 1, control electricity
Road can determine whether whether the contained data of data signal D1 to D8 is equal to 16 carry value 0x47 (i.e. binary values
01000111, here is as aforementioned special value), if then increasing by a count value, if otherwise keeping count value not
Become, within certain time or signal period number, if count value reaches a preset number (in other words the going out of special value
Occurrence number meets that this is pre-conditioned, and such as correlated frequency (this occurrence number in the scheduled time) boundary is in 1/189
To between 1/193), represent calibration and complete, then control circuit makes aligner 820 stop calibration.Additionally, calibration
Device 820 can further include eight phase-adjusting circuits, lowers these edges of warping for the control in control circuit
The phase place of the data signal D1 to D8 after adjustment circuit adjustment, when the occurrence number of this special value does not meet this
When pre-conditioned, control circuit makes these phase-adjusting circuits enter horizontal phasing control to data signal D1 to D8.
Each sample circuit in this, the running of control unit, each edge adjustment circuit and each phase-adjusting circuit,
Effect is taken off as described in embodiment with implementing change front.After aligner 820 completes the timing alignment of transport stream, be by
Transport stream after calibration exports to processing unit 830.Processing unit 830 comprises a header detection module 832 and
PID judge module 834.Header detection module 832 is in order to recognize from the data signal D1 to D8 of transport stream
One header of one packet data.In enforcement, header detection module 832 can comprise comparator, is used for comparing data letter
Whether the data in number D1 to D8 meets the specific identification code of known flow header or rises and open code, if comparing knot
Fruit meets, that is, represent and find header.When header detection module 832 picks out the header of a packet data,
PID judge module 834 the package identification information (PID) from header can judge the type of this packet data.When
Packet data be message data when, PID judge module 834 will packet data via a message outgoing route 842
Output；When packet data is for image data, PID judge module 834 will packet data via an image output
Path 844 exports；When packet data is for information data, PID judge module 834 will packet data via one
Information output path 846 exports.
In addition to aforesaid timing alignment device, the present invention separately discloses a kind of time sequence calibration method, as shown in figure 9, should
One embodiment of method comprises the steps of：
Step S910：Receive a transport stream via multiple paths, this transport stream packets contains a clock signal and many
Data signal, these data signals comprise one first signal, and this clock signal is to be received via a seasonal pulse path,
This first signal is to be received via a first path.This step can be by the input 110 of Fig. 1 or its equivalent circuit
To execute.
Step S920：One calibration steps, for calibrating the relation of this clock signal and this first signal, comprises：
Sample this first signal according to this clock signal, thereby produce one first sampling result；In this first sampling result bag
Judge that this first sampling result is effective during transform strike slip boundary containing this first signal；And it is effective in this first sampling result
When adjust according to this transform strike slip boundary of this clock signal and the transform strike slip boundary of this first signal one of them to meet one
Default sequential relationship.This step can be executed by the aligner 120 of Fig. 1 or its equivalent circuit.
In sum, the timing alignment apparatus and method of the present invention can improve because transmission path difference led to when
Arteries and veins signal and the nonsynchronous problem of data signal, thus the problems such as avoid missampling.
Although embodiments of the invention are as described above, but those embodiments are not used for limiting the present invention, this technology
Field has usually intellectual and according to the content expressed or imply of the present invention, the technical characteristic of the present invention can be imposed
Change, all this kind change all may belong to the patent protection category sought by the present invention, in other words, the present invention's
Scope of patent protection should be defined by tbe claims and be defined.
Claims (17)
1. a kind of transport stream processor with timing alignment functionality, in order to process a transport stream, this transport stream packets
Include a clock signal and many data signals, it comprises：
One input, receives this clock signal and these data signals via multipath respectively；
One aligner, comprises：
Many sample circuits, for according to this clock signal these data signals separately sampled, to produce many sampling results；
Whether one control circuit, in order to comprise the conversion side of its corresponding data signal respectively according to these sampling results
Edge, judges the effectiveness of these sampling results；And
Multiple edge adjustment circuit, be used to these sampling results effective when, adjust the conversion of these data signals respectively
Edge, when making the transform strike slip boundary of these data signals after adjustment preset with the transform strike slip boundary satisfaction one of this clock signal
Order relation；And
One processing unit, in order to recognize a header of a packet data in these data signals after self-adjusting, and according to
Determine this packet data via a message outgoing route, an image output path and a number according to the information of this header
According to one of them output of outgoing route.
2. transport stream processor as claimed in claim 1 is it is characterised in that this control circuit is also according to adjustment
These data signals afterwards count the occurrence number of a special value, and the occurrence number in this special value meets one
Pre-conditioned this aligner of season stops calibration.
3. transport stream processor as claimed in claim 1 is it is characterised in that this aligner comprises further：
Leggy adjustment circuit, for the phase of these data signals controlling after lower these adjustment of adjustment in this control circuit
Position；When the occurrence number of this special value do not meet this pre-conditioned when, this control circuit makes these phase adjustments electricity
Horizontal phasing control is entered on road.
4. a kind of timing alignment device, for calibrating a clock signal of a transport stream and the sequential of one first signal
Relation, it comprises：
One input, for receiving this clock signal via a seasonal pulse transmission path, and receives via a first path
This first signal；And
One aligner, comprises：
One first sample circuit, for sampling this first signal according to this clock signal, thereby produces one first sampling
Result；
One control circuit, for comprise this first signal in this first sampling result transform strike slip boundary when judge this first
Sampling result is effective；And
One first edge adjustment circuit, for adjusting turning of this clock signal according to this when this first sampling result is effective
Change sides edge and this first signal transform strike slip boundary one of them to meet a default sequential relationship.
5. timing alignment device as claimed in claim 4 is it is characterised in that this first edge adjustment circuit is used
To adjust the transform strike slip boundary of this first signal when this first sampling result is effective so that it aligns or close to this seasonal pulse
The transform strike slip boundary of signal and meet this default sequential relationship.
6. timing alignment device as claimed in claim 4 it is characterised in that this transport stream packets contain most it is believed that
Number, this first signal is one of these data signals, and this control circuit completes in this first edge adjustment circuit
After edge adjustment, to count the occurrence number of a special value according further to these data signals, and specific in this
The occurrence number of numerical value meets pre-conditioned this aligner of season and stops calibrating this clock signal and this first signal
Relation.
7. timing alignment device as claimed in claim 4 it is characterised in that this transport stream packets contain most it is believed that
Number, this first signal is one of these data signals, and this control circuit completes in this first edge adjustment circuit
After edge adjustment, to count the occurrence number of a special value according further to these data signals, and specific in this
The occurrence number of numerical value is not inconsistent the phase place that unification this aligner of pre-conditioned season adjusts this first signal.
8. timing alignment device as claimed in claim 7 is it is characterised in that this aligner comprises further：
One first phase adjustment circuit, in the phase place controlling lower this first signal of adjustment of this control circuit.
9. timing alignment device as claimed in claim 8 is it is characterised in that this control circuit is adjusted in this phase place
After the phase place of this first signal of whole the regulation of electrical circuit, to count going out of given period numerical value according further to these data signals
Occurrence number, and the occurrence number in this special value meets this pre-conditioned season this aligner stopping this seasonal pulse of calibration
Signal and the relation of this first signal.
10. timing alignment device as claimed in claim 4 is it is characterised in that this aligner comprises further：
One switch, for this first sample circuit of control enable according to this control circuit.
11. timing alignment devices as claimed in claim 4 it is characterised in that this transport stream packets contain most it is believed that
Number, this first signal is one of these data signals, and these data signals also comprise a secondary signal, and should
Aligner comprises further：
One second sample circuit, for sampling this secondary signal according to this clock signal, thereby produces one second sampling
Result；And
One second edge adjustment circuit, for when this control circuit judges that this second sampling result adjusts this when effective
One of them of the transform strike slip boundary of arteries and veins signal and the transform strike slip boundary of this secondary signal is to meet this default sequential relationship.
12. timing alignment devices as claimed in claim 11 are it is characterised in that this control circuit is pre- according to one
If rule selects one of them as this first signal from these data signals, then select from remaining data signal
Select one of them as this secondary signal.
A kind of 13. time sequence calibration method, for calibrating the sequential of one of transport stream clock signal and one first signal
Relation, it comprises the steps of：
Receive this clock signal via a seasonal pulse transmission path, and receive this first signal via a first path；
Sample this first signal according to this clock signal, thereby produce one first sampling result；
Judge that this first sampling result is effective when the transform strike slip boundary that this first sampling result comprises this first signal；With
And
The transform strike slip boundary of this clock signal and turning of this first signal is adjusted according to this when this first sampling result is effective
Change sides edge one of them to meet a default sequential relationship.
14. time sequence calibration method as claimed in claim 13 are it is characterised in that adjust turning of this clock signal
One of them of transform strike slip boundary of edge and this first signal of changing sides is adjustment to meet the step of this default sequential relationship
The transform strike slip boundary of this first signal, makes the transform strike slip boundary of the first signal align or the transform strike slip boundary close to this clock signal.
15. time sequence calibration method as claimed in claim 13, wherein this transport stream packets contain many data signals, should
First signal is one of these data signals, and this time sequence calibration method comprises further：
It is somebody's turn to do with meeting in adjusting one of them that the transform strike slip boundary of this clock signal is with the transform strike slip boundary of this first signal
The occurrence number of a special value after default sequential relationship, is counted according to these data signals, and specific in this
The occurrence number of numerical value meet one pre-conditioned when stop calibrating the relation of this clock signal and this first signal.
16. time sequence calibration method as claimed in claim 15 are it is characterised in that work as the appearance of this special value
Number of times is not inconsistent the phase place adjusting this first signal when unifying pre-conditioned.
17. time sequence calibration method as claimed in claim 13 are it is characterised in that this transport stream packets contains many data
Signal, this first signal is one of these data signals, and these data signals comprise a secondary signal, and should
Time sequence calibration method comprises further：
Sample this secondary signal according to this clock signal, thereby produce one second sampling result；
Judge that this second sampling result is effective when the transform strike slip boundary that this second sampling result comprises this secondary signal；With
And
The transform strike slip boundary of this clock signal and the conversion side of this secondary signal is adjusted when this second sampling result is effective
One of them of edge is to meet this default sequential relationship.
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