CN106470346A - Transmission stream processor with time sequence calibration function and time sequence calibration device and method - Google Patents

Abstract

The invention discloses a timing calibration device for calibrating the timing relationship between a clock signal and a first signal of a transmission stream, one embodiment of the invention comprises: an input end for receiving the clock signal via a clock transmission path and receiving the first signal via a first path; and a calibrator. The calibrator includes: a first sampling circuit for sampling the first signal according to the clock signal to generate a first sampling result; a control circuit for determining that the first sampling result is valid when the first sampling result includes a transition edge of the first signal; and a first edge adjusting circuit for adjusting one of the transition edge of the clock signal and the transition edge of the first signal to satisfy a predetermined timing relationship when the first sampling result is valid.

Description

Transport stream processor with timing calibration function, timing calibration device and method

technical field

The invention relates to a transport stream processor and a timing calibration device and method, in particular to a transport stream processor capable of calibrating the timing of a transport stream, a timing calibration device and a method.

Background technique

Generally speaking, when a signal processor receives a signal, it needs to sample the signal according to an appropriate clock, so as to restore the content of the signal. For example, when processing a Transport Stream (TS) of Digital Video Broadcasting (DVB), a Transport Stream Processor will sample multiple signals in the Transport Stream according to the clock signal in the Transport Stream. However, since the transmission path of the clock signal is different from the transmission path of each data signal, the clock signal and the data signal received by the transport stream processor may not be the same Synchronization, so that the transport stream processor cannot correctly sample the data signal, resulting in incorrect restored content.

Contents of the invention

In view of the shortcomings of the prior art, an object of the present invention is to provide a transport stream processor and a timing calibration device and method to improve the prior art.

The present invention discloses a transport stream processor with a timing calibration function for processing a transport stream, the transport stream includes a clock signal and multiple data signals, the transport stream processor includes: an input terminal; a calibrator; and a processing unit. The input terminal respectively receives the clock signal and the data signals via multiple paths. The calibrator includes: a multi-sampling circuit, which is used to respectively sample these data signals according to the clock signal, so as to generate multi-sampling results; a control circuit, which is used to respectively determine whether the sampling results contain the transition edges of the corresponding data signals , to determine the validity of these sampling results; and a multi-edge adjustment circuit, used to adjust the conversion edges of these data signals respectively when these sampling results are valid, so that the adjusted conversion edges of these data signals and the conversion of the clock signal The edges satisfy a predetermined timing relationship. The processing unit is used to identify a header of a packet data from the adjusted data signals, and decide to pass the packet data through an audio output path, an image output path and a data output path according to the information of the header. One of them is output.

The present invention further discloses a timing calibration device, which can be applied to the aforementioned transport stream processor, and is used for calibrating the timing relationship between a clock signal and a first signal of a transport stream. An embodiment of the timing calibration device includes: an input terminal for receiving the clock signal via a clock transmission path and receiving the first signal via a first path; and a calibrator. The calibrator includes: a first sampling circuit, used to sample the first signal according to the clock signal, thereby generating a first sampling result; a control circuit, used to include the first sampling result in the first sampling result When the transition edge of the signal determines that the first sampling result is valid; and a first edge adjustment circuit is used to adjust the transition edge of the clock signal and the transition edge of the first signal when the first sampling result is valid. One of them satisfies a predetermined timing relationship.

The present invention correspondingly discloses a timing calibration method for calibrating the timing relationship between a clock signal and a first signal of a transport stream. An embodiment thereof includes the following steps: receiving the clock signal via a clock transmission path, and receive the first signal through a first path and receive a transport stream through a plurality of paths, the transport stream includes a clock signal and multiple data signals, the multiple data signals include a first signal, and the clock signal is passed through a clock signal The first signal is received by a pulse path, and the first signal is received through a first path; and a calibration step is used to calibrate the relationship between the clock signal and the first signal. The calibration step includes: sampling the first signal according to the clock signal, thereby generating a first sampling result; determining that the first sampling result is valid when the first sampling result includes a transition edge of the first signal; and When the first sampling result is valid, at least one of the transition edge of the clock signal and the transition edge of the first signal is adjusted to satisfy a preset timing relationship. .

Regarding the characteristics, implementation and effects of the present invention, preferred embodiments are described in detail below in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of an embodiment of a timing calibration device of the present invention;

FIG. 2 is a schematic diagram of an embodiment of the first sampling circuit of FIG. 1;

FIG. 3 is a schematic diagram of an embodiment of the first edge adjustment circuit in FIG. 1;

Fig. 4 is the schematic diagram of another embodiment of the calibrator of Fig. 1;

FIG. 5 is a schematic diagram of an embodiment in which the first edge adjustment circuit in FIG. 1 adjusts the edge relationship between the clock signal and the first signal;

Fig. 6 is the schematic diagram of another embodiment of the calibrator of Fig. 1;

FIG. 7 is a schematic diagram of an embodiment of the first phase adjustment circuit in FIG. 6;

FIG. 8 is a schematic diagram of an embodiment of a transport stream processor including the timing alignment device of FIG. 1; and

FIG. 9 is a schematic diagram of an embodiment of the timing calibration method of the present invention.

Symbol Description

100: timing calibration device

110: input terminal

120: calibrator

122: The first sampling circuit

124: Control circuit

126: First edge adjustment circuit

CLK: clock signal

D1: first signal

D1_Out: the first signal after calibration

D2: second signal

S1: first sampling result

210: Latch

D1(0D): first signal without delay

D1(1D): the first signal delayed by one unit

D1((N-1)D): the first signal delayed by (N-1) units

310: delay unit

320, SEL: select control unit

330: Multiplexer

Ctrl_CLK: trigger signal

Shift_Ctrl_Reg: edge adjustment signal

410: Second sampling circuit

420: second edge adjustment circuit

S2: second sampling result

610: first phase adjustment circuit

710: delay unit

720, SEL: select control unit

730: Multiplexer

Phase_Ctrl_Reg: phase adjustment signal

800: transport stream processor

810: input terminal

820: Timing Calibration Device

830: processing unit

832: Header detection module

834: PID judgment module

842: Audio output path

844: Image output path

846: Data output path

S910～S920: steps

detailed description

The invention discloses a timing calibration device, a transmission stream processor and a timing calibration method, capable of calibrating the relationship between clock signals and data signals transmitted by different paths.

Please refer to FIG. 1 , which is a schematic diagram of an embodiment of a timing calibration device of the present invention. As shown in FIG. 1 , the timing calibration device 100 includes: an input terminal 110 ; and a calibrator 120 . The input terminal 110 is, for example, a plurality of pins (Pins), and is used to receive a transport stream (Transport Stream, TS) through multiple paths, and the transport stream is, for example, a digital video broadcasting (Digital Video Broadcasting, DVB) transport stream Or other transport streams conforming to the MPEG-2 specification, including a clock signal CLK and multiple data signals, these data signals include a first signal D1 and a second signal D2, the input terminal 110 receives the clock through a clock transmission path The signal CLK receives the first signal D1 through a first path, and receives the second signal D2 through a second path. The calibrator 120 is used to calibrate the relationship between the clock signal CLK and the first signal D1, and output the calibrated signal (such as the calibrated first signal D1_Out) for actual sampling or subsequent adjustment (such as phase adjustment), and Can be selectively used to calibrate the relationship between the clock signal CLK and other data signals (such as the second signal D2), the calibrator 120 includes: a first sampling circuit 122; a control circuit 124; and a first edge adjustment circuit 126 .

As mentioned above, the first sampling circuit 122 is used to sample the first signal D1 according to the clock signal CLK, thereby generating a first sampling result S1 for analysis by the control circuit 124. An embodiment of the first sampling circuit 122 is shown in FIG. 2 As shown, N latches 210 are included, and the N latches 210 are respectively used to sample the first signal D1 (0D) without delay and the first signal delayed by one unit according to the clock signal CLK according to the signal transmission sequence. D1(1D), ..., the first signal D1((N-1)D) delayed by (N-1) units, thereby generating the first sampling result S1 includes N parallel output sampling data, where N is An integer greater than 1, the value can be determined by the implementer according to requirements, and the delay signals D1(0D) to D1((N-1)D) can be generated by a known or self-designed delay circuit. The control circuit 124 is, for example, a processor or a circuit that can execute the logic judgment required by this embodiment, and is used to include the transition edge (Transition Edge) of the first signal D1 in the first sampling result S1 (that is, 0 to 1 or 1 to 0 level change edge), it is determined that the first sampling result S1 is valid (the valid first sampling result S1 is, for example, ten-bit sampling value 0000111111 or 1111000000), if the first sampling result S1 is invalid (invalid first sampling The result S1 is, for example, the result that all sampled values are 1 or 0), then the control circuit 124 makes the first sampling circuit 122 re-sample the first signal D1 to generate a new first sampling result S1 until the first sampling result S1 until valid. The first edge adjustment circuit 126 is used for adjusting one of the transition edge of the clock signal CLK and the transition edge of the first signal D1 to satisfy a preset timing relationship when the first sampling result S1 is valid.

An embodiment of the first edge adjustment circuit 126, as shown in FIG. One delay unit is used to output the first signal D1 delayed by one or more units according to the input signal, and the M selection control units 320 are used for a trigger signal Ctrl_CLK (whose frequency is equal to the clock signal CLK) of the control circuit 120 Frequency) and M edge adjustment signals Shift_Ctrl_Reg make each output of M multiplexers 330 undelayed or delayed by one or more units of the first signal D1, wherein M is an integer greater than 1 (for example, the M value is equal to the aforementioned N value), for example, when M is 3, and the three edge adjustment signals Shift_Ctrl_Reg are 011, then the first multiplexer 330 that receives 0 outputs the undelayed first signal D1, and the second multiplexer 330 that receives 1 The multiplexer 330 outputs the first signal D1 delayed by one unit, and the third multiplexer 330 that receives 1 outputs the first signal D1 delayed by two units as the final output first signal D1_Out for actual sampling or Other adjustments (such as phase adjustments). In an embodiment, the delay units 310 can also be used to generate the delayed signals D1 (0D) to D1 ((N−1)D) required by the first sampling circuit 122 .

As mentioned above, if the calibrator 120 is also used to calibrate the relationship between the clock signal CLK and the second signal D2, the calibrator 120 further includes as shown in FIG. Sampling the second signal D2 to generate a second sampling result S2; the control circuit 124 is used to determine that the second sampling result S2 is valid when the second sampling result S2 includes a transition edge of the second signal D2; and a second edge adjustment circuit 420 It is used to adjust one of the transition edge of the clock signal CLK and the transition edge of the second signal D2 to meet the preset timing relationship when the second sampling result S2 is valid, and output a calibrated signal (for example, the calibrated first The second signal D2_Out) is used for actual sampling or subsequent adjustment (such as phase adjustment). Since the second sampling circuit 410 and the second edge adjustment circuit 420 are the same or equivalent to the first sampling circuit 122 and the first edge adjustment circuit 126 respectively, redundant and repeated descriptions are omitted here. The adjustment of the relationship between the clock signal CLK and other data signals can be deduced by analogy.

Please refer to FIG. 5, which is a schematic diagram of an embodiment in which the first edge adjustment circuit 126 adjusts the edge relationship between the clock signal CLK and the first signal D1. As shown in FIG. shown), the clock signal CLK before adjustment is not aligned with the edge of the first signal D1, and the adjusted clock signal CLK is close to or aligned with the edge of the first signal D1. At this time, the aforementioned preset timing relationship refers to the The edges are close to or aligned, but this is not an implementation limitation, and the implementer can make the edges of the two signals conform to a specific relationship according to requirements. In this embodiment, considering that the clock signal CLK still needs to be used to sample other data signals, the first edge adjustment circuit 126 first adjusts the conversion edge of the first signal, but the implementer can decide which one to adjust according to the needs, and can Based on the disclosure of the present invention, it is understood how to adjust the embodiments of the present invention accordingly. In addition, if the rising edge of the clock signal CLK is used as the basis for sampling data, the first edge adjustment circuit 126 adjusts the transition edge of the first signal D1 to be close to or aligned with the falling edge of the clock signal CLK to meet the preset timing. relationship (as shown by the dotted arrow in FIG. 5 ), whereby the rising edge of the clock signal CLK can be close to or aligned with the middle of the two-level change interval of the first signal D1, so as to improve the tolerance to sampling offset; and if The falling edge of the clock signal CLK is used as the basis for sampling data, and the first edge adjustment circuit 126 adjusts the transition edge of the first signal D1 to be close to or aligned with the rising edge of the clock signal CLK, but as long as it is possible to implement, implement The operator can decide to adjust the rules according to the needs.

Please refer to FIG. 1 again, after the first edge adjustment circuit 126 completes the edge adjustment, the control circuit 124 can optionally further count the number of occurrences of a specific value according to these data signals, and when the number of occurrences of the specific value matches a The preset condition causes the calibrator 120 to stop calibrating the relationship between the clock signal and the first signal, wherein the preset condition can be selectively related to frequency, for example, the preset condition can be that the number of occurrences within a predetermined time is between Or not less than a predetermined range. For example, the transmission stream received by the input terminal 110 will transmit a synchronization information at a fixed interval, and the synchronization information is a specific value. By counting the number of occurrences of the synchronization information within a predetermined time, it can be judged whether the data is correct or not. Whether the edge adjustment of the signal is correct.

As mentioned above, if the count value does not reach the preset number (in other words, the number of occurrences of a specific value does not meet the preset condition), it means that the calibration is not completed, and the control circuit 124 can selectively make the calibrator 120 adjust the first signal The phase of D1, at this moment calibrator 120 as shown in Figure 6, further comprises: a first phase adjustment circuit 610, is used for adjusting the first signal D1 ( hereinafter referred to as the phase of D1_Out), and output the adjusted first signal D1_Out. An embodiment of the first phase adjustment circuit 610, as shown in FIG. It is a latch, which is used to output the first signal D1_Out delayed by one or more units according to the clock signal CLK, and the X selection control units 720 are used to adjust the signal Phase_Ctrl_Reg according to the trigger signal Ctrl_CLK of the control circuit 120 and the X phase adjustment signals Let each of the X multiplexers 730 output the first signal D1_Out that is not delayed or delayed by one or more units, where X is a positive integer, for example, when X is 3, the 3 phase adjustment signals Phase_Ctrl_Reg are 010, Then the first multiplexer 730 that receives 0 outputs the undelayed first signal D1_Out (that is, the first signal D1_Out does not pass through any delay unit 710), and the second multiplexer 730 that receives 1 outputs a delayed one-unit The first signal D1_Out (that is, the first signal D1_Out passes through a delay unit 710), and the third multiplexer 730 that receives 0 outputs the first signal D1_Out delayed by one unit (that is, the output of the second multiplexer 730 The first signal D1_Out) is used as the final output first signal D1_Out for actual sampling or other adjustments (such as phase adjustment). Similarly, after the phase adjustment circuit 610 adjusts the phase of the first signal D1_Out, the control circuit 124 can count the number of occurrences of the specific value according to these data signals, and calibrate when the number of occurrences of the specific value meets the preset condition. The calibrator 120 stops calibrating the relationship between the clock signal CLK and the first signal D1; or the calibrator 120 adjusts the first signal D1_Out output by the first edge adjustment circuit 126 again when the number of occurrences of the specific value does not meet the preset condition. phase.

Please refer to FIG. 1 again, the calibrator 120 may further include: a switch (not shown) for enabling and disabling the first sampling circuit 122 according to the control of the control circuit 124 . For example, the switch is located between the source of the clock signal CLK and the first sampling circuit 122. When the control circuit 124 turns on the switch, the first sampling circuit 122 can perform sampling accordingly; when the sampling is completed for calibration Or after the calibration is completed, the control circuit 124 makes the switch non-conductive, thereby disabling the first sampling circuit 122 , at this time the control circuit 124 and the first edge adjustment circuit 126 can continue to operate to maintain the calibration effect. In addition, the control circuit 124 can select one of these data signals as the first signal D1 and/or select one of the other data signals as the second signal D2 according to a preset rule, similar signal selection And so on.

Based on the fact that the aforementioned timing calibration device can be applied to a transport stream processor, the present invention correspondingly discloses a transport stream processor with a timing calibration function, an embodiment of which is shown in FIG. 8 . The transport stream is, for example, a transport stream from a terrestrial digital video broadcasting (Digital Video Broadcasting-Terrestrial, DVB-T) device or other video and audio transport streams. The transport stream includes multiple packets transmitted continuously, and the types of packets include image data packets. , audio data packets, and information packets (such as subtitles, program information, etc.). Each packet has a header (Header), which contains packet identification information (Packet Identifier (PID)) for identifying the type of the packet. The transport stream processor 800 includes: an input terminal 810 , a calibrator 820 and a processing unit 830 . The input terminal 810 receives the transport stream through multiple signal paths. The received transport stream includes one clock signal CLK, eight data signals D1 to D8, one valid signal Valid and one synchronous signal Sync. Each packet in the transport stream Packet data is distributed among data signals D1 to D8. The calibrator 820 includes eight sampling circuits, a control circuit, and eight edge adjustment circuits. These sampling circuits are used to respectively sample the data signals D1 to D8 according to the clock signal to generate eight sampling results. The control circuit is used for determining the validity of the sampling results respectively according to whether the sampling results contain transition edges of the corresponding data signals. The edge adjustment circuits are used to respectively adjust the transition edges of the data signals when the sampling results are valid, so that the adjusted transition edges of the data signals and the clock signal satisfy a preset timing relationship. During the calibration process, the calibrator 820 can further use the specific value corresponding to the synchronization signal Sync in the transport stream to determine whether the calibration result is correct. For example, when the valid signal Valid is 1 and the synchronous signal Sync is 1, the control circuit can determine whether the data contained in the data signals D1 to D8 is equal to the hexadecimal value 0x47 (that is, the binary value 01000111, here as the aforementioned specific value ), if so, increase a count value, otherwise keep the count value unchanged, within a certain time or number of signal cycles, if the count value reaches a preset number (in other words, the number of occurrences of a specific value satisfies the preset condition, such as the relevant frequency (the number of occurrences within a predetermined time period) is between 1/189 and 1/193), which means that the calibration is completed, and the control circuit makes the calibrator 820 stop the calibration. In addition, the calibrator 820 may further include eight phase adjustment circuits, which are used to adjust the phases of the data signals D1 to D8 adjusted by these edge adjustment circuits under the control of the control circuit. When the condition is set, the control circuit makes these phase adjustment circuits adjust the phases of the data signals D1 to D8. In this example, the operation, functions and implementation changes of each sampling circuit, control unit, each edge adjustment circuit and each phase adjustment circuit are as described in the previous embodiments. After the calibrator 820 completes the timing calibration of the transport stream, it outputs the calibrated transport stream to the processing unit 830 . The processing unit 830 includes a header detection module 832 and a PID determination module 834 . The header detection module 832 is used for identifying a header of a packet of data from the data signals D1 to D8 of the transport stream. In practice, the header detection module 832 may include a comparator for comparing whether the data in the data signals D1 to D8 conform to a specific identification code or a start code of a known packet header. If the comparison result is consistent, it means that a Header. When the header detecting module 832 identifies the header of a packet of data, the PID judging module 834 can judge the type of the packet data from the packet identification information (PID) in the header. When the package data is audio data, the PID judging module 834 is about to output the package data through an audio output path 842; when the package data is image data, the PID judgment module 834 is about to output the package data through an image output path 844; when the package data is For information data, the PID judging module 834 is about to output the packet data through an information output path 846 .

In addition to the aforementioned timing calibration device, the present invention discloses another timing calibration method, as shown in FIG. 9 , an embodiment of the method includes the following steps:

Step S910: Receive a transport stream through multiple paths, the transport stream includes a clock signal and a plurality of data signals, the data signals include a first signal, the clock signal is received through a clock path, the first signal is received via a first path. This step can be performed by the input terminal 110 in FIG. 1 or its equivalent circuit.

Step S920: a calibration step for calibrating the relationship between the clock signal and the first signal, including: sampling the first signal according to the clock signal, thereby generating a first sampling result; determining that the first sampling result is valid when the transition edge of the first signal is included; and adjusting one of the transition edge of the clock signal and the transition edge of the first signal to satisfy A preset timing relationship. This step can be performed by the calibrator 120 in FIG. 1 or its equivalent circuit.

To sum up, the timing calibration device and method of the present invention can improve the problem of asynchronous clock signal and data signal caused by different transmission paths, thereby avoiding problems such as sampling errors.

Although the embodiments of the present invention are as described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make changes to the technical characteristics of the present invention according to the explicit or implicit content of the present invention. All these changes may belong to the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention should be defined by the claims.

Claims (17)

1. A transport stream processor with a timing alignment function, used for processing a transport stream, the transport stream includes a clock signal and multiple data signals, comprising: an input terminal, respectively receiving the clock signal and the data signals through multiple paths; A calibrator, comprising: A multi-sampling circuit is used to respectively sample these data signals according to the clock signal to generate multi-sampled results; a control circuit for determining the validity of the sampling results respectively according to whether the sampling results contain transition edges of their corresponding data signals; and The multi-edge adjustment circuit is used to adjust the transition edges of these data signals respectively when the sampling results are valid, so that the adjusted transition edges of these data signals and the transition edges of the clock signal satisfy a preset timing relationship; and A processing unit, used for identifying a header of a packet of data from the adjusted data signals, and deciding to pass the packet of data through an audio output path, an image output path, and a data output path according to the information of the header One of them is output. 2. The transport stream processor according to claim 1, wherein the control circuit also counts the number of occurrences of a specific value according to the adjusted data signals, and when the number of occurrences of the specific value matches a preset condition to stop the calibrator from calibrating. 3. The transport stream processor according to claim 1, wherein the calibrator further comprises: a multi-phase adjustment circuit, which is used to adjust the phases of the adjusted data signals under the control of the control circuit; When the number of occurrences of the specific value does not meet the preset condition, the control circuit makes the phase adjustment circuits perform phase adjustment. 4. A timing calibration device for calibrating the timing relationship between a clock signal of a transport stream and a first signal, comprising: an input terminal for receiving the clock signal via a clock transmission path and receiving the first signal via a first path; and A calibrator, comprising: a first sampling circuit, used for sampling the first signal according to the clock signal, thereby generating a first sampling result; a control circuit for determining that the first sampling result is valid when the first sampling result includes a transition edge of the first signal; and A first edge adjustment circuit is used to adjust one of the transition edge of the clock signal and the transition edge of the first signal to satisfy a preset timing relationship when the first sampling result is valid. 5. The timing calibration device according to claim 4, wherein the first edge adjustment circuit is used to adjust the transition edge of the first signal to be aligned with or close to the clock when the first sampling result is valid The transition edge of the signal satisfies the preset timing relationship. 6. The timing calibration device as claimed in claim 4, wherein the transport stream includes multiple data signals, the first signal is one of the data signals, and the control circuit performs edge adjustment on the first edge adjustment circuit Afterwards, further counting the occurrence times of a specific value according to the data signals, and instructing the calibrator to stop calibrating the relationship between the clock signal and the first signal when the occurrence times of the specific value meet a preset condition. 7. The timing calibration device according to claim 4, wherein the transport stream includes multiple data signals, the first signal is one of the data signals, and the control circuit performs edge adjustment on the first edge adjustment circuit Afterwards, further counting the occurrence times of a specific value according to the data signals, and instructing the calibrator to adjust the phase of the first signal when the occurrence times of the specific value do not meet a preset condition. 8. The timing calibration device according to claim 7, wherein the calibrator further comprises: a first phase adjustment circuit for adjusting the phase of the first signal under the control of the control circuit. 9. The timing calibration device according to claim 8, wherein the control circuit further counts the number of occurrences of a specific period value according to the data signals after the phase adjustment circuit adjusts the phase of the first signal, and then When the occurrence times of the specific value meet the preset condition, the calibrator stops calibrating the relationship between the clock signal and the first signal. 10. The timing calibration device according to claim 4, wherein the calibrator further comprises: a switch for enabling the first sampling circuit according to the control of the control circuit. 11. The timing calibration device according to claim 4, wherein the transport stream includes multiple data signals, the first signal is one of the data signals, and the data signals further include a second signal, and the calibration The implementer further includes: a second sampling circuit, used for sampling the second signal according to the clock signal, thereby generating a second sampling result; and A second edge adjustment circuit is used to adjust one of the transition edge of the clock signal and the transition edge of the second signal to meet the preset timing relationship when the control circuit determines that the second sampling result is valid. 12. The timing calibration device according to claim 11, wherein the control circuit selects one of the data signals as the first signal according to a preset rule, and then selects one of the other data signals One of them is used as the second signal. 13. A timing calibration method for calibrating the timing relationship between a clock signal of a transport stream and a first signal, comprising the following steps: receiving the clock signal via a clock transmission path, and receiving the first signal via a first path; sampling the first signal according to the clock signal, thereby generating a first sampling result; determining that the first sampling result is valid when the first sampling result includes a transition edge of the first signal; and When the first sampling result is valid, one of the transition edge of the clock signal and the transition edge of the first signal is adjusted accordingly to satisfy a preset timing relationship. 14. The timing calibration method according to claim 13, wherein the step of adjusting one of the transition edge of the clock signal and the transition edge of the first signal to meet the preset timing relationship is to adjust the second The transition edge of a signal is aligned with or close to the transition edge of the clock signal. 15. The timing calibration method according to claim 13, wherein the transport stream comprises multiple data signals, the first signal is one of the data signals, the timing calibration method further comprises: After adjusting one of the transition edge of the clock signal and the transition edge of the first signal to meet the preset timing relationship, count the number of occurrences of a specific value according to the data signals, and count the occurrence times of the specific value Stop calibrating the relationship between the clock signal and the first signal when the number of occurrences meets a preset condition. 16. The timing calibration method according to claim 15, wherein the phase of the first signal is adjusted when the number of occurrences of the specific value does not meet a preset condition. 17. The timing alignment method according to claim 13, wherein the transport stream includes multiple data signals, the first signal is one of the data signals, the data signals include a second signal, and the timing alignment The method further includes: sampling the second signal according to the clock signal, thereby generating a second sampling result; determining that the second sampling result is valid when the second sampling result includes a transition edge of the second signal; and One of the transition edge of the clock signal and the transition edge of the second signal is adjusted to satisfy the preset timing relationship when the second sampling result is valid.