CN101674175A - Burst clock utilizing phase selecting technology and data recovery circuit - Google Patents
Burst clock utilizing phase selecting technology and data recovery circuit Download PDFInfo
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- CN101674175A CN101674175A CN 200810215373 CN200810215373A CN101674175A CN 101674175 A CN101674175 A CN 101674175A CN 200810215373 CN200810215373 CN 200810215373 CN 200810215373 A CN200810215373 A CN 200810215373A CN 101674175 A CN101674175 A CN 101674175A
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Abstract
The invention relates to a burst clock utilizing phase selecting technology and a data recovery circuit, comprising a phase-locked loop circuit, an over-sampling phase selecting circuit and a delay locking loop circuit, wherein the phase-locked loop circuit is used for providing multiple groups of fixed clock signals, and each clock signal has a clock phase. The over-sampling phase picking circuitis coupled to the phase-locked loop circuit and is used for detecting the data edge of the received date signals by utilizing the clock signals and select a to-be-locked clock phase according to theposition of the data edge. The delay locking loop circuit is coupled to the phase-locked loop circuit and the over-sampling phase selecting circuit and is used for comparing the data phase of the datasignal with the to-be-locked clock phase, thereby controlling the data phase of the data signal to be delayed by a delay time until the data phase is locked to the clock phase.
Description
Technical field
The present invention relates to a kind of burst type (Burst-mode, BM) clock and data recovery circuit that utilizes phase selecting technology.
Background technology
Along with the rise of broadband application, people are more and more higher for the demand of frequency range, and optical fiber can provide the frequency range of super large, and transmission quality is good and stable, is the final solution of broadband demand.Realize at present the most popular method of fiber-to-the-home be exactly passive optical network with low cost (Passive OpticalNetwork, PON).
Fig. 1 shows the schematic diagram of traditional passive optical network.Please refer to Fig. 1, passive optical network 100 is by an optical line terminal (Optical Line Termination, OLT) 110, Optical Distribution Network (Optical Distribution Network, ODN) 120, and a plurality of optical network units (OpticalNetwork Unit, ONU) 130 compositions.Optical line terminal 110 is mainly put at local side, can be connected to the network of outside, provide network service miscellaneous, for example internet, Digital Television, high definition television (High Definition TV, HDTV), the networking telephone (Voice over IP, VOIP) or the like.These services are broadcast to each optical network unit 130 by Optical Distribution Network 120, and the user just can capture the service that they want.
Optical Distribution Network 120 is made up of an optical fiber and an optical splitter (Optical Splitter), and optical splitter is a passive device, does not need power supply also not need personnel to safeguard.One end of optical splitter is connected to optical line terminal 110, and the other end then is connected to each optical network unit 130.The light signal that optical splitter can be sent optical line terminal 110 etc. is given each optical network unit that is connected to optical splitter 130, and the light signal that also optical network unit 130 can be uploaded simultaneously concentrates at same optical fiber, is sent to optical line terminal 110.Optical network unit 130 is put usually in the place near client, and along with the position difference of putting, can be divided into fiber-to-the-home (Fiber to the Home, FTTH), Fiber To The Building (Fibert othe Building, FTTB), that Fiber to the home is outer (Fiber to the Curb, FTTC) or the like.Want the information uploaded in case the user has, for example (File Transfer Protocol, FTP) file, video conference (video conference) or the like just can be by optical network unit 130 with data upload for file transfer protocol (FTP).
Because passive optical network is the framework of a point-to-multipoint (Point to Multi-Point), the data of uploading all can be concentrated at same optical fiber by optical splitter, so the data based standard that optical network unit will be uploaded is worked out (IEEE802.3ah, and ITU G..983/G.984) be with time division multiplexing (TimeDivision Multiplexing, TDM) mode transmits, optical network unit can only be uploaded data at the time slot that is assigned to by optical line terminal (time slot), and the data phase that each optical network unit is uploaded to optical line terminal is not quite similar.Because the mode of uploading the The data time division multiplexing of numerous clients is uploaded, and each user can use this single optical fiber channel in the time interval of oneself, thus each user can Data transmission time will significantly be shortened.In the case, if use traditional data recovery circuit to do the action of answer, will be long because of its locking and turnaround time, and the time that the user uploads data in the framework is shortened, thereby cause the waste of frequency range service efficiency.So for the action of the transfer of data of this burst type, optical line terminal must have the receiver of a burst type can be apace with the clock and the weakened phase restoring of receiving data, with the more efficient frequency range that utilizes.
Traditional continuous mode data recovery circuit can be divided into two classes substantially, and the first kind is the data recovery circuit based on the phase-locked loop.Fig. 2 shows the data recovery circuit schematic diagram of tradition based on the phase-locked loop.Please refer to Fig. 2, data recovery circuit 200 comprises phase-frequency detector 210, loop filter 220 and voltage-controlled oscillator (Voltage Control Oscillator, VCO) 230, and the lock mode of data recovery circuit 200 is to utilize clock that voltage-controlled oscillator 230 produced and input data to do comparison on phase place and the frequency, when phase place and difference on the frequency generation, controlling signal promptly can change the frequency of voltage-controlled oscillator 230; When the phase difference signal no longer occurred, data recovery circuit 200 promptly reached the stable state of locking.
Second class is called two circuit data recovery circuit.Fig. 3 shows traditional two circuit data recovery circuit schematic diagram.Please refer to Fig. 3, data recovery circuit 300 comprises phase-frequency detector 310, loop filter 320, voltage-controlled oscillator 330, phase detectors 340, loop filter 350 and voltage controlled delay line (Voltage Control Delay Line, VCDL) 360, and the lock mode of data recovery circuit 300 is the clock signal that utilizes the voltage-controlled oscillator 330 of the reference clock of an outside and top to be produced, next and input data are done the comparison on phase place and the frequency, use producing the delay-locked loop that a stable output clock is given the below.When data entered data recovery circuit 300, the clock signal of fixed frequency was done the comparison on the phase place therewith, and did not do the comparison on the frequency; When not having phase difference, delay-locked loop promptly reaches the stable state of locking.
Want to have the data recovery circuit of quick lock in characteristic, must utilize the phase selecting technology of sampling, crossing sampling promptly is to utilize one group of same frequency but clock signals having different phases, respectively the data state is done the action of sampling.Fig. 4 shows three times of schematic diagrames of crossing sampling of tradition.Please refer to Fig. 4, it comprises and utilizes three clock signals respectively the data state to be taken a sample, and therefore is called three times and crosses sampling.Wherein, utilize this three data modes that clock signal takes a sample out, adjacent in twos state is done mutual exclusion (XOR) computing, and, promptly can understand data edges actually between any two groups of adjacent clock signals through after the set of number circuit calculating ballot.
For instance, Fig. 5 shows the schematic diagram that conventional phase is chosen.Please refer to Fig. 5, because data edges appears at the centre of #0 and these two clock signals of #2, the clock signal that therefore can select #1 is as replying the clock signal that data are used.The above-mentioned sampling phase selecting circuit of crossing only utilizes just choosing of digital circuit can determine sampling clock, so is fit to be used in the application of quick lock in when doing the action that phase place chooses.Yet such framework still lacks the ability of eliminating phase error in the circuit, and when the shake of data increased, the situation that the phase place of being taken a sample just might make a mistake finally still can cause data to reply mistake.
Summary of the invention
The invention provides a kind of burst clock and data recovery circuit that utilizes phase selecting technology, in conjunction with the fast selecting characteristic of crossing sample circuit and the stability characteristic (quality) of delay-locked loop, to increase the speed and the stability of phase locking.
The present invention proposes a kind of burst clock and data recovery circuit that utilizes phase selecting technology, and it comprises phase-locked loop circuit, crosses sampling phase selecting circuit and delay locked loop circuit.Wherein, phase-locked loop circuit is in order to provide many groups fixing clock signal, and each clock signal has a clock phase place.Cross the sampling phase selecting circuit and be coupled to phase-locked loop circuit, detect the data edges of the data signals that is received in order to utilize these clock signals, and choose the clock phase of desire locking according to the position of this data edges.Delay locked loop circuit then is coupled to phase-locked loop circuit and crosses the sampling phase selecting circuit, in order to the data phase of comparing data signal and the clock phase of desire locking, and the data phase of control data signal postpones a time of delay, till data phase is locked to clock phase.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 shows the schematic diagram of traditional passive optical network.
Fig. 2 shows the data recovery circuit schematic diagram of traditional phase-locked loop for the basis.
Fig. 3 shows the schematic diagram of traditional two circuit data recovery circuit.
Fig. 4 is three times of schematic diagrames of crossing sampling that illustrate according to one embodiment of the invention.
Fig. 5 is the schematic diagram that the phase place that illustrates according to one embodiment of the invention is chosen.
Fig. 6 is the circuit working schematic diagram that illustrates according to one embodiment of the invention.
Fig. 7 is the calcspar of the data recovery circuit that illustrates according to one embodiment of the invention.
Fig. 8 is the clock signal that illustrates according to one embodiment of the invention and the phase relation schematic diagram and the clock figure of data signals.
Fig. 9 is the calcspar of crossing the sampling phase selecting circuit that illustrates according to one embodiment of the invention.
Figure 10 is the clock signal that illustrates according to one embodiment of the invention and the phase relation schematic diagram and the clock figure of data signals.
Figure 11 is the calcspar of the delay locked loop circuit that illustrates according to one embodiment of the invention.
Figure 12 is the calcspar of the data recovery circuit that illustrates according to one embodiment of the invention.
Figure 13 is the circuit diagram that the phase place that illustrates according to one embodiment of the invention is chosen control circuit and phase detectors.
The reference numeral explanation
100: passive optical network
110: optical line terminal
120: Optical Distribution Network
130: optical network unit
200,300,700,1100: data recovery circuit
210,310: phase-frequency detector
220,320,350,1252: loop filter
230,330: voltage-controlled oscillator
340: phase detectors
360: voltage controlled delay line
701,910,1110,1220: amplifying circuit
702,920,1120,1230: sample circuit
703,940,1140,1240: phase place is chosen control circuit
704,1150,1250: the delay-locked loop control circuit
710,930,1130,1210: phase-locked loop circuit
720,900: cross the sampling phase selecting circuit
730,1100: delay locked loop circuit
740,1270: decision circuit
1251: charge pump
1260: reset circuit
1271: multiplexer
1272: gate
The 1273:D D-flip flop
1310: the ballot circuit
1320: control circuit
1330: unlock circuit
Embodiment
The present invention is in conjunction with the advantage of crossing sampling phase selecting circuit and delay-locked loop, utilized the quick characteristic of sampling phase selecting circuit earlier, meet burst type (Burst-mode, BM) clock and data are replied (Clock and Data Recovery, CDR) requirement of circuit on speed, again in conjunction with delay-locked loop (Delay Locked Loop, stability characteristic (quality) DLL).Thus, data recovery circuit of the present invention not only has the ability of quick lock in, also can have the stability characteristic (quality) of delay-locked loop.In order to make content of the present invention more clear, below the example that can implement according to this really as the present invention especially exemplified by embodiment.
The present invention has disposed an action that delay locked loop circuit comes the data signal is done phase alignment in addition after crossing the sampling phase selecting circuit, to eliminate phase difference therebetween.Fig. 6 is the circuit working schematic diagram that illustrates according to one embodiment of the invention.Please refer to Fig. 6, after data signals enters data recovery circuit, cross the work that data edges that sampling phase selecting circuit 610 just can begin to look for data signals is chosen with excute phase.Behind the determination data marginal position, data recovery circuit then can be closed the work kenel of sampling phase selecting circuit 610, be transformed into a delay locked loop circuit 620, and data signals will direct and local clock signal after entering data recovery circuit be done the action of phase alignment.By the conversion of these two work kenels, can realize the burst clock and the data recovery circuit of quick lock in and tool stability characteristic (quality).
Fig. 7 is the calcspar of the data recovery circuit that illustrates according to one embodiment of the invention.Please refer to Fig. 7, the data recovery circuit 700 of present embodiment is by a phase-locked loop (Phase Locked Loop, PLL) circuit 710 produces a plurality of fixing clock signals, and offers the circuit use of below, and wherein each clock signal all has fixing clock phase.The circuit of below then can be divided into sampling phase selecting circuit 720 and 730 two parts of delay locked loop circuit are explained.
Crossing sampling phase selecting circuit 720 is that (Sampler) takes a sample to the state of data signal via sample circuit 702 by after the amplitude amplification of amplifying circuit 701 with data signals.Wherein, sample circuit 702 for example is the data signal to be carried out three times cross sampling, four times and cross sampling or other and cross sampling more than three times, and does not limit its scope.The sampling result of sample circuit 702 can be transferred to phase place and choose control circuit (Phase Selecting Control Circuit) 703 and do the judgement of data edges position, and choose the clock phase of delay locked loop circuit 730 required lockings, select as the loop of delay locked loop circuit 730 required uses.Above-mentioned amplifying circuit 701 comprises pre-amplifier (PreAmp) and voltage controlled delay line (Voltage Control Delay Line, VCDL), wherein pre-amplifier is the amplitude in order to the amplification data signal, and voltage controlled delay line then is the phase place in order to the delayed data signal.
730 of delay locked loop circuits are by amplifying circuit 701, sample circuit 702, and phase place is chosen the phase detectors that are selected in the control circuit 703, and (Phase Detector, PD), and delay-locked loop control circuit 704 is formed.Wherein, according to the phase place comparative result of phase detectors and digital circuit generation, by the time of delay of voltage controlled delay line in the delay-locked loop control circuit 704 control amplifying circuits 701, to reach the target of locking.At last, when the data phase of data signals aligns with clock phase, can will carry out the data signals output that phase place is adjusted by decision circuit (Decision Circuit) 740.Below be about to the action that phase place chooses and be called coarse adjustment, the action of phase locking is called fine setting, and respectively respectively detailed explanation is done in these two work again for an embodiment.
At the part of coarse adjustment action, Fig. 8 is the clock signal that illustrates according to one embodiment of the invention and phase relation schematic diagram and the clock figure of data signals, and Fig. 9 is the calcspar of the mistake sampling phase selecting circuit that illustrates according to one embodiment of the invention.Please also refer to Fig. 8 and Fig. 9, after data signals entered sampling phase selecting circuit 900, amplifying circuit 910 can first amplification data signal amplitude, then sample circuit 920 clock signal that can utilize phase-locked loop circuit 930 to be produced is done the action of sampling to the state of data signal.Then, phase place is chosen control circuit 940 and promptly can be come the judgment data edge can drop between which two clock signal according to the data mode of being taken a sample, and through after the ballot of some, can determine the interval of selecting.
As shown in Figure 8, present embodiment is sampled as example with four times of mistakes, and provides four groups to have clock signals having different phases PH0, PH90, PH180 and PH270 by phase-locked loop circuit 930.The tentation data edge appears between PH0 and two clock signals of PH90, and cross sampling phase selecting circuit 900 behind the position that has determined data edges, will select this clock signal of PH90 as the target of delay locked loop circuit institute desire with the data phase alignment.
In view of the above, in above-mentioned coarse adjustment process, cross the position at sampling phase selecting circuit 900 meeting determination data edges and the loop path of delay locked loop circuit, the clock phase of selected data phase place desire locking just.On the other hand, data signals can be done the action that amplitude amplifies through amplifying circuit 910 earlier after entering sampling phase selecting circuit 900, and this does not partly influence the action that phase place is selected.And the data after amplifying are taken a sample by the state of 920 pairs of data signals of sample circuit earlier, and after choosing control circuit 940 calculating sampling results by phase place, promptly finish the work that phase place is chosen.
At the part of trimming movement, Figure 10 is the clock signal that illustrates according to one embodiment of the invention and the phase relation schematic diagram and the clock figure of data signals, and Figure 11 is the calcspar of the delay locked loop circuit that illustrates according to one embodiment of the invention.Please also refer to Figure 10 and Figure 11, in the path of the selected delay-locked loop of decision, and and data phase do after the clock phase of lock out action, can carry out the action of phase alignment.
As shown in figure 10, when the position at judgment data edge is between PH0 and two clock signals of PH90 the time, can determine the clock phase as the locking of data phase desire with PH90, and when delay locked loop circuit 1100 begins to move, data phase then can the direction to PH90 slowly move, up to the phase alignment of PH90 till.In view of the above, can reach the purpose of phase locking.
In above-mentioned trim process, after entering delay locked loop circuit 1100, data signals does the action that amplitude amplifies through the pre-amplifier of amplifying circuit 1110 between meeting, and the clock signal that the data signals after amplifying can utilize phase-locked loop circuit 1130 to be produced by sample circuit 1120 is earlier taken a sample to it, and sampling result is transferred to phase place choose that phase detectors in the control circuit 1140 are done phase-lead or the comparison that falls behind, the action that it can determine delay-locked loop control circuit 1150 to carry out forward the voltage controlled delay line of amplifying circuit 1110 or postpone backward, the data phase of data signals can be adjusted to step by step with the clock phase of clock signal in view of the above and be alignd, till locking.
Figure 12 is the calcspar of the data recovery circuit that illustrates according to one embodiment of the invention.Please refer to Figure 12, present embodiment is introduced the data recovery circuit of Fig. 7 than the detail circuits framework.Wherein, data recovery circuit 1200 comprises that phase-locked loop circuit 1210, amplifying circuit 1220, sample circuit 1230, phase place choose control circuit 1240, delay-locked loop control circuit 1250, reset circuit 1260 and decision circuit 1270, and its function division is as follows:
Phase-locked loop circuit 1210 has fixing clock phase in order to provide many groups fixing clock signal (comprising PH0, PH90, PH180, PH270 and PHS0, PHS90, PHS180, PHS270) and respectively organize clock signal.1220 of amplifying circuits comprise pre-amplifier and voltage controlled delay line, and wherein pre-amplifier is in order to the amplitude of amplification data signal, and voltage controlled delay line then is the phase place in order to the delayed data signal.
Sample circuit 1230 is made up of 6 D flip-flops and synchronous circuit, it comprises and utilized clock signal PH0, PH90, PH180 and PH270 that phase-locked loop circuit 1210 provided and latter two clock signal PH180 ' of a last clock cycle and PH270 ' that the data signal is done sampling action, to detect its data edges, and the data sampling result then can send into the phase place of rear end and choose control circuit 1240 after synchronous through synchronous circuit.
Phase place is chosen control circuit 1240 meeting utilization phase detectors (Phase Detector wherein, PD) the sampled data signal is done comparison on the phase state, and selected near the clock phase of data edges target as delay locked loop circuit 1250 lockings.
In detail, phase place is chosen control circuit 1240 when synchrodata enters, can utilize the different clocks phase place to the data signal do sampling and synchronously after data result, with its output with as the differentiation on the data mode, if the difference on the state is arranged, promptly can instead push back in sample circuit 1230 clock to the sampling result of data, and find the position of data edges.
Phase place choose control circuit 1240 in fact when judging between phase region be utilize data sampling and synchronously after three the data sampling results in front and back do judgement on the data mode, if the state outcome of these two synchrodatas of PH0 and PH90 is not simultaneously, we promptly can instead push back clock signal when the data signal is done sampling, clk0 is different with the data mode that clk90 is sampled to, so data edges can occur between clk0 and the clk90.
1250 of delay locked loop circuits can utilize phase detectors that phase place chooses and be selected in the control circuit 1240 and clock signal to do comparison on the phase place, then the charge pump of control lag locked loop control circuit 1250 (Charge Pump, CP) 1251 provide electric current to loop filter (Loop Filter, LF) 1252 do the action of charge and discharge, and then change the control voltage of the voltage controlled delay line of amplifying circuit 1220.By continuous sampling, delay lock action, finally the data phase of data signals can be alignd with selected clock phase, and reach the target of phase locking.
Reset circuit 1260 comprises that being connected to phase place chooses charge pump 1251 in ballot circuit, unlock circuit and the delay locked loop circuit 1250 in the control circuit 1240, its work is for before data enter circuit, and the output state in will vote earlier circuit and the unlock circuit just begins to count after removing and wait pending data to import.Reset circuit 1260 can also return the accurate bit recovery of the output voltage of charge pump 1251 to default voltage simultaneously, and the wait controlling signal comes loop filter 1252 is done the action of charging or discharge.
1270 of decision circuit comprise the multiplexer 1271 and the gate 1272 in an output control time that can select to desire dateout, again via after D flip-flop 1273 samplings, data output are finished the action that clock and data are replied at last.
It should be noted that, in the framework of above-mentioned data recovery circuit 1200, crossing sampling phase selecting circuit and delay locked loop circuit has circuit element partly to overlap, and comprises that phase-locked loop circuit 1210, amplifying circuit 1220, sample circuit 1230 and phase place choose control circuit 1240.Difference was that the sampling phase selecting circuit only utilized the preamplifier in the amplifying circuit 1220 amplitude of data signals to be amplified the phase place that delay locked loop circuit then also utilizes the voltage controlled delay line in the amplifying circuit 1220 to come the delayed data signal in addition.
In addition, cross the sampling phase selecting circuit and utilize phase place to choose the phase detectors that control circuit 1240 is chosen required use in the delay locked loop circuit, also determined the clock phase of institute's desire locking, describe in detail for an embodiment again with next.
Figure 13 is the circuit diagram that the phase place that illustrates according to one embodiment of the invention is chosen control circuit and phase detectors.Please refer to Figure 13, when data recovery circuit also operated in the operating state that sampling phase chooses, phase place is chosen phase detectors PD1-PD4 in the control circuit 1300 respectively in order to detect the state of data signals, with the judgment data edge is to drop in the middle of which two clock signal, and via the ballot circuit 1310 come counts, after judging end, ballot circuit 1310 just can stop action.This moment, 1320 of control circuits can be controlled multiplexer MUX1 and MUX2 selects the phase detectors as required use in the delay-locked loop path from four phase detectors PD1-PD4.
After the state of unlock circuit 1330 was removed via reset circuit, unlock circuit 1330 promptly can begin to wait the pending data input.Data enter after the circuit, and unlock circuit 1330 can begin the enumeration data number, and after the data number of accumulative total reaches predefined dateout number, promptly produces a controlling signal, with the data output after replying.
And when data recovery circuit operates in the delay-locked loop pattern, selected phase detectors then can utilization itself characteristic to decide at present data mode through the clock sampling result be leading at present or lag behind the clock of desire locking, and the corresponding controlling signal of output is carried out the adjustment of time of delay for follow-up delay-locked loop control circuit (not shown).
In sum, in the burst clock and data recovery circuit that utilizes phase selecting technology of the present invention, utilize the sampling phase selecting circuit of crossing more than three times to come quick selected data phase bit position earlier, and the path of decision delay-locked loop, utilize delay-locked loop to do the action of phase locking again.Wherein, cross the quick characteristic conforms burst clock and the requirement of data recovery circuit on speed of sampling phase selecting circuit, the stability characteristic (quality) of delay-locked loop then can help accurately and the apace data phase of locking data signal of data recovery circuit.
Though the present invention discloses as above with preferred embodiment; but it is not in order to qualification the present invention, those skilled in the art, under the premise without departing from the spirit and scope of the present invention; when can doing some changes and modification, so protection scope of the present invention should be as the criterion with claim of the present invention.
Claims (14)
1. a burst clock and data recovery circuit that utilizes phase selecting technology comprises:
One phase-locked loop circuit, in order to provide many groups fixing clock signal, each described clock signal has a clock phase place;
One crosses the sampling phase selecting circuit, is coupled to this phase-locked loop circuit, detects a data edges of a data signals that is received in order to utilize described clock signal, and chooses this clock phase of desire locking according to the position of this data edges; And
One delay locked loop circuit, be coupled to this phase-locked loop circuit and this crosses the sampling phase selecting circuit, in order to a data phase of this data signals relatively and this clock phase of desire locking, and this data phase of controlling this data signals postpones a time of delay, till this data phase is locked to this clock phase.
2. burst clock and the data recovery circuit that utilizes phase selecting technology as claimed in claim 1 also comprises:
One decision circuit is coupled to this delay locked loop circuit, in order to according to this clock phase that this delay locked loop circuit locked, selects output this data signals corresponding to this clock phase.
3. burst clock and the data recovery circuit that utilizes phase selecting technology as claimed in claim 2, wherein this decision circuit comprises and choosing from this data edges this clock signal farthest, and uses this clock phase of this clock signal to export this data signals.
4. burst clock and the data recovery circuit that utilizes phase selecting technology as claimed in claim 1, wherein be somebody's turn to do the sampling phase selecting circuit and comprised:
One amplifying circuit is in order to amplify this data signals that is received;
One sample circuit is coupled to this amplifying circuit, in order to utilize a take a sample state of this data signals of described clock signal; And
One phase place is chosen control circuit, is coupled to this sample circuit, judges this data edges of this data signals in order to this state of taking a sample according to each described clock signal, and chooses this clock phase of the required locking of this delay locked loop circuit.
5. burst clock and the data recovery circuit that utilizes phase selecting technology as claimed in claim 4, wherein this sample circuit comprises:
A plurality of triggers, be coupled to respectively the output of this phase-locked loop circuit described clock signal one of them, and in order to this data signals is done sampling; And
One synchronous circuit is coupled to described trigger, in order to a sampling result of synchronous described trigger, and exports this sampling result to this phase place and chooses control circuit.
6. burst clock and the data recovery circuit that utilizes phase selecting technology as claimed in claim 4, wherein this phase place is chosen control circuit and is comprised:
A plurality of phase detectors, receive respectively this data signals and described clock signal one of them, be to drop between any two clock signals in order to this data edges of judging this data signals;
One ballot circuit is coupled to described phase detectors, drops on the number of times of this clock signal of each described phase detectors in order to this data edges of counting this data signals, and obtains voting results; And
One control circuit is coupled to this ballot circuit, in order to according to these voting results, select described phase detectors one of them as employed these phase detectors of this delay locked loop circuit.
7. burst clock and the data recovery circuit that utilizes phase selecting technology as claimed in claim 6, wherein this phase place is chosen control circuit and is also comprised:
One unlock circuit in order to receiving this data signals, and is counted the data number of this data signals, to produce a controlling signal, with the data output after replying.
8. burst clock and the data recovery circuit that utilizes phase selecting technology as claimed in claim 7, wherein be somebody's turn to do the sampling phase selecting circuit and also comprised:
One reset circuit, be coupled to this ballot circuit and this unlock circuit, remove in order to the output state of will vote circuit and this unlock circuit, and this ballot circuit and this unlock circuit just begin to count the number of times that this clock signal of each described phase detectors drops on this data edges of this data signals after the output state removing.
9. burst clock and the data recovery circuit that utilizes phase selecting technology as claimed in claim 4, wherein this phase place choose control circuit comprise choose from nearest two clock signals of this data edges one of them, and with this clock phase of this selected clock signal this clock phase as the required locking of this delay locked loop circuit.
10. burst clock and the data recovery circuit that utilizes phase selecting technology as claimed in claim 9, wherein this phase place is chosen control circuit and is comprised and choosing after this data edges, and from this nearest clock signal of this data edges.
11. burst clock and the data recovery circuit that utilizes phase selecting technology as claimed in claim 4, wherein this delay locked loop circuit comprises:
This amplifying circuit is in order to amplify this data signals that is received;
This sample circuit is coupled to this amplifying circuit, in order to utilize a take a sample state of this data signals of this selected clock signal;
One phase detectors are coupled to this sample circuit, in order to the comparison of this clock phase being done phase-lead or being fallen behind, and export a controlling signal; And
One delay-locked loop control circuit is coupled to this phase detectors, in order to control this amplifying circuit this time of delay to this data phase according to this controlling signal, till this data phase is locked to this clock phase.
12. burst clock and the data recovery circuit that utilizes phase selecting technology as claimed in claim 11, wherein this amplifying circuit comprises:
One pre-amplifier is in order to amplify this data signals that is received; And
One voltage controlled delay line is coupled to this pre-amplifier, postpones this time of delay in order to this data phase with this data signals.
13. burst clock and the data recovery circuit that utilizes phase selecting technology as claimed in claim 12, wherein this delay-locked loop control circuit comprises:
One charge pump is in order to provide an electric current according to this controlling signal; And
One loop filter is coupled to this charge pump, in order to receiving this electric current carrying out charge and discharge, and exports a control voltage to this voltage controlled delay line, to change this time of delay of this voltage controlled delay line.
14. burst clock and the data recovery circuit that utilizes phase selecting technology as claimed in claim 1 wherein was somebody's turn to do the sampling phase selecting circuit and comprised that this data signals is carried out three times took a sample or four times of samplings excessively excessively.
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| CN103684440A (en) * | 2012-09-04 | 2014-03-26 | 瑞昱半导体股份有限公司 | Clock and data recovery circuit and clock and data recovery |
| CN106470346A (en) * | 2015-08-18 | 2017-03-01 | 晨星半导体股份有限公司 | There are transport stream processor and the timing alignment apparatus and method of timing alignment functionality |
| CN108233871A (en) * | 2016-12-09 | 2018-06-29 | 格芯公司 | The digital frequency multiplier of local oscillator signal is generated in FDSOI technologies |
| WO2020186647A1 (en) * | 2019-03-20 | 2020-09-24 | Huawei Technologies Co., Ltd. | Improved burst-mode clock-data-recovery (bm-cdr) for 10g-pon |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20040117691A1 (en) * | 2002-12-13 | 2004-06-17 | George Fang | Method and related device for reliably receiving a digital signal |
| KR100531469B1 (en) * | 2003-01-09 | 2005-11-28 | 주식회사 하이닉스반도체 | Analog Delay Lock Loop with store circuit about delay lock |
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| CN102118163A (en) * | 2010-07-20 | 2011-07-06 | 钰创科技股份有限公司 | Double-loop controlled phase-locked loop |
| CN103684440A (en) * | 2012-09-04 | 2014-03-26 | 瑞昱半导体股份有限公司 | Clock and data recovery circuit and clock and data recovery |
| CN106470346A (en) * | 2015-08-18 | 2017-03-01 | 晨星半导体股份有限公司 | There are transport stream processor and the timing alignment apparatus and method of timing alignment functionality |
| CN108233871A (en) * | 2016-12-09 | 2018-06-29 | 格芯公司 | The digital frequency multiplier of local oscillator signal is generated in FDSOI technologies |
| WO2020186647A1 (en) * | 2019-03-20 | 2020-09-24 | Huawei Technologies Co., Ltd. | Improved burst-mode clock-data-recovery (bm-cdr) for 10g-pon |
| CN113169801A (en) * | 2019-03-20 | 2021-07-23 | 华为技术有限公司 | Improved burst mode clock data recovery for 10G-PON |
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